PD - 94099B
SMPS MOSFET
Applications
l Switch Mode Power Supply (SMPS)
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency
Circuits
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Low RDS(on)
IRFP32N50K
HEXFET® Power MOSFET
VDSS
RDS(on)typ.
ID
0.135Ω
32A
500V
TO-247AC
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case )
Mounting torque, 6-32 or M3 screw
Max.
Units
32
20
130
460
3.7
± 30
13
-55 to + 150
A
W
W/°C
V
V/ns
300
°C
10lb*in (1.1N*m)
Avalanche Characteristics
Symbol
EAS
IAR
EAR
Parameter
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
450
32
46
mJ
A
mJ
Typ.
Max.
Units
–––
0.24
–––
0.26
–––
40
°C/W
Thermal Resistance
Symbol
RθJC
RθCS
RθJA
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Parameter
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
1
10/19/04
IRFP32N50K
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
RDS(on)
VGS(th)
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
∆V(BR)DSS/∆TJ
Min. Typ. Max. Units
Conditions
500 ––– –––
V
VGS = 0V, ID = 250µA
––– 0.54 ––– V/°C Reference to 25°C, ID = 1mA
––– 0.135 0.16
Ω
VGS = 10V, ID = 32A
3.0
––– 5.0
V
VDS = V GS, ID = 250µA
––– ––– 50
µA VDS = 500V, VGS = 0V
––– ––– 250
µA
VDS = 400V, VGS = 0V, TJ = 150°C
––– ––– 100
VGS = 30V
nA
––– ––– -100
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
14
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
28
120
48
54
5280
550
45
5630
155
265
Max. Units
Conditions
–––
S
VDS = 50V, ID = 32A
190
ID = 32A
59
nC
VDS = 400V
84
VGS = 10V
–––
VDD = 250V
–––
I
D = 32A
ns
–––
RG = 4.3Ω
–––
VGS = 10V
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 400V
Diode Characteristics
Symbol
IS
ISM
VSD
trr
Qrr
IRRM
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Reverse RecoveryCurrent
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
32
–––
130
A
–––
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = 32A, V GS = 0V
TJ = 25°C, IF = 32A
di/dt = 100A/µs
D
S
––– ––– 1.5
V
––– 530 800
ns
––– 9.0 13.5
µC
––– 30 –––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.87mH, RG = 25Ω,
IAS = 32A,
ISD ≤ 32A, di/dt ≤ 296A/µs, VDD ≤ V(BR)DSS,
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Rθ is measured at TJ approximately 90°C
TJ ≤ 150°C
2
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IRFP32N50K
1000
100
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
100
10
1
5.0V
0.1
5.0V
1
0.1
0.01
1
10
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
0.1
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
TOP
ID, Drain-to-Source Current (A)
I D, Drain-to-Source Current (A)
TOP
10
0.1
100
1
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
1000
TJ = 150° C
10
TJ = 25 ° C
1
0.1
V DS = 50V
20µs PULSE WIDTH
4
5
7
8
9
11
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
100
10
12
3.0
ID = 32A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60
80 100 120 140 160
TJ , Junction Temperature ( ° C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFP32N50K
V GS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds
Crss = Cgd
SHORTED
Coss = Cds + Cgd
10000
C, Capacitance(pF)
20
Ciss
1000
Coss
100
VGS , Gate-to-Source Voltage (V)
100000
ID = 32A
V DS= 400V
V DS= 250V
V DS= 100V
16
12
8
4
Crss
10
0
1
10
100
1000
0
40
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
120
160
200
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
100
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
80
QG , Total Gate Charge (nC)
TJ = 150° C
10
TJ = 25 ° C
10us
100us
10
1
1ms
0.1
0.2
V GS = 0 V
0.6
0.9
1.3
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
100
1
1.6
TC = 25 °C
TJ = 150 °C
Single Pulse
10
10ms
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFP32N50K
35
VGS
30
ID , Drain Current (A)
RD
VDS
D.U.T.
RG
25
+
-VDD
10V
20
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
15
Fig 10a. Switching Time Test Circuit
10
VDS
5
0
90%
25
50
75
100
125
150
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response(Z thJC )
1
D = 0.50
0.1
0.20
0.10
0.05
0.02
0.01
0.01
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
0.001
0.00001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
EAS , Single Pulse Avalanche Energy (mJ)
IRFP32N50K
800
ID
14A
20A
BOTTOM 32A
TOP
640
15V
480
320
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
tp
160
A
0.01Ω
Fig 12c. Unclamped Inductive Test Circuit
0
25
50
75
100
125
150
Starting T J, Junction Temperature ( ° C)
Fig 12a. Maximum Avalanche Energy
Vs. Drain Current
V(BR)DSS
tp
I AS
Fig 12d. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
VGS
.2µF
.3µF
D.U.T.
QGS
+
V
- DS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13a. Gate Charge Test Circuit
6
Charge
Fig 13b. Basic Gate Charge Waveform
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IRFP32N50K
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
+
-
-
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFP32N50K
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
EXAMPLE: T HIS IS AN IRFPE30
WIT H ASSEMBLY
LOT CODE 5657
ASSEMBLED ON WW 35, 2000
IN T HE ASSEMBLY LINE "H"
Note: "P" in assembly line
position indicates "Lead-Free"
PART NUMBER
INT ERNATIONAL
RECTIFIER
LOGO
IRFPE30
56
ASS EMBLY
LOT CODE
035H
57
DATE CODE
YEAR 0 = 2000
WEEK 35
LINE H
This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 10/04
8
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