PD - 95107 IRF3704ZCSPbF IRF3704ZCLPbF Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l Lead-Free HEXFET® Power MOSFET VDSS RDS(on) max 7.9m: 20V Benefits l Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current D2Pak IRF3704ZCSPbF Qg 8.7nC TO-262 IRF3704ZCLPbF Absolute Maximum Ratings Max. Units VDS Drain-to-Source Voltage Parameter 20 V VGS Gate-to-Source Voltage ± 20 g g ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 67 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 47 IDM Pulsed Drain Current PD @TC = 25°C Maximum Power Dissipation 57 PD @TC = 100°C Maximum Power Dissipation 28 TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range c A 260 W 0.38 -55 to + 175 Soldering Temperature, for 10 seconds W/°C °C 300 (1.6mm from case) Thermal Resistance Parameter RθJC RθJA Junction-to-Case Junction-to-Ambient (PCB Mount) f Typ. Max. Units ––– 2.65 °C/W ––– 40 Notes through are on page 11 www.irf.com 1 03/11/04 IRF3704ZCS/LPbF Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units BVDSS Drain-to-Source Breakdown Voltage 20 ––– ––– ∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.014 ––– RDS(on) Static Drain-to-Source On-Resistance ––– 6.3 7.9 ––– 8.9 11.1 V Conditions VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 21A VGS = 4.5V, ID = 17A VGS(th) Gate Threshold Voltage 1.65 2.1 2.55 V ∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -5.6 ––– mV/°C IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA VDS = 16V, VGS = 0V ––– ––– 150 Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V Gate-to-Source Reverse Leakage ––– ––– -100 IGSS gfs Qg VDS = VGS, ID = 250µA VDS = 16V, VGS = 0V, TJ = 125°C VGS = -20V Forward Transconductance 48 ––– ––– Total Gate Charge ––– 8.7 13 Qgs1 Pre-Vth Gate-to-Source Charge ––– 2.9 ––– Qgs2 Post-Vth Gate-to-Source Charge ––– 1.1 ––– Qgd Gate-to-Drain Charge ––– 2.3 ––– ID = 17A Qgodr Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– 2.4 ––– See Fig. 16 Qsw ––– 3.4 ––– Qoss Output Charge ––– 5.6 ––– td(on) Turn-On Delay Time ––– 8.9 ––– tr Rise Time ––– 38 ––– td(off) Turn-Off Delay Time ––– 11 ––– tf Fall Time ––– 4.2 ––– Ciss Input Capacitance ––– 1220 ––– Coss Output Capacitance ––– 390 ––– Crss Reverse Transfer Capacitance ––– 190 ––– e e S VDS = 10V, ID = 17A nC VGS = 4.5V VDS = 10V nC VDS = 10V, VGS = 0V VDD = 10V, VGS = 4.5V e ID = 17A ns Clamped Inductive Load pF VDS = 10V VGS = 0V ƒ = 1.0MHz Avalanche Characteristics EAS Parameter Single Pulse Avalanche Energy IAR Avalanche Current EAR Repetitive Avalanche Energy c d c Typ. ––– Max. 36 Units mJ ––– 17 A ––– 5.7 mJ Diode Characteristics Parameter Min. Typ. Max. Units IS Continuous Source Current ––– ––– ISM (Body Diode) Pulsed Source Current ––– ––– VSD (Body Diode) Diode Forward Voltage ––– trr Reverse Recovery Time ––– Qrr Reverse Recovery Charge ––– 2 c 67 g Conditions MOSFET symbol A D 260 showing the integral reverse ––– 1.0 V p-n junction diode. TJ = 25°C, IS = 17A, VGS = 0V 11 17 ns 2.3 3.5 nC G S e TJ = 25°C, IF = 17A, VDD = 10V di/dt = 100A/µs e www.irf.com IRF3704ZCS/LPbF 1000 1000 VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V 10 ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 100 VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V TOP TOP 3.0V 60µs PULSE WIDTH Tj = 25°C 100 3.0V 10 60µs PULSE WIDTH Tj = 175°C 1 1 0.1 1 0.1 10 1 10 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (Α) 1000.0 T J = 25°C T J = 175°C 100.0 VDS = 10V 60µs PULSE WIDTH 10.0 3.0 4.0 5.0 6.0 7.0 VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 8.0 ID = 42A VGS = 10V 1.5 1.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C) Fig 4. Normalized On-Resistance vs. Temperature 3 IRF3704ZCS/LPbF 10000 12 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd VGS, Gate-to-Source Voltage (V) ID= 17A C, Capacitance (pF) C oss = C ds + C gd Ciss 1000 Coss Crss 8 6 4 2 0 100 1 10 0 100 10 15 20 25 Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 1000.0 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 5 QG Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) 100.0 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 T J = 175°C 10.0 T J = 25°C 1.0 100µsec 10 VGS = 0V 1 0.1 0.0 0.5 1.0 1.5 VSD, Source-toDrain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 VDS= 16V VDS= 10V 10 2.0 1msec Tc = 25°C Tj = 175°C Single Pulse 0 10msec 1 10 100 VDS , Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRF3704ZCS/LPbF 70 2.6 LIMITED BY PACKAGE VGS(th) Gate threshold Voltage (V) ID , Drain Current (A) 60 50 40 30 20 10 0 25 50 75 100 125 150 2.2 ID = 250µA 1.8 1.4 1.0 0.6 175 -75 -50 -25 T C , Case Temperature (°C) 0 25 50 75 100 125 150 175 200 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature Thermal Response ( Z thJC ) 10 1 D = 0.50 0.20 0.10 0.05 0.1 τJ 0.02 0.01 0.01 SINGLE PULSE ( THERMAL RESPONSE ) R1 R1 τJ τ1 τ1 R2 R2 τ2 τ2 R3 R3 τ3 τC τ τ3 Ci= τi/Ri Ci= τi/Ri Ri (°C/W) τi (sec) 0.920 0.000139 0.194 0.000602 0.538 0.001567 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 1E-006 1E-005 0.0001 0.001 0.01 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRF3704ZCS/LPbF 15V + V - DD IAS A 0.01Ω tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp EAS, Single Pulse Avalanche Energy (mJ) D.U.T RG VGS 20V DRIVER L VDS 140 ID 5.6A 8.5A BOTTOM 17A TOP 120 100 80 60 40 20 0 25 50 75 100 125 150 175 Starting T J, Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy vs. Drain Current I AS LD VDS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T Current Regulator Same Type as D.U.T. VGS Pulse Width < 1µs Duty Factor < 0.1% 50KΩ 12V .2µF Fig 14a. Switching Time Test Circuit .3µF D.U.T. + V - DS VDS 90% VGS 3mA 10% IG ID Current Sampling Resistors Fig 13. Gate Charge Test Circuit 6 VGS td(on) tr td(off) tf Fig 14b. Switching Time Waveforms www.irf.com IRF3704ZCS/LPbF D.U.T Driver Gate Drive P.W. + + - - • • • • D.U.T. ISD Waveform Reverse Recovery Current + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period * RG D= VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer Period VDD + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRF3704ZCS/LPbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎠ ⎝ 2 This can be expanded and approximated by; *dissipated primarily in Q1. Ploss = (Irms × Rds(on ) ) 2 ⎛ ⎞ ⎛ Qgs 2 Qgd +⎜I× × Vin × f ⎟ + ⎜ I × × Vin × ig ig ⎝ ⎠ ⎝ ⎞ f⎟ ⎠ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝ 2 ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRF3704ZCS/LPbF D2Pak Package Outline Dimensions are shown in millimeters (inches) D2Pak Part Marking Information (Lead-Free) T H IS IS AN IR F 5 3 0 S W IT H L OT COD E 8 0 24 AS S E M B L E D O N W W 0 2 , 2 0 0 0 IN T H E AS S E M B L Y L IN E "L " IN T E R N AT IO N AL R E C T IF IE R L O GO N ote: "P " in as s em bly line pos ition in dicates "L ead-F ree" P AR T N U M B E R F 530S AS S E M B L Y L O T CO D E D AT E C O D E Y E AR 0 = 2 0 0 0 WE E K 02 L IN E L OR IN T E R N AT IO N AL R E C T IF IE R L OGO AS S E M B L Y L O T COD E www.irf.com P AR T N U M B E R F 530S D AT E C O D E P = D E S IG N AT E S L E AD -F R E E P R O D U CT (O P T IO N AL ) Y E AR 0 = 2 0 0 0 WE E K 02 A = AS S E M B L Y S IT E C O D E 9 IRF3704ZCS/LPbF TO-262 Package Outline IGBT 1- GATE 2- COLLECTOR 3- EMITTER TO-262 Part Marking Information EXAMPLE: T HIS IS AN IRL3103L LOT CODE 1789 AS S EMBLED ON WW 19, 1997 IN THE AS S EMBLY LINE "C" Note: "P" in ass embly line pos ition indicates "Lead-Free" INTERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C OR INTERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE 10 PART NUMBER DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 7 = 1997 WEEK 19 A = AS S EMBLY S IT E CODE www.irf.com IRF3704ZCS/LPbF D2Pak Tape & Reel Infomation Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) FEED DIRECTION 1.85 (.073) 1.60 (.063) 1.50 (.059) 11.60 (.457) 11.40 (.449) 1.65 (.065) 0.368 (.0145) 0.342 (.0135) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 1.75 (.069) 1.25 (.049) 10.90 (.429) 10.70 (.421) 4.72 (.136) 4.52 (.178) 16.10 (.634) 15.90 (.626) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 0.25mH, RG = 25Ω, IAS = 17A. Pulse width ≤ 400µs; duty cycle ≤ 2%. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 This is applied to D2Pak, when mounted on 1" square PCB (FR4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 42A. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 03/04 www.irf.com 11