INFINEON TLE5010

P reli mi nary Dat a Sheet, V 0.9, Ma y 2007
TLE5010
D
ra
ft
GMR B a sed A ng u lar S en s or
Se n so rs
Edition 2007-05
Published by
Infineon Technologies AG
81726 München, Germany
© 2007 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TLE5010
Draft
Revision History:
2007-05
Previous Version:
-
Page
V 0.9
Subjects (major changes since last revision)
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15
TLE5010
Draft
1
1.1
1.2
1.3
1.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
GMR Voltage Regulator VRG (VDDG-Voltage) . . . . . . . . . . . . . . . . . 10
Analog Voltage Regulator VRA (VDDA-Voltage) . . . . . . . . . . . . . . . . 10
Digital Voltage Regulator VRD (VDDD-Voltage) . . . . . . . . . . . . . . . . 10
GMR Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
5.1
5.2
5.3
Electrical and Magnetic Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Offset and Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Amplitude Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Offset Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature dependent behavior . . . . . . . . . . . . . . . . . . . . . . . . . . .
Orthogonality Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calibration Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Angle Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Components of the Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR Error Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature dependent Offset Value . . . . . . . . . . . . . . . . . . . . . . . .
Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Amplitude Normalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Orthogonality Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resulting Angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Anisotropy Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hysteresis Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Residual Angle Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR Parameters after Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
5.5
5.5.1
5.5.2
5.6
5.7
Preliminary Data Sheet
4
6
6
7
7
8
15
15
16
17
17
18
18
18
19
19
19
19
19
20
20
20
20
21
21
21
21
22
22
22
22
23
V 0.9, 2007-05
TLE5010
Draft
6
Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Clock Supply (CLK Timing Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
8.1
Synchronous Serial Communication Interface (SSC) . . . . . . . . . . . . .
SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Spike Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Spike Filter Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Spike Filter On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Filter for DATA and CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Command Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
8.3
8.3.1
8.3.2
8.4
8.5
26
27
27
30
30
30
31
31
32
32
9
Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reserved Registers (08H to 0BH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10
10.1
10.2
Data Communication via SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Active Byte Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example: Update X and Y and set ADC-Test Mode . . . . . . . . . . . . .
43
44
44
45
11
11.1
11.2
11.3
Test Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Angle Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Angle Test and Temperature Measurement Timing . . . . . . . . . . . . . . . . .
46
46
47
47
48
12
12.1
12.2
12.3
12.4
Overvoltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Supply Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDD Overvoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDD - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
49
49
50
50
13
13.1
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Angle Sensor System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
14
14.1
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Footprint PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Data Sheet
5
52
52
53
54
54
54
55
V 0.9, 2007-05
Draft
GMR Based Angular Sensor
1
Overview
1.1
Features
TLE5010
• Giant MagnetoResistance based principle
• Integrated magnetic field sensing for angle
measurement
• Full 0 - 360° angle measurement
• Highly accurate single bit SD-ADC
PG-DSO-8-3
• 16 bit representation of sine / cosine values on the
interface
• Bidirectional SSC interface up to 2 Mbit/s
• 3 pin SSC interface, SPI compatible with open drain
• ADCs and filters are synchronized with external commands via SSC
• Test resistors for simulating angle values
• Core supply voltage 2.5 V
• 0.25 µm CMOS technology
• Automotive qualified: -40°C to +150°C (Junction Temperature)
• Latch up immunity according JEDEC standard
• ESD > 2 kV (HBM)
• Green package with lead-free plating
Type
TLE5010
Marking
5010-2
Preliminary Data Sheet
Ordering Code
tbd.
6
Package
PG-DSO-8
V 0.9, 2007-05
TLE5010
Draft
Overview
1.2
Target Applications
Angular position sensing in automotive applications like:
•
•
•
•
Steering Angle
Brushless DC Motor Commutation (e.g. EPS)
Rotary Switch
General Angular sensing in automotive applications
1.3
Product Description
The TLE5010 is a 360° angle sensor, which detects the orientation of a magnetic field.
This is achieved by measuring sine and cosine angle components with monolithic
integrated GMR elements (Giant Magnetic Resistance).
Data communication is done with a bi-directional SSC interface (SPI compatible).
The sine and cosine values can be read out. These signals can be digitally processed
to calculate the angle orientation of the magnetic field (magnet). This calculation can be
done by using a cordic algorithm.
It is possible to connect more than one TLE5010 to one SSC Interface of a µC for
redundancy or any other reasons.
In this case the synchronization of the connected TLE5010 is done by a broadcast
command.
Each connected TLE5010 can be addressed by a dedicated chip select CS pin.
Online diagnostic functionalities are provided to ensure a reliable operation.
These are
•
•
•
•
Angle Test (generated via test voltages feeding the ADC).
Crossed signal paths (switchable for comparison)
Inverted signs of bit streams
Over and undervoltage detections
Preliminary Data Sheet
7
V 0.9, 2007-05
TLE5010
Draft
1.4
Overview
Pin Configuration (top view)
8
7
6
5
1
2
3
4
Center of
Sensitive Area
Figure 1
Pin Configuration
Table 1
Pin Definitions and Functions
Pin No.
Symbol
In/Out
Function
1
CLK
I
Chip Clock
2
SCK
I
SSC Clock
3
CS
I
SSC Chip Select
4
DATA
I/O
SSC Data, open drain
5
TST1
I/O
Test Pin 1, must be connected to GND
6
VDD
-
Supply voltage
7
GND
-
Ground
8
TST2
I/O
Test Pin 2, must be connected to GND
Preliminary Data Sheet
8
V 0.9, 2007-05
TLE5010
Draft
General
2
General
2.1
Functional Description
The clock for the sensors will be provided by external. This ensures a synchronously
operation in case of multiple system participants.
The sensor has its own PLL to generate the necessary clock frequency for the chip
operation.
2.2
Block Diagram
The block diagram shows all switches in reset position.
GND
VDD
GND-off
Comp
VDD_max
TST1
VDD_O V
Comp
V DD-off
Comp
CLK
SCK
SCK
V RG VRG _OV VRG _Rst
V RA
V RA_OV
V RA_Rst
VRD
SSC
VRD_OV V RD_Rst
DA TA
CS
Angle
V oltage
GMR X
Temperature
Sensor
V DDG
A
D
2
1
GND
Comb
Filter 16
FS YNC
FIR
Filter 16
XH
XL
Control
FSM
FCNT
V DDG
A
D
2
GND
1
Comb 16
Filter
FIR 16
Filter
YH
YL
A ngle
Voltage
GMR Y
Analog Clock
Digital Clock
2
V RG_Rst
VRA_Rst
VRD_Rst
differential
TLE5010
Reset
P LL
CLK
Lock
Digital Reset
TS T1
Figure 2
TST2
Block Diagram
Preliminary Data Sheet
9
V 0.9, 2007-05
TLE5010
Draft
2.3
General
Internal Power Supply
The internal stages of the TLE5010 are supplied with different voltage regulators. Each
voltage regulator has its own over- and undervoltage detection circuits.
GMR Voltage Regulator VRG (VDDG-Voltage)
The GMR voltage regulator supplies all GMR parts.
• GMR Bridges
• Test Voltages for Angle Test
• ADC Reference Voltage
The voltages are monitored in the VRG over- and undervoltage detectors.
Analog Voltage Regulator VRA (VDDA-Voltage)
The analog voltage regulator supplies the analog parts.
•
•
•
•
•
ADCs
PLL (analog)
VDD-Off comparator
GND-Off comparator
VDD Overvoltage detection
The voltages are monitored in the VRA over- and undervoltage detectors.
Digital Voltage Regulator VRD (VDDD-Voltage)
The digital voltage regulator supplies all digital parts.
•
•
•
•
•
Comb filters, FIR filters and Low Pass filter
PLL (digital)
Control FSM with Bitmap
SSC -Interface
Counters (Reset, FSYNC, FCNT)
The voltages are monitored in the VRD over- and undervoltage detectors.
Preliminary Data Sheet
10
V 0.9, 2007-05
TLE5010
Draft
2.4
General
GMR Functionality
The GMR sensor is implemented in vertical integration. This means, that the GMR active
areas are integrated above the logic part. GMR elements change their resistance
depending on the direction of the magnetic field.
4 individual GMR elements are connected to one Wheatstone sensor bridge.
They sense either the
• X component, VX (cosine) or the
• Y component, VY (sine)
of the applied magnetic field.
The advantage of a full-bridge structure is that the GMR signal amplitude is doubled.
90°
GMR Resistors
S
0°
VX
N
ADCX+
Figure 3
1)
VY
ADCX -
GND
ADCY+
ADCY -
V DDG
Sensitive bridges of the GMR Sensor1)
The arrows in the resistor symbols show the direction of the reference layer
Preliminary Data Sheet
11
V 0.9, 2007-05
TLE5010
Draft
General
The output signal of each bridge is only unambiguous over 180° between two maxima.
Therefore two bridges are orientated orthogonal to each other.
Using the ARCTAN function, the true 360° angle value can be calculated which is
represented by the relation of the X and Y signals.
As only the relative values influence the result, the absolute size of the two signals is of
minor importance. Therefore most influences to the amplitudes are compensated.
Y Component (SIN)
VY
X Component (COS)
VX
V
VX (COS)
0°
90°
180°
270°
360°
Angle α
VY (SIN)
Figure 4
Ideal Output of the GMR Sensor
Preliminary Data Sheet
12
V 0.9, 2007-05
TLE5010
Draft
3
Table 2
Absolute Maximum Ratings
Absolute Maximum Ratings
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
min.
Unit
Notes
max.
Voltage on VDD pin
respect to ground (VSS)
VDD
-0.5
6.5
V
max 40 h / lifetime
Voltage on any pin
respect to ground (VSS)
VIN
-0.5
6.5
V
VDD + 0.35 V may
Junction Temperature
not be exceeded
TJ
Magnetic Field Induction B
-40
150
-
|125|
-
|80|
°C
mT
max 5 min. @
tA = 25°C
max 5 h @
tA = 25°C
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDD or VIN < GND)
the voltage on VDD pins with respect to ground (GND) must not exceed the values
defined by the absolute maximum ratings.
Preliminary Data Sheet
13
V 0.9, 2007-05
TLE5010
Draft
Operating Range
4
Operating Range
The following operating conditions must not be exceeded in order to ensure correct
operation of the TLE5010.
All parameters specified in the following sections refer to these operating conditions,
unless otherwise noticed.
Table 3
Operating Range ( - 40°C < TJ < 150°C )
Parameter
Supply Voltage
Output Current
Input Voltage
Symbol
VDD
IQ
VIN
Limit Values
Unit
Notes
min.
typ.
max.
4.5
-
5.5
V
1)
-
-5
-10
mA
2) 3)
-0.3
-
5.5
V
VDD + 0.5 V may not
be exceeded
Magnetic Induction BXY
25
30
45
mT
In X / Y direction4)
Angle Range
Ang
TST
0
-
360
°
sine / cosine
-40
-
50
°C
tlife
-
-
15
Years
Storage
Temperature
Overall Life Time
1)
Directly blocked with 100 nF ceramic capacitor
2)
Max current to GND over Open Drain Output
3)
The corresponding voltage levels are listed in Table 5 "Electrical Parameters for 4.5V < VDD < 5.5V" on
Page 16
4)
Values refer to an homogenous magnetic field (Bxy) without vertical magnetic induction (Bz = 0 mT). By
applying a vertical magnetic induction an additional error has to be considered
Note:
For a calculation of the corresponding ambient temperature the thermal
resistances in Table 20 "Package Parameters" on Page 51 have to be used.
Preliminary Data Sheet
14
V 0.9, 2007-05
TLE5010
Draft
Electrical and Magnetic Parameters
5
Electrical and Magnetic Parameters
5.1
Electrical Parameters
These are all parameters over operating range, unless otherwise specified.
Unless individually specified, typical values correspond to a supply voltage VDD = 5.0 V
and 25°C.
All other values correspond to - 40°C < TJ < 150°C
Table 4
Electrical Parameters
Parameter
Supply Current
Symbol Limit Values
1)
POR Level
POR Hysteresis
Power On Time
PLL Jitter
ADC Noise 5)
Unit
Notes
mA
VDD = 4.5 to 5.5V
VDD = 6.5 V
Power On Reset
min.
typ.
max.
-
15
20
-
-
21
VPOR
2.0
VPORhy tPon
50
2.3
2.9
V
30
-
mV
100
200
µs
VDD > VDDmin & after
first edge on fCLK
tPLLjit_S tPLLjit_L
NADC
-
1.3
2.0 2)
ns
short term
3.0
3.9
long term 4)
1
2.2
digits 1 σ @ FIR_BYP = 0
-
2
4.42)
IDD
3)
1 σ @ FIR_BYP = 1
Input Signal
Low Level
VL
-0.35
-
0.3 VDD
V
Input Signal
High Level
VH
0.7 VDD
-
VDD
+0.35
V
Tested only at DATA
pin as structures of
all pins are identical
Capacitance of
SSC Data Pin
CLDATA -
4
6 2)
pF
Internal
1)
Without external pull-up resistor for SSC-Interface
2)
Not tested
3)
From pulse to pulse
4)
Accumulated over 1 ms
5)
ADC noise in respect to the peak ADC value specified in “Signal Processing” on Page 23.
Noise tested using 1 σ of 100 sample values from Angle Test “000”
Preliminary Data Sheet
15
V 0.9, 2007-05
TLE5010
Draft
Electrical and Magnetic Parameters
..
Electrical Parameters for 4.5V < VDD < 5.5V
Table 5
Parameter
Symbol Limit Values
min.
VHY
Pull-Up Current
IPU
Pull-Down Current IPD
Input Hysteresis
Output Signal
Low Level
1)
VOL
typ.
Unit
Notes
max.
0.07 VDD -
-
V
-10
-
-150
µA
CS, DATA
15
-
225
µA
SCK, CLK
15
-
225
TST1
10
-
150
TST2
-
-
0.7
0.4
IQ = - 10 mA
IQ = - 5 mA 1)
V
The value -5 mA is not tested
5.2
ESD Protection
Table 6
ESD Protection
Parameter
Symbol
Limit Values
min.
ESD Voltage
VHBM
VCDM
Unit
Notes
max.
-
±2
kV
HBM 1)
-
± 500
V
CDM
2)
1)
Human Body Model (HBM) according to: JEDEC EIA/JESD22-A114-B (R = 1.5 kΩ, C = 100 pF, TA = 25°C)
2)
Charge Device Model (CDM) according to: ANSI ESD STM JEDEC JESD 22-C101-A Class III.
Preliminary Data Sheet
16
V 0.9, 2007-05
TLE5010
Draft
5.3
Electrical and Magnetic Parameters
GMR Parameters
All parameters over operating range, unless otherwise specified.
Table 7
Basic GMR Parameters
Parameter
Symbol Limit Values
min.
X, Y Output range
X, Y Amplitude 1)
X, Y Synchronism
X; Y Offset
2)
3)
X, Y Orthogonality
Error
Notes
typ.
max.
RGADC AX, AY 7402
-
±23230 digits
12337
15781
3922
-
20620
k
80
100
120
%
OX, OY
-3000 0
3000
digits @ Calib. Conditions
ϕ
-10.0
10.0
°
X0, Y0
X,Y without field
Unit
0
-5000 -
5000
1)
See Figure 4, Page 12
2)
k = 100 x ( AX / AY ).
3)
OSIN = ( YMAX + YMIN ) / 2 ; OCOS = ( XMAX + XMIN ) / 2
4)
Not tested.
digits @ Calib. Conditions
Operating Range
@ Calib. Conditions
@ Calib. Conditions
digits without magnet4)
Offset and Amplitude
VY
+A
0°
90°
180°
0
Offset
270°
360°
Angle
-A
Figure 5
Offset and Amplitude Definition
Preliminary Data Sheet
17
V 0.9, 2007-05
TLE5010
Draft
Electrical and Magnetic Parameters
Amplitude Definition
The amplitude is defined as half difference between the signed maximum and minimum
values of the idealized (fitted) sine or cosine wave.
X MAX – X MIN
A X = --------------------------------AY
2
Y MAX – Y MIN
= -------------------------------2
Offset Definition
The offset of the X and Y signals is defined as the mean value between the signed
maximum and minimum values of the idealized (fitted) sine or cosine wave.
OX
OY
X MAX + X MIN
--------------------------------=
2
Y MAX + Y MIN
= --------------------------------2
Temperature dependent behavior
The temperature offset gradients for both channels depend on the value at 25°C. It can
be calculated using following linear equations:
KT OX = tco_d_x + ( tco_k_x × O X25 )
KT OY = tco_d_y + ( tco_k_y × O Y25 )
OX25, OY25: Offset values at 25°C in digits.
.
Table 8
GMR Temperature Coefficients
Parameter
Symbol
Limit Values
min.
Unit
typ.
max.
Offset Temperature
Coefficient base
tco_d_x -
+0.116296
-
tco_d_y -
-0.079401
-
Offset Temperature
Coefficient gain
tco_k_x -
-0.0010147
-
tco_k_y -
-0.0010121
-
Preliminary Data Sheet
18
Notes
digits_/_K
1_/_K
V 0.9, 2007-05
TLE5010
Draft
Electrical and Magnetic Parameters
Orthogonality Definition
The corresponding maximum and zero crossing points of the SIN and COS signals are
not exactly in a distance of 90°. The difference between X and Y phase is called
’Orthogonality Error’.
ϕ = ϕX – ϕY
jideal = 0°
jX : Phase error of X (= cos) Signal
jY : Phase error of Y (= sin) Signal
5.4
Calibration
GMR Values
The end-of-line calibration can be done using following sequence.
The conditions are specified in Table 9.
•
•
•
•
•
•
Turn magnetic field left and measure X and Y values
Calculation of Amplitude, Offset, Phase correction values of left turn
Turn further 90° left and 90° back right without measurement
Turn magnetic field right and measure X and Y values
Calculation of Amplitude, Offset, Phase correction values of right turn
Calculation of mean values of Amplitude, Offset, Phase correction values
The above gained values have to be stored in a non-volatile memory. They are used for
the correction of the read-out X and Y values before the angular calculation.
The resulting angular deviation is calculated using above determined parameters.
Temperature Measurement
The signal amplitude T25 of the temperature measurement path at calibration conditions
has to be measured and stored.
Calibration Conditions
All errors are related to a calibration done using following conditions:
Table 9
GMR calibration conditions
Parameter
Flux density
Temperature
Preliminary Data Sheet
Symbol Limit Values
BCAL
TCAL
Unit
Notes
BZ = 0 mT
min.
typ.
max.
-
30
-
mT
-
25
-
°C
19
V 0.9, 2007-05
TLE5010
Draft
Electrical and Magnetic Parameters
5.5
Angle Calculation
5.5.1
Components of the Output Signals
The X and Y signals at the output can be described with following equations:
X = A X × cos ( α + ϕ X ) + O X
Y = A Y × sin ( α + ϕ Y ) + O Y
AX : Amplitude of X (= cos) Signal
OX : Offset of X (= cos) Signal
AY : Amplitude of Y (= sin) Signal
OY : Offset of Y (= sin) Signal
ϕX : Phase error of X (= cos) Signal
ϕY : Phase error of Y (= sin) Signal
5.5.2
GMR Error Compensation
Temperature dependent Offset Value
To increase the accuracy, the temperature dependent offset drift can be compensated.
The temperature of the chip has to be read out. The Offset values OX and OY have to
be multiplied with the Offset temperature coefficient and the temperature value.
KT OX
O X = O X25 + -------------- × ( T – T 25 )
S
T
KT OY
O Y = O Y25 + -------------- × ( T – T 25 )
S
T
OX25 , OY25 : Offset value at 25°C in digits
T25 : Temperature value at 25°C in digits
T : Temperature value in digits
ST : Sensitivity of the temperature measurement path, (see chapter “Temperature
Measurement” on Page 46).
Preliminary Data Sheet
20
V 0.9, 2007-05
TLE5010
Draft
Electrical and Magnetic Parameters
Offset Correction
After read-out of the X and Y value first the temperature corrected offset value has to be
subtracted.
X 1 = X – OX
Y1 = Y – OY
Amplitude Normalization
Then the X and Y values are normalized using the peak values determined in the
calibration.
X
1
X 2 = ------
AX
Y1
Y 2 = -----AY
Non-Orthogonality Correction
The influence of the non-orthogonality can be compensated using following equation.
Only the Y channel has to be corrected.
Y 2 – X 2 × sin ( – ϕ )
Y 3 = -------------------------------------------
cos ( – ϕ )
Resulting Angle
After correction of all errors, the resulting angle can be calculated using the arctan
function1).
Y3
α = arc tan  ------ – ϕ X
 X 2
1)
µC-function “arctan2(Y3,X2)” to resolve 360°
Preliminary Data Sheet
21
V 0.9, 2007-05
TLE5010
Draft
5.6
Electrical and Magnetic Parameters
GMR Parameters after Calibration
After calibration under the conditions specified in Table 9 "GMR calibration
conditions" on Page 19, the sensor has following remaining error:
The error value refers to BZ = 0 mT and operating conditions given in Table 3
"Operating Range ( - 40°C < TJ < 150°C )" on Page 14.
Table 10
GMR parameter with temperature dependent offset compensation
Parameter
Symbol
Limit Values
min. typ.
Unit Notes
max.
1)
Overall Error
1)
At 25°C, B=30mT
2)
incl. hysteresis error
3)
At 0h
Preliminary Data Sheet
-
0.7
22
2,0
°
2) 3)
V 0.9, 2007-05
TLE5010
Draft
6
Signal Processing
Signal Processing
Table 11
Signal Processing
Parameter
Symbol Limit Values
Internal Cutoff
Frequency (-3dB)
of sin or cos Value
fCut-Off
Update Time of
sin or cos Value2)
tupd
Settle Time
3)
Peak ADC Output
value
min.
typ.
-
4.9
1)
Unit
Notes
kHz
FIR_BYP=0
max.
-
19.6
tsettle
ADCPk
FIR_BYP=1
-
81,9
-
µs
FIR_BYP=0
-
20,5
-
FIR_BYP=1
-
163,8
-
FIR_BYP=0
-
41,0
-
FIR_BYP=1
-
-
23230
digits signed 16 bit
integer (2s
complement) 4) 5)
6)
1)
For 4 Mhz input frequency
2)
tupd = 8192 / (25 x fCLK) for FIR_BYP = 0
tupd = 8192 / (100 x fCLK) for FIR_BYP = 1
3)
tsettle = 2 x tupd , after change of ADC input source
4)
Output values are valid up to this limit. Above it, corrupted results may occur due to non-linearity of the ADC.
5)
The internal quantization is typically 5.166 µV per digit.
6)
Correspond to max. GMR output value.
Preliminary Data Sheet
23
V 0.9, 2007-05
TLE5010
Draft
7
Clock Supply (CLK Timing Definition)
Clock Supply (CLK Timing Definition)
The clock signal input “CLK” must fulfill certain requirements which are described in the
following:
• The high or low pulse width must not exceed the specified values, because the PLL
needs a minimum pulse width and must be spike filtered.
• The duty cycle factor should be 0.5 but can deviate to the values limited by tCLKh(f_min)
and tCLKl(f_min).
• The PLL is triggered at the positive edge of the clock. If more than 2 edges are
missing, a chip reset is generated automatically.
tCLK
tCLKh
tCLKl
VH
VL
t
Figure 6
CLK Timing Definition
Table 12
CLK Timing Specification
Parameter
Symbol
fCLK
CLK Duty Cycle 1)
CLKDUTY
CLK rise time
tCLKr
CLK fall time
tCLKf
PLL Frequency
fPLL
Digital Clock
fDIG
Digital Clock Periode tDIG
Input Frequency
1)
Limit Values
Unit
Notes
min.
typ.
max.
3.9
4.00
4.2
MHz
30
50
70
%
-
-
20
ns
from VL to VH
-
-
20
ns
from VH to VL
-
100
-
MHz
fCLK * 25
-
25
-
MHz
( 25 / 4 ) * fCLK
-
40
-
ns
4 / (25 * fCLK)
Minimum duty cycle factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min) = 1 / fCLK(f_min)
Maximum duty cycle factor: tCLKh(f_max) / tCLK(f_min) with tCLKh(f_max) = tCLK(f_min) - tCLKl(min)
Preliminary Data Sheet
24
V 0.9, 2007-05
TLE5010
Draft
Synchronous Serial Communication Interface (SSC)
8
Synchronous Serial Communication Interface (SSC)
The 3 pin synchronous serial interface (SSC) has a bidirectional data line (open drain),
serial clock signal and chip select.
It is designed to communicate with a micro controller with bidirectional SSC interface
supporting Open Drain. Other micro controllers may require an external NPN transistor.
This allows communication with SPI compatible devices.
µC
(SSC Master)
TLE 501x
(SSC Slave)
typ. 1k Ω
DATA
Shift Register
*)
SCK
*)
DATA
Shift Register
*)
SCK
*)
Clock Generator
Figure 7
CS
CS
*) optional , e.g. 100 Ω
SSC Half-Duplex Configuration for µC with Open Drain support
µC
(SSC Master)
Shift Register
typ. 1kΩ
MRST
TLE 501x
(SSC Slave)
*)
*)
MTSR
DATA
Shift Register
optional
*)
SCK
SCK
*)
Clock Generator
Figure 8
CS
CS
*) optional , e.g. 100 Ω
SSC Half-Duplex Configuration for µC without Open Drain support
Preliminary Data Sheet
25
V 0.9, 2007-05
TLE5010
Draft
8.1
Synchronous Serial Communication Interface (SSC)
SSC Timing Definition
SSC Timing Diagram
tSCKp
tCSs
tSCKh
tCSh
tSCKl
tCSoff
CS
VH
VL
SCK
VH
VL
DATA
VH
VL
tDATr
Figure 9
tDATw
SSC Timing Definition
• SSC Inactive Time ( CSoff )
The SSC inactive time defines the delay, before the TLE5010 can be selected again
after a transfer. The TLE5010 reacts only to one command after SSC inactive time.
Then the SSC Interface of the TLE5010 is disabled until the next SSC Inactive Time
is performed.
• DATA Write Time ( tDATW )
During this time the TLE5010 changes the data line, thus the data are invalid.
The DATA Write Time values are defined without pull-up resistor.
• Pull-up Time Value ( tPU )
The value in Table 13 "SSC Timing Specification" on Page 27 is estimated with
60 ns.
• Chip Select Off time ( tCSOFF )
Preliminary Data Sheet
26
V 0.9, 2007-05
TLE5010
Draft
Table 13
Synchronous Serial Communication Interface (SSC)
SSC Timing Specification 1)
Parameter
SSC Baud Rate
Symbol Limit Values
fSSC
Unit
min.
typ. max.
-
2.0
2.12)
MBit /
s
tCSs
CS Hold Time
tCSh
CSoff
tCSoff
SCK High
tSCKh
SCK Low
tSCKl
DATA Read Time tDATr
3*tDIG+10 -
-
ns
5*tDIG+10 -
-
ns
10*tDIG
-
-
ns
5*tDIG
-
-
ns
5*tDIG
-
-
ns
6*tDIG-10
-
7*tDIG+10
ns
(Data Valid Time)
5*tDIG-10
-
7*tDIG+10
tDATw
6*tDIG+25 -
7*tDIG+50
+ tPU
ns
tDATs
-
30 4)
ns
CS Setup Time
DATA Write Time
(Data Valid Time)
3)
DATA slope
20
Notes
SSC inactive time
SSC_FILT = 0
SSC_FILT = 1
Falling edge 5)
1)
Timings have to be calculated acc. Table 12 "CLK Timing Specification" on Page 24.
2)
fCLK/2, synchronized to fCLK if fCLK = fCLK(max)
3)
tPU is the time generated by the pull-up resistor
4)
Not tested.
5)
Internal slope control of falling edge for data bit transition from VH to VL.
Preliminary Data Sheet
27
V 0.9, 2007-05
TLE5010
Draft
Synchronous Serial Communication Interface (SSC)
t SCKl MIN
t SCKh
SCK
t DATw MIN
Wr
t DATw MAX
S SC_FILT=0
tPU
Earliest sample timepoint
t DATr MIN
Rd
t DATr MAX
SCK
t DATw MIN
Wr
t DATw MAX
SSC_FILT=1
tPU
tDATr MIN
t DATr MAX
Figure 10
Earliest sample timepoint of
second sample from 2 of 3 filter
Rd
SSC Interface Timing Details with worst-case specified Timing
Note:
– The read window includes the sampling of the data bit.
– For SSC_FILT = 1, the 2-of-3 selection is already regarded.
Only the 2 last data values have to be equal.
– For SSC_FILT = 0 only one sample point is selected.
Preliminary Data Sheet
28
V 0.9, 2007-05
TLE5010
Draft
Synchronous Serial Communication Interface (SSC)
The margin time in following table is the time between write access to the SSC Data Line
and the earliest possible sample read of the TLE5010 itself for read back.
It is useful to have a maximum distance between WRITE and subsequent READ. This
ensures a reliable read back of the written data for the Slave-Active Byte generation.
Table 14
Maximum Pull-up Time Margin with worst-case specified Timing
SSC_FILT
0
1
1)
Min. tPU Margin 1)
90
50
SSC_TIMING
don’t care
Unit
ns
Comment
Calculation: Margin=tSCKl(min)+tDATwMAX -(tPU)-tDATrMIN.For Margin<50 ns no problems can occur.
8.2
SSC Baud rate
The SSC Baud rate depends on the internal clock frequency.
12 internal digital clock cycles are necessary to ensure a reliable operation.
Therefore the maximum SSC Baud rate depends on the external CLK.
f CLK
f SSC = -----------
2
8.3
SSC Spike Filter
A SSC Spike Filter for all SSC lines can be selected via the SSC_FILT bit.
8.3.1
SSC Spike Filter Off
When the spike filter is disabled, each slope of a rising voltage is used to define a bit.
This is independent of the length of the sampled pulse.
For example a positive spike generates therefore a rising and a falling edge.
Preliminary Data Sheet
29
V 0.9, 2007-05
TLE5010
Draft
8.3.2
Synchronous Serial Communication Interface (SSC)
SSC Spike Filter On
A sliding window with four consecutive sample bits is analyzed.
The sample frequency is:
1
f S = --------------f DIGIT
Rising Edge Detect for SCK
• After a rising edge (LH combination), at least one of the 2 following samples has to be
’high’. Valid bit combinations: 0111 , 0110 , 0101.
• A falling condition has to be detected before.
Falling Edge Detect for SCK
• After a falling edge (HL combination), at least one of the 2 following samples has to
be ’low’. Valid bit combinations: 1000 , 1001 , 1010.
• A rising condition has to be detected before.
)
SCK (PAD)
SCK Fall
)
SCK rise
detected )
)
SCK Rise
SCK fall
detected
Suppressed
Spike
Masked, because
no fall detected
Figure 11
SSC Spike Filter
Filter for DATA and CS
• The DATA pin has a ’2-of-3’ filter.
• The CS input has a ’2-of-3’ filter, which suppresses only positive spikes.
Preliminary Data Sheet
30
V 0.9, 2007-05
TLE5010
Draft
8.4
Synchronous Serial Communication Interface (SSC)
SSC Data Transfer
The following transfer bytes are possible:
•
•
•
•
Command byte (to access and change operating modes of the TLE5010)
Data bytes (any data transferred in any direction)
CRC byte (cyclic redundancy check)
Slave Active byte (response of all selected slaves)
SSC-Master is driving DATA (µC)
SSC-Slave is driving DATA (Sensor)
Command Byte
Data Byte(s)
SCK
DATA
MSB
6
5
4
3
2
1
LSB MSB
6
5
CRC
SlaveActive
4
3
2
1
LSB
CS
DATA
Command Byte
SSC-Master is driving DATA (µC)
Figure 12
8.5
Data
SSC-Slave is driving DATA (Sensor)
SSC Data Transfer (Data Read Example)
SSC Command Byte
The TLE5010 is controlled by a command byte. It is sent first at every data transmission.
Table 15
Structure of the Command Byte
Name
RW
Bits
[7]
ADDR
[6..3]
ND
[2..0]
Preliminary Data Sheet
Description
Read - Write
’0’ = write, ’1’ = read
Address to be read / written
’0..15’ - register start address (address auto increment)
Number of data bytes
’0..7’ - number of data bytes to be transferred
31
V 0.9, 2007-05
TLE5010
Draft
Register Table
9
Register Table
This chapter defines the complete address range as well as all registers of the TLE5010.
It also defines the read/write access rights of the specific registers. In the following table
values through symbols are listed. Access to the registers is done via the SSC interface.
Table 16
Address Map
Addr. Name
00H
01H
02H
03H
04H
05H
06H
CTRL1
Bits
7
-
XL
XH
YL
YH
FCNT_
STAT
FSYNC_ FILT_
INV
INV
07H
ANGT
08H
09H
0AH
0BH
-
0CH
TST
0DH
0EH
ID
LOCK
0FH
CRTL2
-
6
5
-
4
-
-
Preliminary Data Sheet
1
-
0
AUTO UR
XLow
XHigh
YLow
YHigh
STAT_ GMR_
UPDATE
VR
OFF
FCNT
FSYNC
ANGT_
EN
ANGT_Y
reserved
reserved
reserved
reserved
FILT_ FILT_
CRS
BYP
TEMP_
FILT_
ADCPY
EN
PAR
DEV_ID
VDD_
OV
3
2
SSC_
FILT
VDD_
OFF
LOCK
VRG_ VRA_
OV
OV
GND_
OFF
32
ANGT_X
TST_ TST_ TST_
ADC
GMR CHAN
REV_ID
VRD_
OV
S_NO
V 0.9, 2007-05
TLE5010
Draft
Register Table
Bit Types
Abbreviation
Function
Description
L
Locked
Locked register.
These registers can only be written, when the unlockvalue is written in the lock register (0EH).
This ensures, that these bits cannot be modified
unwanted during normal operation.
U
Update
Update-Buffer is for this bit is present.
In case of an Update Command and the UpdateMode bit (UR in CTRL1) is set, the immediate values
are stored in this Update-Buffer simultaneous.
This enables a snapshot of all necessary system
parameters at the same time.
S
Status
Reset only after readout
R
Read
Read-only registers
W
Write
Read and write registers
Preliminary Data Sheet
33
V 0.9, 2007-05
TLE5010
Draft
Register Table
CTRL1
Addr: 00H
Reset Value: 01H
7
6
5
reserved
reserved
reserved
-
-
-
4
3
2
reserved SSC_FILT reserved
WL
WL
-
1
0
AUTO
UR
WL
WL
Field
Bits
Type
Description
reserved
7
-
reserved, has to be set to 0
reserved
6
-
reserved, has to be set to 0
reserved
5
-
reserved, has to be set to 0
reserved
4
-
reserved, has to be set to 0
SSC_FILT
3
WL
SSC Digital Spike Filter enable for all SSC lines
( CS, CLK and DATA )
0: Digital SSC Spike filters off
1: Digital SSC Spike filters on (modified timing)
reserved
2
-
reserved, has to be set to 0
AUTO
1
WL
Automatic update at angle tests
0: no automatic update in Angle Test Mode
1: automatic update-command after tsettle,
counters FSYNC and FCNT are reset to “0”.
Then the Angle-Test (ANGT_EN) is automatically
disabled and switches back to normal operation.
Also the UPDATE bit is toggled
UR
0
WL
Update / Run Mode
0: Run Mode (Buffer1 values are immediate values)
1: Update Mode (Buffer2 values are stored values)
Preliminary Data Sheet
34
V 0.9, 2007-05
TLE5010
Draft
Register Table
The values in Register 01H to 04H represent one byte of two’s complement signed 16 bit
integer values.
X_L
Addr: 01H
7
Reset Value: 00H
6
5
4
3
2
1
0
1
0
1
0
1
0
X Low Byte
RU
X_H
Addr: 02H
7
Reset Value: 00H
6
5
4
3
2
X High Byte
RU
Y_L
Addr: 03H
7
Reset Value: 00H
6
5
4
3
2
Y Low Byte
RU
Y_H
Addr: 04H
7
Reset Value: 00H
6
5
4
3
2
Y High Byte
RU
Preliminary Data Sheet
35
V 0.9, 2007-05
TLE5010
Draft
Register Table
FCNT_STAT
Addr: 05H
7
reserved
-
Reset Value: 80H
6
5
4
3
STAT_VR GMR_OFF UPDATE
RS
RU
2
1
0
FCNT
RS
RU
Field
Bits
Type
Description
reserved
7
-
STAT_VR
6
RS
Voltage Regulator Status
This bit is a logical OR combination of Digital, Analog,
GMR and VDDOV Comparator and GNDOFF, and
VDDOFF Comparator outputs.
0: Voltage Supply ok
1: Voltage Supply not ok
GMR_OFF
5
RU
ADC Values are no GMR values
(e.g.: Temperature measurement is active)
This bit indicates, whether GMR values or any other
values are connected to the ADCs. This value is read
back from the multiplexer control signals.
0: X,Y Values are GMR values
1: X,Y Values normally represent temp. measurement
or angle test values. In case of non functional MUX this
bit is set to “1”
UPDATE
4
RU
Update Toggle bit. This bit toggles after every update
(update command or automatic update at angle test)
The bit is independent of 'UR' bit in CTRL1
FCNT
3-0
RU
Frame Counter (4 bit unsigned integer value)
This counter counts every new X,Y value pair coming
out of the data path. (approx. 80µs)
This counter is reset to 0H after any write to FSYNC and
after every change of the ANGT_EN bit. As tsettle time
has to be waited for valid X,Y data, this counter must be
≥ 2H to indicate valid X,Y values. If it overflows, it resets
to 3H to show, that values are still valid.
Note: If FIR_BYP is activated, this counter counts 4
times faster!
Preliminary Data Sheet
36
V 0.9, 2007-05
TLE5010
Draft
Register Table
FSYNC_INV
Addr: 06H
7
Reset Value: 00H
6
5
4
3
FILT_INV
FSYNC
WU
WU
2
1
0
Field
Bits
Type
Description
FILT_INV
7
WU
Filter Input Inversion (to check the digital data path
during operation)
0: Filter Inputs are not inverted
1: Filter Inputs are inverted
FSYNC
6-0
WU
Frame Synchronization (7bit unsigned integer value)
The Filter Update time of approx. 80 µs results from
the filter decimation. The phase of this decimation
can be set and checked by this counter.
If FIR_BYP is activated, this counter overflows at the
value 31D.
ANGT
Addr: 07H
7
Reset Value: 00H
6
5
reserved ANGT_EN
-
W
4
3
2
1
0
ANGT_Y
ANGT_X
W
W
Field
Bits
Type
Description
reserved
7
-
reserved, has to be set to 0
ANGT_EN
6
W
Angle Test Enable
0: Angle Test disable command
1: Angle Test enable command
in this case X and Y values represent resistive test
values, which can be used to simulate angle values
ANGT_Y
5-3
W
ANGT_X
2-0
W
Angle Test X and Y value
see : Table 17 "Functional Angle Test" on Page 45
Preliminary Data Sheet
37
V 0.9, 2007-05
TLE5010
Draft
Register Table
Reserved Registers (08H to 0BH)
The values in these registers are 8 bit unsigned integer values.
The values in addr.8 and addr.9 have to be in reset status.
Reserved
Addr: 08H
7
Reset Value: FFH
6
5
4
3
2
1
0
1
0
Reserved
Reserved
Addr: 09H - 0BH
7
6
Reset Value: 00H
5
4
3
2
Reserved
Preliminary Data Sheet
38
V 0.9, 2007-05
TLE5010
Draft
Register Table
TST
Addr: 0CH
Reset Value: 00H
7
6
TEMP_EN
ADCPY
WL
WL
5
4
3
FILT_PAR FILT_CRS FIR_BYP
WL
WL
WL
2
1
0
TST_ADC TST_GMR
WL
TST_
CHAN
WL
WL
Field
Bits
Type
Description
TEMP_EN
7
WL
Temperature Device Enable
0: Temperature Measurement disabled
1: Temperature Measurement enabled
The X value represents the temperature.
Automatic update mode enabled, if AUTO='1'
ADCPY
6
WL
Y Polarity
0: No inversion of Y bit stream
1: Inversion of Y bit stream (rotating direct. changed)
FILT_PAR
5
WL
Filter switched parallel
0: Filters in normal mode
1: Filters parallel, input selected by TST_CHAN
FILT_CRS
4
WL
Filter switched across
0: Filters in normal mode
1: Filters crossed, X and Y outputs are exchanged
FIR_BYP
3
WL
FIR Filter Bypass
0: No FIR Bypass
1: FIR Bypass
TST_ADC 1)
2
WL
ADC input switch to TST1and TST2
0: No ADC input switch, normal operation
1: ADC input switched to TST1,2, ADC selected by
TST_CHAN 2)
TST_GMR 1)
1
WL
GMR switch to TST1and TST2
0: No GMR switch, normal operation
1: GMR switched to TST1,2 2)
TST_CHAN
0
WL
Test Channel select
0: X channel linked to TST1and TST2
1: Y channel linked to TST1and TST2
1)
Only for test purposes
2)
if TST_ADC and TST_GMR are set to ’1’ at the same time, TST_GMR is forced to 0. TST_ADC has the higher
priority.
Preliminary Data Sheet
39
V 0.9, 2007-05
TLE5010
Draft
Register Table
ID
Addr: 0DH
7
Reset Value: 12H
6
5
4
3
2
1
DEV_ID
DEV_REV
R
R
0
Field
Bits
Type
Description
DEV_ID
7-4
R
Device Identifier
001H: TLE5010 productive chip
DEV_REV
3-0
R
Device Revision (current number)
00H: TLE5010 productive chip, 1st revision (B11)
01H: TLE5010 productive chip, 2nd revision (B21)
02H: TLE5010 productive chip, 3rd revision (B31)
03H: TLE5010 productive chip, 4th revision (B41)
(Referred to errata sheets for further versions)
LOCK
Addr: 0EH
7
Reset Value: 00H
6
5
4
3
2
1
0
1
0
LOCK
W
Field
Bits
Type
Description
LOCK
7-0
W
Lock Byte
≠ 5AH: Lock registers locked
= 5AH: Lock registers unlocked
CTRL2
Addr: 0FH
7
VDD_OV
RS
Reset Value: 00H
6
5
4
VDD_OFF GND_OFF VRG_OV
RS
Preliminary Data Sheet
RS
RS
40
3
2
VRA_OV
VRD_OV
S_NO
RS
RS
WL
V 0.9, 2007-05
TLE5010
Draft
Register Table
Field
Bits
Type
Description
VDD_OV
7
RS
VDD Overvoltage Comparator
0: No VDD Overvoltage occurred
1: VDD Overvoltage occurred
VDD_OFF
6
RS
VDD - Off Comparator
0: No VDD - Off occurred
1: VDD - Off occurred
GND_OFF
5
RS
GND - Off Comparator
0: No GND - Off occurred
1: GND - Off occurred
VRG_OV
4
RS
GMR Voltage Regulator Overvoltage Comparator
0: Voltage ok
1: VRG Overvoltage occurred
VRA_OV
3
RS
Analog Voltage Regulator Overvoltage Comparator
0: Voltage ok
1: VRA Overvoltage occurred
VRD_OV
2
RS
Digital Voltage Regulator Overvoltage Comparator
0: Voltage ok
1: VRD Overvoltage occurred
S_NO
1-0
WL
Slave Number
Used in the SSC protocol
Preliminary Data Sheet
41
V 0.9, 2007-05
TLE5010
Draft
10
Data Communication via SSC
Data Communication via SSC
• The data transmission order is ’MSB first’.
• Data is put on the data line with the rising edge on SCK and read with the falling edge
on SCK.
• The SSC interface is byte aligned. Functions are activated after each transmitted byte.
• A “high” condition on the negated chip select pin (CS) of the selected TLE5010
interrupts the transfer immediately. The CRC calculator is automatically resetted.
• Every access to the TLE5010 with ND (number of data) ≥ 1 is done with address auto
increment.
• After an auto-increment overflow the addresses are beginning from 00H again.
• For every data transfer with ND ≥ 1 a 8 bit CRC byte will be appended by the selected
TLE5010. No CRC byte is sent in a data transfer with ND = 0 (e.g. Update Command).
• After the CRC byte is sent, the bit represented by S_NO is pulled low by the selected
slave in the Slave-Active-Byte (bits [3..0], low nibble). In this way, also broadcastmessages produce an individual feedback of every selected slave. This is necessary
to differentiate the individual TLE5010 slave response, because the CRC byte is
written by both TLE5010 in parallel.
• If the CRC byte on the bus is the same as the internal generated CRC of each
TLE5010, each slave pulls low the dedicated bit in the Slave-Active-Byte (bits [7..4],
high nibble). If not, the bit in the high nibble remains ’1’.
• A write command to address 00H with ND = 0 will update all values inside the
TLE5010, and only in this case the transfer can proceed. Furthermore this command
is add to the CRC-calculation of the following SSC Transfer.
• A command of “0000_0000” is called ’Update Command’.
This command transfers the present immediate values of each register to the update
register. After an Update Command, the CS line need not set and reset again.
• After the CRC and Slave-Active byte have been sent the transfer ends.
The TLE5010 always sends logical “1” and all following sent bits from the SSC Master
are ignored (TLE5010 is in idle mode). To enable data transfers again the chip select
pin (CS) of the TLE5010 has to be deselected for CSoff (see Table 13) once.
• If the update mode is selected (CTRL register, UR = ’1’), all accesses are done to
update registers where update registers are present. Other registers are accessed
directly.
Preliminary Data Sheet
42
V 0.9, 2007-05
TLE5010
Draft
Data Communication via SSC
10.1
CRC Generation
• This CRC is according to the J1850 Bus-Specification of 15.Feb.1994 for Class B
Data Communication.
• Every new transfer resets the CRC generation.
• Every byte of a transfer will be taken into account to generate the CRC (also
the sent command(s)).
• Generator Polynom: X8+X4+X3+X2+1, for the CRC generation the fast CRC
generation circuit is used. (See Figure 13)
• The remainder of the fast CRC circuit is initial set to ’11111111B’.
• Remainder is bit inverted before transmission.
Figure 13 shows the fast CRC Polynom.
The zero extension for initial CRC calculation is included!
Input
xor
&
TX_CRC
1
xor
1
X0
X1
xor
1
X2
xor 1
1
X3
1
X4
1
X5
Serial
CRC
output
1
X6
X7
parallel Remainder
Figure 13
10.2
Fast CRC polynomial division circuit
Slave Active Byte Generation
The position of the ’0’ in a nibble corresponds to the given slave number.
The slave active byte (cccc_nnnn) is made up of a
• low nibble (nnnn). One ’0’ is generated always according to the slave number.
• high nibble (cccc). The ’0’ is only generated, if the readback CRC is correct.
Slave1: S_NO = 0 Ö bit 0 is pulled low
Slave Active Byte: 1110_1110
Slave2: S_NO = 1 Ö bit 1 is pulled low
Slave Active Byte: 1101_1101
Slave3: S_NO = 2 Ö bit 2 is pulled low
Slave Active Byte: 1011_1011
Slace4: S_NO = 3 Ö bit 3 is pulled low
Slave Active Byte: 0111_0111
Example for a communication disturbed by other bus participants:
Slave1: S_NO = 0 Ö bit 0 is pulled low, but the high nibble remains as ’1111’.
> Slave Active Byte: 1111_1110
Preliminary Data Sheet
43
V 0.9, 2007-05
TLE5010
Draft
Data Communication via SSC
Example: Update X and Y and set ADC-Test Mode
Command
Data
00000001
00000101
CRC (init all ‘0’)
00000000
----------------------------------xor 11111111
-------=11111110.0
.
.A
xor 10001110.1
.
.
--------..
.
= 01110000.10
.
.B
xor 1000111.01
.
.
-------.-.
.
= 0110111.110
.
.C
xor 100011.101
.
.
------.--.
.
= 10100.0110
.
.D
xor 10001.1101
.
.
-----.---.
.
= 00101.101101 .
.E
xor 100.011101 .
.
---.------ .
.
= 001.11000001.
.F
xor 1.00011101.
.
---.------ .
.
=.11011100.0
.G
xor.10001110.1
.
.--------..
= 1010010.10
.H
xor 1000111.01
.
-------..
= 10101.1100
.I
xor 10001.1101
.
----.----.
= 100.000100 .J
xor 100.011101 .
---.------ .
=01100100. Remainder
10011011 inverted Remainder
Transmitted Sequence:
Command Data
CRC
00000001 00000101 10011011
Preliminary Data Sheet
44
V 0.9, 2007-05
TLE5010
Draft
11
Test Structures
Test Structures
Two different test signal structures are implemented in the TLE5010. These are:
• Functional angle test. In this case, well-knows signals feed the ADCs.
• Temperature measurement. This is useful to read out the chip temperature for
compensation purposes.
11.1
Functional Angle Tests
It is possible to feed the ADCs with appropriate values to simulate a certain magnetposition and other GMR effects.
The values are generated with resistors on the chip.
Following X / Y ADC values can be programmed:
• 4 points, circle amplitude = 70.7%
(0°, 90°, 180°, 270°)
• 8 points, circle amplitude = 100.0%
(0°, 45°, 90°, 135°,180°, 225°, 270°, 315°)
• 8 points, circle amplitude = 122.1%
(35.3°, 54.7°, 125.3°, 144.7°, 215.3°, 234.7°, 305.3°, 324.7°)
• 4 points, circle amplitude = 141.4%
(45°, 135°, 225°, 315°)
Note: The 100% values correspond to typically 21700 digits and a voltage of ~ 110 mV.
Table 17
Functional Angle Test
Register Bits
X / Y Values (decimal)
min.
typ.
max.
000
-400
0
400
001
14800
15500
16200
010
20700
21700
22700
011
100
32767
1)
-400
0
400
101
-14800
-15500
-16200
110
-20700
-21700
-22700
111
1)
-32768
Not allowed to use.
Preliminary Data Sheet
45
V 0.9, 2007-05
TLE5010
Draft
Test Structures
ADC Test Vectors
Y
122.1%
141.4%
100.0%
0%
X
70.7%
Figure 14
11.2
ADC Test Vectors
Temperature Measurement
An internal bandgap voltage can be used to measure the temperature on the chip.
This may be used to compensate temperature dependent errors.
The temperature value is sent out instead of the X value.
Table 18
Temperature Measurement
Parameter
Value at -40°C
Value at 25°C
Value at 150°C
Temperature Sensitivity
1)
Symbol Limit Values
T-40
T25
T150
ST
Unit
min.
typ.
max.
-
-
+22000 digits
+2550
+5775
+9000
digits
-22000 -
-
digits
-
-
dig / K
-188.75
Notes
1)
Should be used for temperature compensation of offset errors
Preliminary Data Sheet
46
V 0.9, 2007-05
TLE5010
Draft
Test Structures
11.3
Angle Test and Temperature Measurement Timing
The angle test and the temperature readout is based on the same mechanism.
In the Normal Mode, the output path is linked to the angle test or temperature
measurement unit until the mode is terminated.
< tupd
< tupd
tupd
tupd
tupd
tupd
tupd
tupd
FSYNC
(reset)
4
5
0
1
2
0
1
2
ADC&Filter
Val_G4
Val_G5
Val_A0
Val_A1
Val_A2
Val_G0
Val_G1
Val_G2
X[16],Y[16]
Buffer1
Val_G3
Val_G0
Val_G1
FCNT[4]
Val_G4
Val_A0
Val_A1
ANGT_EN
or TEMP_EN
Update
useful
GMR_OFF
Figure 15
No GMR signal available
Measurement in Normal Mode
In the Automatic Mode, the signal is automatically switched back to GMR measurement
after the read-out of one value.
< tupd
tupd
tupd
tupd
FSYNC
(reset)
FCNT[4]
tupd
tupd
tupd
Updated FCNT=2
4
5
0
1
0
1
2
ADC&Filter
Val_G4
Val_G5
Val_A0
Val_A1
Val_G0
Val_G1
Val_G2
X[16],Y[16]
Buffer1
Val_G3
Val_A0
Val_A1
Val_G0
Val_G4
Val_G1
ANGT_EN
or TEMP_EN
automatic!
Update
No GMR signal available
GMR_OFF
Figure 16
Measurement in Automatic Mode
Preliminary Data Sheet
47
V 0.9, 2007-05
TLE5010
Draft
Overvoltage Comparators
12
Overvoltage Comparators
Various comparators monitor the voltage in order to ensure a error free operation.
The overvoltages must be active for at least tDEL to set the test comparator bits in the
SSC Interface registers. This works as digital spike suppression.
Table 19
Test Comparators
Parameter
Symbol Limit Values
VOVG
VOVA
VOVD
VDD Overvoltage VDDOV
GND - Off Voltage VGNDoff
VDD - Off Voltage VVDDoff
Overvoltage
Detection
Spike filter Delay
12.1
tDEL
Unit
min.
typ.
-
2.80 -
V
-
2.80 -
V
-
2.80 -
V
-
6.5
-
V
-
0.54 -
V
-
0.48 -
-
10
Notes
max.
-
VGND_OFF = VGND - VTST1
VVDD_off = VCLK - VDD
or VSCK - VDD
V
µs
The error condition has to be
longer than this value
(min. 256 clocks of fDIG)
Internal Supply Voltage Comparators
Every voltage regulator has an overvoltage comparator to detect a malfunction.
If the nominal output voltage of 2.5 V is larger than VOVG, VOVA and VOVD, then this
overvoltage comparator is activated. It sets the VRx_OV bit.
.
VDDA
-
REF
VDD
VRG
VRA
VRD
+
GND
Figure 17
12.2
10µs
Spike
Filter
xxx_OV
GND
OV Comparator
VDD Overvoltage Detection
This comparator (see Figure 17) monitors the external supply voltage at the VDD pin.
It activates the STAT_VR bit.
Preliminary Data Sheet
48
V 0.9, 2007-05
TLE5010
Draft
12.3
Overvoltage Comparators
GND - Off Comparator
This comparator is used to detect a voltage difference between the GND pin and TST1
(which must be soldered to GND in the application). It activates the STAT_VR bit.
This circuit can detect a disconnection of the Supply GND Pin.
.
VDD
VDDA
VGNDoff
+dV
TST1
GND
-
10µs
Spike
Filter
+
GND_OFF
GND
Figure 18
12.4
GND - Off Comparator
VDD - Off Comparator
This comparator detects a disconnection of the VDD pin supply voltage. In this case the
TLE5010 is supplied by the SCK, CLK and CS input pins via the ESD structures.
It activates the STAT_VR bit.
The retriggerable analog monoflop is necessary because of the not static signal of the
CLK and SCK signals.
This comparator is also activated, if spikes on CLK or SCK achieve the condition:
(VCLK - VDD) > VVDDoff or (VSCK - VDD) > VVDDoff
.
VDDA
-
VDD
1µs
Mono
Flop
VVDDoff
CLK
SCK
-dV
GND
Figure 19
+
10µs
Spike
Filter
VDD _OFF
GND
VDD - Off Comparator
Preliminary Data Sheet
49
V 0.9, 2007-05
TLE5010
Draft
Typical Application Circuit
13
Typical Application Circuit
The application circuit shows the µC version with open drain capabilities.
12V
Voltage
Regulator
VDD
SSC
CLK
DATA_o
CAN RX
CAN TX
CAN
Tranceiver
CAN
µController
Master
DATA_i
SCK
each
100R
1k
VDD
100R
GMR-Sensor
TLE5010
100nF
GND
CSQ
GND
Figure 20
13.1
Application Circuit
Angle Sensor System
A complete system may consist out of one TLE5010 and a micro controller. The second
TLE5010 can be redundand in order to increase the system reliability. The µC should
contain a CORDIC coprocessor for fast angle calculations and a flash memory for the
calibration data storage.
Preliminary Data Sheet
50
V 0.9, 2007-05
TLE5010
Draft
Package Information
14
Package Information
14.1
Package Parameters
Table 20
Package Parameters
Parameter
Symbol
Limit Values
Unit
Notes
min.
typ.
max.
Thermal Resistance RthJA
-
150
200
K/W
Junction to Air 1)
RthJC
RthJL
-
-
75
K/W
Junction to Case
-
-
85
K/W
Junction to Lead
Soldering Moisture
Level
Lead frame
Plating
Molding Compound
1)
MSL 3
Cu194 / OLIN
Sn 100%
EME-G700
260°C
Fe 2.35%, P 0.03%,
Cu 97.5%, Zn0.12%
stamped
> 7 µm
Halogen Free
according to Jedec JESD51-7
Preliminary Data Sheet
51
V 0.9, 2007-05
TLE5010
Draft
Package Information
E
0.2
M
+0.05
0.41 +0.1
-0.05
0.2 -0.01
1.27
A
C
8˚MAX.
3.9 ±0.11)
1.22 ±0.18
1.65 ±0.1
4.9 ±0.08
0.33 ±0.08 x 45˚
A
(1.5)
D
0.1 MIN.
STAND OFF
Package Outline PG-DSO-8
0.64 ±0.25
0.1 8x
D C 8x SEATING
PLANE
6 ±0.2
2.53
0.4 B
Detail A
3 x 1.27 = 3.81
3)
1.95
1
4
B
0.32 MIN.
Pin 1
Index Marking
ø0.6 Sensitive Area 2)
5
0.4 A
Center of
Sensitive Area
8
5.06 ±0.1
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Max. 3˚ tilt of sensitive area to preference "E"
3) Independent from dimensions 1.65 and 1.22
GPS19032
Figure 21
Package Outline PG-DSO-8
Preliminary Data Sheet
52
V 0.9, 2007-05
TLE5010
Draft
Package Information
1.31
Footprint PG-DSO-8
5.69
0.65
1.27
Figure 22
Footprint PG-DSO-8
Packing
0.3
12 ±0.3
5.2
8
1.75
6.4
2.1
Figure 23
Tape and Reel
Preliminary Data Sheet
53
V 0.9, 2007-05
TLE5010
Draft
Package Information
Marking
Top view
123456
G 0624
Bottom view
Type code
Date code
(Year/Month)
111111
11111
111111
Pin 1
Pin 1 marking
Green Package
Production Code
HLGM1227
Figure 24
Marking
Processing
For processing recommendations please refer Infineon’s “Notes on Processing”
Preliminary Data Sheet
54
V 0.9, 2007-05
TLE5010
Draft
Preliminary Data Sheet
Package Information
55
V 0.9, 2007-05
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG