PD - 95122
SMPS MOSFET
IRFB13N50APbF
Applications
l Switch Mode Power Supply (SMPS)
l Uninterruptible Power Supply
l High Speed Power Switching
l Lead-Free
HEXFET® Power MOSFET
VDSS
RDS(on) max
ID
0.450 Ω
14A
500V
Benefits
l Low Gate Charge Qg results in Simple Drive Requirement
l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness
l Fully Characterized Capacitance and Avalanche Voltage
and Current
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case )
Mounting torqe, 6-32 or M3 screw
Max.
Units
14
9.1
56
250
2.0
± 30
9.2
-55 to + 150
A
W
W/°C
V
V/ns
300
°C
10
lbf•in (1.1N•m)
Avalanche Characteristics
Symbol
EAS
IAR
EAR
Parameter
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
560
14
25
mJ
A
mJ
Typ.
Max.
Units
–––
0.50
–––
0.50
–––
62
°C/W
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
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Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
1
3/18/04
IRFB13N50APbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
RDS(on)
VGS(th)
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
∆V(BR)DSS/∆TJ
Min. Typ. Max. Units
Conditions
500 ––– –––
V
VGS = 0V, ID = 250µA
––– 0.55 ––– V/°C Reference to 25°C, I D = 1mA
––– ––– 0.450
Ω
VGS = 10V, ID = 8.4A
2.0
––– 4.0
V
VDS = VGS, ID = 250µA
––– ––– 25
VDS = 500V, VGS = 0V
µA
––– ––– 250
VDS = 400V, VGS = 0V, TJ = 125°C
––– ––– 100
VGS = 30V
nA
––– ––– -100
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
8.1
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
15
39
39
31
1910
290
11
2730
82
160
Max. Units
Conditions
–––
S
VDS = 50V, ID = 8.4A
81
ID = 14A
20
nC
VDS = 400V
36
VGS = 10V, See Fig. 6 and 13
–––
VDD = 250V
–––
ID = 14A
ns
–––
R G = 7.5Ω
–––
VGS = 10V,See Fig. 10
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 400V
Diode Characteristics
Symbol
IS
ISM
VSD
trr
Q rr
iRRM
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Reverse RecoveryCurrent
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
14
–––
–––
56
A
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = 14A, VGS = 0V
TJ = 125°C, IF = 14A
di/dt = 100A/µs
D
S
––– ––– 1.5
V
––– 370 550
ns
––– 4.4 6.5
µC
––– 21
31
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
Starting TJ = 25°C, L = 5.7mH, RG = 25Ω,
IAS = 14A, dv/dt = 7.6V/ns. (See Figure 12a)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
ISD ≤ 14A, di/dt ≤ 250A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C.
2
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IRFB13N50APbF
TOP
I D, Drain-to-Source Current (A)
10
BOTTOM
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
1
I D, Drain-to-Source Current (A)
100
4.5V
0.1
BOTTOM
10
4.5V
1
20µs PULSE WIDTH
T J= 25 ° C
0.01
0.1
1
10
20µs PULSE WIDTH
T J= 150 ° C
0.1
100
0.1
V DS, Drain-to-Source Voltage (V)
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
3.0
100
I D = 14A
2.5
10
TJ = 25 °C
1
V DS= 50V
20µs PULSE WIDTH
0.1
4
6
8
10
12
14
V GS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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16
2.0
(Normalized)
RDS(on) , Drain-to-Source On Resistance
I D, Drain-to-Source Current (A)
TJ = 150 °C
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
TJ , Junction Temperature
80
100
120
140
( ° C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
160
IRFB13N50APbF
100000
10000
Ciss
1000
Coss
100
10
Crss
I D = 14A
7
5
2
1
0
1
10
100
1000
0
12
36
48
60
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1000
ID, Drain-to-Source Current (A)
100
I SD , Reverse Drain Current (A)
24
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
TJ = 25 °C
1
V GS = 0 V
0.2
0.5
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
TJ = 150 °C
10
0.1
0.8
1.1
V SD,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS = 400V
VDS = 250V
VDS = 100V
10
Coss = Cds + Cgd
VGS , Gate-to-Source Voltage (V)
C, Capacitance(pF)
12
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
1.4
10
100µsec
1msec
1
0.1
10msec
Tc = 25°C
Tj = 150°C
Single Pulse
10
100
1000
10000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFB13N50APbF
15
VGS
12
I D , Drain Current (A)
RD
V DS
D.U.T.
RG
9
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
6
Fig 10a. Switching Time Test Circuit
VDS
3
90%
0
25
50
75
100
TC , Case Temperature
125
150
( ° C)
10%
VGS
Fig 9. Maximum Drain Current vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
(Z thJC )
1
D = 0.50
0.1
0.20
Thermal Response
0.10
0.05
0.02
0.01
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P DM
t1
t2
Notes:
1. Duty factor D =
2. Peak T
0.001
0.00001
0.0001
0.001
0.01
t1/ t 2
J = P DM x Z thJC
+TC
0.1
1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFB13N50APbF
1150
ID
EAS , Single Pulse Avalanche Energy (mJ)
920
TOP
6.3A
BOTTOM
8.9A
14A
15V
690
D.U.T
RG
460
DRIVER
L
VDS
+
- VDD
IAS
20V
230
tp
A
0.01Ω
Fig 12c. Unclamped Inductive Test Circuit
0
25
50
75
100
Starting Tj, Junction Temperature
125
150
( ° C)
Fig 12a. Maximum Avalanche Energy
vs. Drain Current
V(BR)DSS
tp
I AS
Fig 12d. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
VGS
.2µF
.3µF
D.U.T.
QGS
+
V
- DS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13a. Gate Charge Test Circuit
6
Charge
Fig 13b. Basic Gate Charge Waveform
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IRFB13N50APbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
•
•
•
•
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFB13N50APbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
1
2
3
4- DRAIN
14.09 (.555)
13.47 (.530)
4- COLLECTOR
4.06 (.160)
3.55 (.140)
3X
3X
LEAD ASSIGNMENTS
IGBTs, CoPACK
1 - GATE
2 - DRAIN
1- GATE
1- GATE
3 - SOURCE 2- COLLECTOR
2- DRAIN
3- SOURCE
3- EMITTER
4 - DRAIN
HEXFET
1.40 (.055)
1.15 (.045)
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010
LOT CODE 1789
AS S E MB L E D ON WW 19, 1997
IN T H E AS S E MB LY L INE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E R NAT IONAL
R E CT IF IE R
L OGO
AS S E MB L Y
LOT CODE
PAR T NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.03/04
8
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