IRF IRFB9N65APBF

PD - 95416
IRFB9N65APbF
HEXFET® Power MOSFET
SMPS MOSFET
Applications
l
l
l
l
Switch Mode Power Supply (SMPS)
Uninterruptible Power Supply
High Speed Power Switching
Lead-Free
VDSS
RDS(on) max
ID
0.93Ω
8.5A
650V
Benefits
l
l
l
Low Gate Charge Qg results in Simple
Drive Requirement
Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
Fully Characterized Capacitance and
Avalanche Voltage and Current
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current ˆ
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt ƒˆ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torqe, 6-32 or M3 screw
Max.
8.5
5.4
21
167
1.3
± 30
2.8
-55 to + 150
Units
A
W
W/°C
V
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Typical SMPS Topologies
l
l
Single Transistor Flyback
Single Transistor Forward
Notes 
through …
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1
06/16/04
IRFB9N65APbF
Static @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
V(BR)DSS
∆V(BR)DSS/∆TJ
Min.
650
–––
–––
2.0
–––
–––
–––
–––
Typ.
–––
0.67
–––
–––
–––
–––
–––
–––
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA†
0.93
Ω
VGS = 10V, ID = 5.1.A „
4.0
V
VDS = VGS, ID = 250µA
25
VDS = 650V, VGS = 0V
µA
250
VDS = 520V, VGS = 0V, TJ = 125°C
100
VGS = 30V
nA
-100
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
3.9
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
14
20
34
18
1417
177
7.0
1912
48
84
Max. Units
Conditions
–––
S
VDS = 50V, ID = 3.1Aˆ
48
ID = 5.2A
12
nC
VDS = 400V
19
VGS = 10V, See Fig. 6 and 13 „ˆ
–––
VDD = 325V
–––
I
D = 5.2A
ns
–––
RG = 9.1Ω
–––
RD = 62Ω,See Fig. 10 „ˆ
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz, See Fig. 5ˆ
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 520V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 520V …ˆ
Avalanche Characteristics
Parameter
EAS
IAR
EAR
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
325
5.2
16
mJ
A
mJ
Typ.
Max.
Units
–––
0.50
–––
0.75
–––
62
°C/W
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Diode Characteristics
IS
ISM
VSD
trr
Qrr
ton
2
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 5.2
showing the
A
G
integral reverse
21
––– –––
S
p-n junction diode.
––– ––– 1.5
V
TJ = 25°C, IS = 5.2A, VGS = 0V „
––– 493 739
ns
TJ = 25°C, IF = 5.2A
––– 2.1 3.2
µC di/dt = 100A/µs „ˆ
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFB9N65APbF
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
10
1
20µs PULSE WIDTH
4.5V TJ = 25 °C
0.1
0.1
1
10
10
4.5V
1
20µs PULSE WIDTH
TJ = 150 ° C
0.1
1
100
Fig 1. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
3.0
10
TJ = 150 ° C
TJ = 25 ° C
1
V DS = 100V
20µs PULSE WIDTH
5.0
6.0
7.0
8.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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100
Fig 2. Typical Output Characteristics
100
0.1
4.0
10
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
9.0
ID = 5.2A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFB9N65APbF
2000
VGS , Gate-to-Source Voltage (V)
1600
C, Capacitance (pF)
20
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
Ciss
1200
Coss
800
400
Crss
0
10
100
VDS = 400V
520V
VDS = 325V
VDS = 130V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
1
ID = 5.2A
0
1000
10
40
50
100
100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
10us
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
30
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
10
TJ = 150 ° C
1
10
100us
1ms
1
10ms
TJ = 25 ° C
0.1
0.2
V GS = 0 V
0.4
0.6
0.8
1.0
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
20
QG , Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
1.2
0.1
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFB9N65APbF
10.0
VGS
8.0
ID , Drain Current (A)
RD
V DS
RG
D.U.T.
+
-VDD
10V
6.0
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
4.0
Fig 10a. Switching Time Test Circuit
2.0
VDS
90%
0.0
25
50
75
100
125
150
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.20
0.1
0.10
PDM
0.05
t1
0.02
0.01
0.01
0.00001
t2
SINGLE PULSE
(THERMAL RESPONSE)
0.0001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
15V
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
A
EAS , Single Pulse Avalanche Energy (mJ)
IRFB9N65APbF
800
TOP
BOTTOM
ID
2.3A
3.3A
5.2A
600
400
200
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
800
QGD
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
V DSav , Avalanche Voltage (V)
QGS
780
760
740
720
.3µF
D.U.T.
+
V
- DS
700
A
0
VGS
1
2
3
4
5
I av , Avalanche Current (A)
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
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IRFB9N65APbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFB9N65APbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (.113)
2.62 (.103)
10.54 (.415)
10.29 (.405)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
LEAD ASSIGNMENTS
1.15 (.045)
MIN
1
2
1234-
14.09 (.555)
13.47 (.530)
1.40 (.055)
1.15 (.045)
2 - DRAIN
GATE
3 - SOURCE
DRAIN
SOURCE
4 - DRAIN
DRAIN
IGBTs, CoPACK
1234-
GATE
COLLECTOR
EMITTER
COLLECTOR
4.06 (.160)
3.55 (.140)
3X
3X
HEXFET
1 - GATE
3
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E X AMP L E :
T H IS IS AN IR F 1010
L OT COD E 1789
AS S E MB L E D ON WW 19, 1997
IN T H E AS S E MB L Y L INE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
IN T E R NAT IONAL
R E CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
P AR T N U MB E R
D AT E CODE
YE AR 7 = 1997
WE E K 19
L IN E C
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
‚ Starting TJ = 25°C, L = 24mH
RG = 25Ω, IAS = 5.2A. (See Figure 12)
ƒ ISD ≤ 5.2A, di/dt ≤ 90A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
† Uses IRFIB5N65A data and test conditions
Data and specifications subject to change without notice.
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TAC Fax: (310) 252-7903
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8
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