PD - 95011
SMPS MOSFET
IRFP26N60LPbF
HEXFET® Power MOSFET
Applications
• Zero Voltage Switching SMPS
• Telecom and Server Power Supplies
• Uninterruptible Power Supplies
• Motor Control applications
• Lead-Free
VDSS RDS(on) typ. Trr typ. ID
600V
170ns
210mΩ
Features and Benefits
• SuperFast body diode eliminates the need for external
diodes in ZVS applications.
• Lower Gate charge results in simpler drive requirements.
• Enhanced dv/dt capabilities offer improved ruggedness.
• Higher Gate voltage threshold offers improved noise immunity .
26A
TO-247AC
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
26
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
IDM
17
100
PD @TC = 25°C Power Dissipation
470
W
3.8
±30
W/°C
V
21
-55 to + 150
V/ns
c
VGS
Linear Derating Factor
Gate-to-Source Voltage
d
dv/dt
TJ
Peak Diode Recovery dv/dt
TSTG
Storage Temperature Range
Operating Junction and
°C
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
Mounting torque, 6-32 or M3 screw
1.1(10)
Diode Characteristics
Symbol
Parameter
A
N•m (lbf•in)
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
26
ISM
(Body Diode)
Pulsed Source Current
–––
–––
100
showing the
integral reverse
c
MOSFET symbol
A
(Body Diode)
D
G
VSD
Diode Forward Voltage
–––
–––
1.5
V
p-n junction diode.
TJ = 25°C, IS = 26A, VGS = 0V
trr
Reverse Recovery Time
–––
170
250
ns
TJ = 25°C, IF = 26A
–––
210
320
–––
670
1000
–––
1050 1570
Qrr
Reverse Recovery Charge
IRRM
Reverse Recovery Current
ton
Forward Turn-On Time
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–––
7.3
11
f
S
f
T = 25°C, I = 26A, V = 0V f
T = 125°C, di/dt = 100A/µs f
TJ = 125°C, di/dt = 100A/µs
nC
J
S
GS
J
A
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
1
2/12/04
IRFP26N60LPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
V(BR)DSS
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ
RDS(on)
–––
Breakdown Voltage Temp. Coefficient
–––
0.33
–––
V/°C Reference to 25°C, ID = 1mA
Static Drain-to-Source On-Resistance
–––
210
250
VGS(th)
Gate Threshold Voltage
3.0
–––
5.0
mΩ
V
IDSS
Drain-to-Source Leakage Current
–––
–––
50
µA
VDS = 600V, VGS = 0V
–––
–––
2.0
mA
VDS = 480V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 30V
Gate-to-Source Reverse Leakage
–––
–––
-100
Internal Gate Resistance
–––
0.8
–––
Ω
f = 1MHz, open drain
IGSS
RG
–––
V
Conditions
600
VGS = 0V, ID = 250µA
VGS = 10V, ID = 16A
f
VDS = VGS, ID = 250µA
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
13
–––
–––
–––
–––
180
–––
–––
61
S
Conditions
gfs
Qg
Forward Transconductance
VDS = 50V, ID = 16A
Total Gate Charge
Qgs
Gate-to-Source Charge
Qgd
Gate-to-Drain ("Miller") Charge
–––
–––
85
VGS = 10V, See Fig. 7 & 15
td(on)
Turn-On Delay Time
–––
31
–––
VDD = 300V
tr
Rise Time
–––
110
–––
td(off)
Turn-Off Delay Time
–––
47
–––
RG = 4.3Ω
tf
Fall Time
–––
42
–––
VGS = 10V, See Fig. 11a & 11b
Ciss
Input Capacitance
–––
5020
–––
VGS = 0V
Coss
Output Capacitance
–––
450
–––
Crss
Reverse Transfer Capacitance
–––
34
–––
Coss eff.
Effective Output Capacitance
–––
230
–––
Coss eff. (ER)
Effective Output Capacitance
–––
170
–––
ID = 26A
nC
ns
VDS = 480V
f
ID = 26A
f
VDS = 25V
pF
ƒ = 1.0MHz, See Fig. 5
VGS = 0V,VDS = 0V to 480V
g
(Energy Related)
Avalanche Characteristics
Symbol
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
–––
Max.
570
Units
mJ
–––
26
A
–––
47
mJ
Units
Thermal Resistance
Typ.
Max.
RθJC
Symbol
Junction-to-Case
Parameter
–––
0.27
RθCS
Case-to-Sink, Flat, Greased Surface
0.24
–––
RθJA
Junction-to-Ambient
–––
40
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
Starting TJ = 25°C, L = 1.7mH, RG = 25Ω,
IAS = 26A, dv/dt = 21V/ns. (See Figure 12a)
ISD ≤ 26A, di/dt ≤ 480A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C.
2
°C/W
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% V DSS .
Coss eff.(ER) is a fixed capacitance that stores the same energy
as Coss while VDS is rising from 0 to 80% V DSS .
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IRFP26N60LPbF
100
1000
100
10
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
12V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
1
5.5V
0.1
10
BOTTOM
VGS
15V
12V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.5V
1
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
0.1
0.01
0.1
1
10
0.1
100
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.0
T J = 150°C
10.00
TJ = 25°C
1.00
VDS = 50V
20µs PULSE WIDTH
ID = 26A
2.5
(Normalized)
100.00
RDS(on) , Drain-to-Source On Resistance
1000.00
ID, Drain-to-Source Current (Α)
1
VGS = 10V
2.0
1.5
1.0
0.5
0.10
2.0
4.0
6.0
8.0
10.0
12.0
14.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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16.0
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFP26N60LPbF
100000
25
Coss = Cds + Cgd
10000
Ciss
20
Energy (µJ)
C, Capacitance(pF)
30
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
1000
Coss
15
10
100
5
Crss
0
10
1
10
100
0
1000
VDS, Drain-to-Source Voltage (V)
300
400
500
600
700
Fig 6. Typ. Output Capacitance
Stored Energy vs. VDS
12.0
1000.00
10.0
VDS= 480V
VDS= 300V
ISD, Reverse Drain Current (A)
ID= 26A
VGS , Gate-to-Source Voltage (V)
200
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100.00
VDS= 120V
8.0
6.0
4.0
2.0
0.0
T J = 150°C
10.00
T J = 25°C
1.00
VGS = 0V
0.10
0
25
50
75
100
125
Q G Total Gate Charge (nC)
Fig 7. Typical Gate Charge Vs.
Gate-to-Source Voltage
4
100
150
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VSD, Source-to-Drain Voltage (V)
Fig 8. Typical Source-Drain Diode
Forward Voltage
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IRFP26N60LPbF
30
ID, Drain-to-Source Current (A)
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
25
ID, Drain Current (A)
100
100µsec
10
1msec
1
Tc = 25°C
Tj = 150°C
Single Pulse
20
15
10
5
10msec
0
0.1
1
10
100
1000
10000
25
Fig 9. Maximum Safe Operating Area
VDS
VGS
RG
RD
75
100
125
150
Fig 10. Maximum Drain Current vs.
Case Temperature
VDS
90%
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 11a. Switching Time Test Circuit
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50
T C , Case Temperature (°C)
VDS, Drain-to-Source Voltage (V)
10%
VGS
td(on)
tr
t d(off)
tf
Fig 11b. Switching Time Waveforms
5
IRFP26N60LPbF
Thermal Response ( Z thJC )
1
0.1
D = 0.50
0.20
0.10
0.05
0.01
0.02
0.01
P DM
t1
SINGLE PULSE
( THERMAL RESPONSE )
0.001
t2
Notes:
1. Duty factor D =
2. Peak T
t1/ t 2
J = P DM x Z thJC
+T C
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 12. Maximum Effective Transient Thermal Impedance, Junction-to-Case
VGS(th) Gate threshold Voltage (V)
6.0
5.0
4.0
ID = 250µA
3.0
2.0
-75
-50
-25
0
25
50
75
100
125
150
T J , Temperature ( °C )
Fig 13. Threshold Voltage vs. Temperature
6
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1
IRFP26N60LPbF
EAS , Single Pulse Avalanche Energy (mJ)
1050
ID
12A
16A
BOTTOM 26A
TOP
900
750
600
450
300
150
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 14a. Maximum Avalanche Energy
vs. Drain Current
15V
V(BR)DSS
DRIVER
L
VDS
D.U.T
RG
+
- VDD
IAS
20V
tp
tp
A
0.01Ω
I AS
Fig 14b. Unclamped Inductive Test Circuit
Fig 14c. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
VGS V
.2µF
.3µF
D.U.T.
QGS
+
V
- DS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 15a. Gate Charge Test Circuit
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Charge
Fig 15b. Basic Gate Charge Waveform
7
IRFP26N60LPbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
•
•
•
•
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 16. For N-Channel HEXFET® Power MOSFETs
8
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IRFP26N60LPbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
-D-
3.65 (.143)
3.55 (.140)
15.90 (.626)
15.30 (.602)
-B-
-A-
0.25 (.010) M D B M
2.50 (.089)
1.50 (.059)
4
5.50 (.217)
20.30 (.800)
19.70 (.775)
2X
1
2
5.30 (.209)
4.70 (.185)
NOTES:
5.50 (.217)
4.50 (.177)
1 DIMENSIONING & TOLERANCING
PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE
TO-247-AC.
3
-C-
14.80 (.583)
14.20 (.559)
2.40 (.094)
2.00 (.079)
2X
5.45 (.215)
2X
4.30 (.170)
3.70 (.145)
0.80 (.031)
3X 0.40 (.016)
1.40 (.056)
3X 1.00 (.039)
0.25 (.010) M
2.60 (.102)
2.20 (.087)
C A S
3.40 (.133)
3.00 (.118)
LEAD ASSIGNMENTS
Hexfet
IGBT
1 -LEAD
GateASSIGNMENTS
1 - Gate
1
GATE
2 - Drain
2 - Collector
2 - DRAIN
3 - Source
3 - Emitter
3 - SOURCE
4 - Drain
4 - DRAIN4 - Collector
TO-247AC Part Marking Information
EXAMPLE: T HIS IS AN IRFPE30
WIT H ASSEMBLY
LOT CODE 5657
ASSEMBLED ON WW 35, 2000
IN THE AS SEMBLY LINE "H"
Note: "P" in assembly line
position indicates "Lead-Free"
INT ERNATIONAL
RECT IFIER
LOGO
PART NUMBER
IRFPE30
56
035H
57
ASSEMBLY
LOT CODE
DAT E CODE
YEAR 0 = 2000
WEEK 35
LINE H
TO-247AC package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.2/04
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9