IRF IRLU7821CPBF

PD - 96056
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
l Lead-Free
IRLR7821CPbF
IRLU7821CPbF
®
HEXFET Power MOSFET
VDSS RDS(on) max
10m:
30V
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
D-Pak
IRLR7821CPbF
Qg
10nC
I-Pak
IRLU7821CPbF
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
Parameter
30
V
VGS
Gate-to-Source Voltage
± 20
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
f
47f
65
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
IDM
Pulsed Drain Current
PD @TC = 25°C
Maximum Power Dissipation
75
PD @TC = 100°C
Maximum Power Dissipation
37.5
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
c
A
260
W
W/°C
°C
0.50
-55 to + 175
Thermal Resistance
Typ.
Max.
–––
2.0
RθJA
Junction-to-Case
Junction-to-Ambient (PCB Mount)
Parameter
–––
50
RθJA
Junction-to-Ambient
–––
110
RθJC
g
Units
°C/W
Notes  through … are on page 11
www.irf.com
1
10/2/06
IRLR/U7821CPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
Drain-to-Source Breakdown Voltage
30
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
23
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
7.5
10
mV/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 15A
–––
9.5
12.5
VGS = 4.5V, ID = 12A
V
VGS = 0V, ID = 250µA
VGS(th)
Gate Threshold Voltage
1.0
–––
–––
V
∆VGS(th)
Gate Threshold Voltage Coefficient
–––
-5.3
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
VDS = 24V, VGS = 0V
–––
–––
150
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
gfs
Qg
Forward Transconductance
46
–––
–––
S
VDS = 15V, ID = 12A
f
f
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V, TJ = 125°C
VGS = -20V
Total Gate Charge
–––
10
14
Qgs1
Pre-Vth Gate-to-Source Charge
–––
2.0
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
1.2
–––
Qgd
Gate-to-Drain Charge
–––
2.5
–––
ID = 12A
Qgodr
–––
4.3
–––
See Fig. 16
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
3.7
–––
Qoss
Output Charge
–––
8.5
–––
td(on)
Turn-On Delay Time
–––
11
–––
VDD = 15V, VGS = 4.5V
tr
Rise Time
–––
4.2
–––
ID = 12A
td(off)
Turn-Off Delay Time
–––
10
–––
tf
Fall Time
–––
3.2
–––
Ciss
Input Capacitance
–––
1030
–––
Coss
Output Capacitance
–––
360
–––
Crss
Reverse Transfer Capacitance
–––
120
–––
VDS = 16V
nC
nC
ns
VGS = 4.5V
VDS = 16V, VGS = 0V
f
Clamped Inductive Load
VGS = 0V
pF
VDS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
dh
c
Typ.
Max.
Units
–––
230
mJ
–––
12
A
–––
7.5
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
f
Conditions
IS
Continuous Source Current
–––
–––
65
ISM
(Body Diode)
Pulsed Source Current
–––
–––
260
showing the
integral reverse
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.0
V
p-n junction diode.
TJ = 25°C, IS = 12A, VGS = 0V
trr
Reverse Recovery Time
–––
26
38
ns
Qrr
Reverse Recovery Charge
–––
15
23
nC
ton
Forward Turn-On Time
2
ch
MOSFET symbol
A
D
G
S
f
TJ = 25°C, IF = 12A, VDD = 15V
di/dt = 100A/µs
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
www.irf.com
IRLR/U7821CPbF
1000
10000
VGS
10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
2.5V
1000
100
BOTTOM
10
1
2.5V
100
BOTTOM
10
2.5V
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
0.1
0.1
1
10
1
0.1
100
1
Fig 1. Typical Output Characteristics
2.0
°C
10
°C
V DS= 15V
20µs PULSE WIDTH
1
2.0
4.0
6.0
8.0
V GS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
www.irf.com
10.0
I D = 65A
1.5
(Normalized)
R DS(on) , Drain-to-Source On Resistance
I D , Drain-to-Source Current (A)
TJ = 175
100
Fig 2. Typical Output Characteristics
1000
100
10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
TJ = 25
VGS
10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
2.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
TJ, Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRLR/U7821CPbF
10000
6
VGS , Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
Coss = Cds + Cgd
Ciss
1000
Coss
Crss
100
ID= 12A
4
3
2
1
0
10
1
10
0
100
4
6
8
10
12
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
ID, Drain-to-Source Current (A)
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
100
I SD , Reverse Drain Current (A)
2
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
TJ = 175 ° C
10
T J= 25 ° C
1
V GS = 0 V
0.1
0.0
0.5
1.0
1.5
V SD,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS= 24V
VDS= 16V
5
100µsec
10
1msec
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
2.0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
www.irf.com
IRLR/U7821CPbF
2.5
70
VGS(th) Gate threshold Voltage (V)
LIMITED BY PACKAGE
60
I D , Drain Current (A)
50
40
30
20
10
2.0
ID = 250µA
1.5
1.0
0.5
0
25
50
75
100
125
150
175
-75 -50 -25
TC , Case Temperature ( °C)
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Threshold Voltage Vs. Temperature
(Z thJC )
10
1
D = 0.50
Thermal Response
0.20
0.10
0.05
0.1
0.02
0.01
P DM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
t1/ t 2
J = P DM x Z thJC
+T C
0.1
1
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
www.irf.com
5
IRLR/U7821CPbF
15V
1000
ID
4.9A
8.5A
12A
TOP
+
V
- DD
IAS
800
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
20V
VGS
DRIVER
L
VDS
BOTTOM
600
400
200
0
25
50
75
100
125
150
175
( ° C)
Starting Tj, Junction Temperature
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
VDS
Fig 12b. Unclamped Inductive Waveforms
VGS
RG
Current Regulator
Same Type as D.U.T.
RD
D.U.T.
+
-V DD
V GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
50KΩ
12V
Fig 14a. Switching Time Test Circuit
.2µF
.3µF
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
6
10%
VGS
td(on)
tr
t d(off)
tf
Fig 14b. Switching Time Waveforms
www.irf.com
IRLR/U7821CPbF
D.U.T
Driver Gate Drive
ƒ
+
‚
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by R G
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
V DD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
+
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
www.irf.com
7
IRLR/U7821CPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
*dissipated primarily in Q1.
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgd
+⎜I ×
× Vin ×
ig
⎝
⎞ ⎛
Qgs 2
⎞
f⎟ + ⎜ I ×
× Vin × f ⎟
ig
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
www.irf.com
IRLR/U7821CPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 1234
AS S EMBLED ON WW 16, 2001
IN T HE AS S EMBLY LINE "A"
PART NUMBER
INT ERNATIONAL
RECT IFIER
LOGO
Note: "P" in ass embly line pos ition
indicates "Lead-Free"
IRFR120
12
116A
34
AS S EMBLY
LOT CODE
DAT E CODE
YEAR 1 = 2001
WEEK 16
LINE A
"P" in as s embly line pos ition indicates
"Lead-Free" qualification to the Cons umer-level
OR
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRFR120
12
AS S EMBLY
LOT CODE
www.irf.com
34
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
P = DES IGNAT ES LEAD-FREE
PRODUCT QUALIFIED T O
CONS UMER LEVEL (OPT IONAL)
YEAR 1 = 2001
WEEK 16
A = AS S EMBLY S ITE CODE
9
IRLR/U7821CPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFU120
WIT H AS S EMBLY
LOT CODE 5678
AS S EMBLED ON WW 19, 2001
IN THE AS S EMBLY LINE "A"
INT ERNATIONAL
RECTIFIER
LOGO
PART NUMBER
IRFU120
119A
56
78
AS S EMBLY
LOT CODE
Note: "P" in ass embly line position
indicates Lead-Free"
DATE CODE
YEAR 1 = 2001
WEEK 19
LINE A
OR
INTERNATIONAL
RECTIFIER
LOGO
PART NUMBER
IRFU120
56
AS S EMBLY
LOT CODE
10
78
DATE CODE
P = DES IGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 1 = 2001
WEEK 19
A = AS S EMBLY S ITE CODE
www.irf.com
IRLR/U7821CPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 3.2mH
RG = 25Ω, IAS = 12A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
… When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/2006
www.irf.com
11