IRF IRF3707ZCLPBF

PD - 95464
IRF3707ZCSPbF
IRF3707ZCLPbF
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l Lead-Free
HEXFET® Power MOSFET
VDSS RDS(on) max
9.5m:
30V
Benefits
l Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
D2Pak
IRF3707ZCS
Qg
9.7nC
TO-262
IRF3707ZCL
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
Parameter
30
V
VGS
Gate-to-Source Voltage
± 20
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
59
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
42
IDM
Pulsed Drain Current
230
PD @TC = 25°C
Maximum Power Dissipation
57
PD @TC = 100°C
Maximum Power Dissipation
28
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
h
h
c
A
W
0.38
-55 to + 175
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
W/°C
°C
300 (1.6mm from case)
x
x
10 lbf in (1.1 N m)
Thermal Resistance
Parameter
RθJC
Junction-to-Case
RθJA
Junction-to-Ambient (PCB Mount)
g
Typ.
Max.
Units
–––
2.653
°C/W
–––
40
Notes  through † are on page 11
www.irf.com
1
6/29/04
IRF3707ZCS/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
Drain-to-Source Breakdown Voltage
30
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.023
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
7.5
9.5
mV/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 21A
–––
10
12.5
VGS = 4.5V, ID = 17A
V
VGS = 0V, ID = 250µA
VGS(th)
Gate Threshold Voltage
1.35
1.80
2.25
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-5.3
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
VDS = 24V, VGS = 0V
–––
–––
150
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
Forward Transconductance
81
–––
–––
Total Gate Charge
–––
9.7
15
Qgs1
Pre-Vth Gate-to-Source Charge
–––
2.8
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
1.0
–––
Qgd
Gate-to-Drain Charge
–––
3.4
–––
ID = 17A
Qgodr
–––
2.5
–––
See Fig. 16
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
4.4
–––
–––
6.2
–––
IGSS
gfs
Qg
e
e
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V, TJ = 125°C
VGS = -20V
S
VDS = 15V, ID = 17A
VDS = 15V
nC
VGS = 4.5V
Qoss
Output Charge
td(on)
Turn-On Delay Time
–––
9.8
–––
VDD = 15V, VGS = 4.5V
tr
Rise Time
–––
41
–––
ID = 17A
td(off)
Turn-Off Delay Time
–––
12
–––
tf
Fall Time
–––
3.6
–––
Ciss
Input Capacitance
–––
1210
–––
Coss
Output Capacitance
–––
260
–––
Crss
Reverse Transfer Capacitance
–––
130
–––
nC
ns
VDS = 16V, VGS = 0V
e
Clamped Inductive Load
VGS = 0V
pF
VDS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
Typ.
–––
d
c
Units
mJ
Max.
40
–––
23
A
–––
5.7
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
h
IS
Continuous Source Current
–––
–––
59
ISM
(Body Diode)
Pulsed Source Current
–––
–––
230
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.0
trr
Reverse Recovery Time
–––
14
21
ns
Qrr
Reverse Recovery Charge
–––
5.2
7.8
nC
2
c
Conditions
MOSFET symbol
A
V
showing the
integral reverse
D
G
p-n junction diode.
TJ = 25°C, IS = 17A, VGS = 0V
S
e
TJ = 25°C, IF = 17A, VDD = 15V
di/dt = 100A/µs
e
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IRF3707ZCS/LPbF
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
3.0V
100
3.0V
10
30µs PULSE WIDTH
Tj = 25°C
1
0.1
1
BOTTOM
30V
10
30µs PULSE WIDTH
Tj = 175°C
1
0.1
10
1
10
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (Α)
VGS
10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
3.0V
T J = 25°C
T J = 175°C
100
VDS = 10V
30µs PULSE WIDTH
10.0
ID = 42A
VGS = 10V
1.5
1.0
0.5
2
3
4
5
6
7
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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8
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRF3707ZCS/LPbF
100000
ID= 17A
Ciss
1000
Coss
Crss
100
5.0
VGS, Gate-to-Source Voltage (V)
C oss = C ds + C gd
10000
C, Capacitance(pF)
6.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VDS= 24V
VDS= 15V
4.0
3.0
2.0
1.0
0.0
10
1
10
100
0
VDS, Drain-to-Source Voltage (V)
2
4
6
8
10
12
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1000.00
1000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ISD, Reverse Drain Current (A)
100.00
100
T J = 175°C
10.00
T J = 25°C
1.00
0.10
VGS = 0V
0.01
0.0
0.5
1.0
1.5
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
2.0
100µsec
10
1msec
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
0
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF3707ZCS/LPbF
60
Limited By Package
50
ID, Drain Current (A)
VGS(th) Gate threshold Voltage (V)
2.5
40
30
20
10
2.0
ID = 250µA
1.5
1.0
0.5
0
25
50
75
100
125
150
-75 -50 -25
175
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.1
τJ
0.02
0.01
0.01
R1
R1
τJ
τ1
τ1
R2
R2
τ2
τ2
Ci= τi/Ri
Ci= τi/Ri
SINGLE PULSE
( THERMAL RESPONSE )
R3
R3
τ3
τC
τ
τ3
Ri (°C/W) τi (sec)
1.163
0.000257
1.073
0.001040
0.419
0.003089
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF3707ZCS/LPbF
15V
+
V
- DD
IAS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
VGS
20V
DRIVER
L
VDS
175
ID
4.5A
6.8A
BOTTOM 23A
TOP
150
125
100
75
50
25
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
LD
I AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
12V
.2µF
.3µF
Fig 14a. Switching Time Test Circuit
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
10%
VGS
td(on)
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
6
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IRF3707ZCS/LPbF
D.U.T
Driver Gate Drive
P.W.
+
ƒ
+
-
-
„
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
*

RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
Period
VDD
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRF3707ZCS/LPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎠
⎝ 2
This can be expanded and approximated by;
*dissipated primarily in Q1.
Ploss = (Irms × Rds(on ) )
2
⎛
⎞ ⎛
Qgs 2
Qgd
+⎜I×
× Vin × f ⎟ + ⎜ I ×
× Vin ×
ig
ig
⎝
⎠ ⎝
⎞
f⎟
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRF3707ZCS/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 5 3 0 S W IT H
L OT COD E 8 0 24
AS S E M B L E D O N W W 0 2 , 2 0 0 0
IN T H E AS S E M B L Y L IN E "L "
IN T E R N AT IO N AL
R E C T IF IE R
L O GO
N ote: "P " in as s em bly line
pos ition in dicates "L ead-F ree"
P AR T N U M B E R
F 530S
AS S E M B L Y
L O T CO D E
D AT E C O D E
Y E AR 0 = 2 0 0 0
WE E K 02
L IN E L
OR
IN T E R N AT IO N AL
R E C T IF IE R
L OGO
AS S E M B L Y
L O T COD E
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P AR T N U M B E R
F 530S
D AT E C O D E
P = D E S IG N AT E S L E AD -F R E E
P R O D U CT (O P T IO N AL )
Y E AR 0 = 2 0 0 0
WE E K 02
A = AS S E M B L Y S IT E C O D E
9
IRF3707ZCS/LPbF
TO-262 Package Outline
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS S EMBLED ON WW 19, 1997
IN THE AS S EMBLY LINE "C"
Note: "P" in ass embly line
pos ition indicates "Lead-Free"
INTERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INTERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
10
PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S IT E CODE
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IRF3707ZCS/LPbF
D2Pak Tape & Reel Infomation
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Notes:
 Repetitive rating; pulse width limited by
… This is applied to D2Pak, when mounted on 1" square PCB (FR4 or G-10 Material). For recommended footprint and soldering
max. junction temperature.
techniques refer to application note #AN-994.
‚ Starting TJ = 25°C, L = 0.15mH, RG = 25Ω,
† Calculated continuous current based on maximum allowable
IAS = 23A.
junction temperature. Package limitation current is 42A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to
80% VDSS.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 6/04
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11