PHILIPS PCF8593T

INTEGRATED CIRCUITS
DATA SHEET
PCF8593
Low power clock/calendar
Product specification
Supersedes data of July 1994
File under Integrated Circuits, IC12
1997 Mar 25
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING
7
FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.10.1
7.11
Counter function modes
Alarm function modes
Control/status register
Counter registers
Alarm control register
Alarm registers
Timer
Event counter mode
Interrupt output
Oscillator and divider
Designing
Initialization (see Fig.12)
I2C-BUS
8
CHARACTERISTICS OF THE
8.1
8.2
8.3
8.4
Bit transfer
Start and stop conditions
System configuration
Acknowledge
9
I2C-BUS PROTOCOL
9.1
9.2
Addressing
Clock/calendar READ/WRITE cycles
1997 Mar 25
2
10
LIMITING VALUES
11
HANDLING
12
DC CHARACTERISTICS
13
AC CHARACTERISTICS
14
APPLICATION INFORMATION
14.1
14.1.1
14.1.2
14.1.3
Quartz frequency adjustment
Method 1: Fixed OSCI capacitor
Method 2: OSCI Trimmer
Method 3: direct output
15
PACKAGE OUTLINES
16
SOLDERING
16.1
16.2
16.2.1
16.2.2
16.3
16.3.1
16.3.2
16.3.3
Introduction
DIP
Soldering by dipping or by wave
Repairing soldered joints
SO
Reflow soldering
Wave soldering
Repairing soldered joints
17
DEFINITIONS
18
LIFE SUPPORT APPLICATIONS
19
PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
2
1 FEATURES
• I2C-bus interface operating supply voltage: 2.5 to 6.0 V
GENERAL DESCRIPTION
The PCF8593 is a CMOS clock/calendar circuit, optimized
for low power consumption. Addresses and data are
transferred serially via the two-line bidirectional I2C-bus.
The built-in word address register is incremented
automatically after each written or read data byte.
The built-in 32.768 kHz oscillator circuit and the first 8
bytes of RAM are used for the clock/calendar and counter
functions. The next 8 bytes may be programmed as alarm
registers or used as free RAM space.
• Clock operating supply voltage (Tamb = 0 to +70 °C):
1.0 to 6.0 V
• 8 bytes scratchpad RAM (when alarm not used)
• Data retention voltage: 1.0 to 6.0 V
• External RESET input resets I2C interface (only)
• Operating current (fscl = 0 Hz, 32 kHz time base,
VDD = 2.0 V): typ. 1 µA
• Clock function with four year calendar
• Universal timer with alarm and overflow indication
• 24 or 12 hour format
• 32.768 kHz or 50 Hz time base
• Serial input/output bus (I2C-bus)
• Automatic word address incrementing
• Programmable alarm, timer and interrupt function
• Space-saving SO8 package available
• Slave address:
– READ A3
– WRITE A2.
3 QUICK REFERENCE DATA
SYMBOL
VDD
PARAMETER
supply voltage operating mode
IDD
supply current operating mode
IDD
supply current clock mode
CONDITIONS
MIN.
TYP.
MAX.
UNIT
2.5
−
6.0
V
I2C-bus inactive
1.0
−
6.0
V
fscl = 100 kHz
−
−
200
µA
fscl = 0 Hz; VDD = 5 V
−
4.0
15.0
µA
fscl = 0 Hz; VDD = 2 V
−
1.0
8.0
µA
I2C-bus
active
Tamb
operating ambient temperature
−40
−
+85
°C
Tstg
storage temperature
−65
−
+150
°C
4 ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
PCF8593P
DIP8
plastic dual in-line package; 8 leads (300 mil)
SOT97-1
PCF8593T
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
1997 Mar 25
DESCRIPTION
3
VERSION
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
5 BLOCK DIAGRAM
VDD
handbook, full pagewidth
8
OSCI
OSCO
INT
RESET
1
2
OSCILLATOR
32.768 kHz
DIVIDER
1 : 256
100 : 128
100 Hz
7
3
RESET
CONTROL
LOGIC
PCF8593
SCL
SDA
6
control/status
hundredths of a second
seconds
minutes
hours
year/date
weekdays/months
timer
alarm control
2
5
I C-BUS
INTERFACE
ADDRESS
REGISTER
00
01
07
08
alarm registers
or RAM
0F
4
MBD808
V SS
Fig.1 Block diagram.
6 PINNING
SYMBOL
PIN
DESCRIPTION
OSCI
1
oscillator input, 50 Hz or event-pulse
input
OSCO
2
oscillator output
RESET
3
reset input (active LOW)
VSS
4
negative supply
SDA
5
serial data input/output
SCL
6
serial clock input
INT
7
open drain interrupt output
(active LOW)
VDD
8
positive supply
1997 Mar 25
OSCI
1
OSCO
2
RESET
3
V SS
4
PCF8593P
PCF8593T
8
V DD
7
INT
6
SCL
5
SDA
MBD809
Fig.2 Pin configuration.
4
Philips Semiconductors
Product specification
Low power clock/calendar
7
PCF8593
a second, seconds, minutes, hours or days. Days are
counted when an alarm is not programmed.
FUNCTIONAL DESCRIPTION
The PCF8593 contains sixteen 8-bit registers with an 8-bit
auto-incrementing address register, an on-chip
32.768 kHz oscillator circuit, a frequency divider and a
serial two-line bidirectional I2C-bus interface.
Whenever an alarm event occurs the alarm flag of the
control/status register is set. A timer alarm event will set
the alarm flag and an overflow condition of the timer will set
the timer flag. The open-drain interrupt output is switched
on (active LOW) when the alarm or timer flag is set
(enabled). The flags remain set until directly reset by a
write operation.
The first 8 registers (memory addresses 00 to 07) are
designed as addressable 8-bit parallel registers. The first
register (memory address 00) is used as a control/status
register. The memory addresses 01 to 07 are used as
counters for the clock function. The memory addresses
08 to 0F may be programmed as alarm registers or used
as free RAM locations.
7.1
When the alarm is disabled (Bit 2 of control/status
register = 0) the alarm registers at addresses 08 to 0F may
be used as free RAM.
7.3
Counter function modes
The control/status register is defined as the memory
location 00 with free access for reading and writing via the
I2C-bus. All functions and options are controlled by the
contents of the control/status register (see Fig.3).
When the control/status register is programmed, a
32.768 kHz clock mode, a 50 Hz clock mode or an
event-counter mode can be selected.
In the clock modes the hundredths of a second, seconds,
minutes, hours, date, month (four year calendar) and
weekday are stored in a BCD format. The timer register
stores up to 99 days. The event counter mode is used to
count pulses applied to the oscillator input (OSCO left
open-circuit). The event counter stores up to 6 digits of
data.
7.4
The year and date are packed into memory location 05
(see Fig 6). The weekdays and months are packed into
memory location 06 (see Fig.7). When reading these
memory locations the year and weekdays are masked out
when the mask flag of the control/status register is set.
This allows the user to read the date and month count
directly.
When a counter is written, other counters are not affected.
In the event-counter mode events are stored in BCD
format. D5 is the most significant and D0 the least
significant digit. The divider is by-passed.
Alarm function modes
By setting the alarm enable bit of the control/status register
the alarm control register (address 08) is activated.
In the different modes the counter registers are
programmed and arranged as shown in Fig.4. Counter
cycles are listed in Table 1.
By setting the alarm control register a dated alarm, a daily
alarm, a weekday alarm or a timer alarm may be
programmed. In the clock modes, the timer register
(address 07) may be programmed to count hundredths of
1997 Mar 25
Counter registers
In the clock modes 24 h or 12 h format can be selected by
setting the most significant bit of the hours counter
register. The format of the hours counter is shown in Fig.5.
When one of the counters is read (memory locations
01 to 07), the contents of all counters are strobed into
capture latches at the beginning of a read cycle. Therefore,
faulty reading of the count during a carry condition is
prevented.
7.2
Control/status register
5
Philips Semiconductors
Product specification
Low power clock/calendar
handbook, full pagewidth
PCF8593
MSB
7
LSB
6
5
4
3
2
1
0
memory location 00
timer flag
(50% duty factor
seconds flag if alarm
enable bit is 0)
alarm flag (50% duty factor
minutes flag if alarm
enable bit is 0)
alarm enable bit:
0 alarm disabled: flags toggle
alarm control register disabled
(memory locations 08 to 0F
can be treated as RAM)
1 enable Alarm Control register
(memory location 08 is the
Alarm Control register)
mask flag:
0
read locations 05 to 06
unmasked
1
read date and month count
directly
function mode :
00 clock mode 32.768 kHz
01 clock mode 50 Hz
10 event-counter mode
11 test modes
hold last count flag :
0 count
1 store and hold last count in
capture latches
stop counting flag :
0 count pulses
1 stop counting, reset divider
MBD810
Fig.3 Control/status register.
1997 Mar 25
6
Philips Semiconductors
Product specification
Low power clock/calendar
handbook, full pagewidth
PCF8593
control/status
control/status
hundredths of a second
1/10 s
1/100 s
seconds
10 s
1s
minutes
10 min
1 min
hours
10 h
1h
year/date
10 day
1 day
weekday/month
10 month
1 month
timer
10 day
1 day
D1
D0
D3
D2
02
D5
D4
03
free
05
free
timer
T1
01
04
free
alarm control
00
06
T0
07
alarm control
08
hundredths of a second
1/10 s
1/100 s
alarm seconds
alarm minutes
alarm
D1
alarm
D0
D3
D2
D5
D4
09
0A
0B
alarm hours
free
alarm date
free
alarm month
free
alarm timer
alarm timer
CLOCK MODES
EVENT COUNTER
0C
0D
0E
0F
MBD811
Fig.4 Register arrangement.
1997 Mar 25
7
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
MSB
handbook, full pagewidth
7
LSB
6
5
4
3
2
1
0
memory location 04 (hours counter)
unit hours BCD
ten hours (0 to 12 binary)
AM/PM flag:
0 AM
1 PM
format:
0 24 h format, AM/PM flag
remains unchanged
1 12 h format, AM/PM flag
will be updated
MBD812
Fig.5 Format of the hours counter.
MSB
handbook, full pagewidth
7
LSB
6
5
4
3
2
1
0
memory location 05 (year/date)
unit hours BCD
ten days (0 to 3 binary)
year (0 to 3 binary, read as 0 if
the mask flag is set)
MBD813
Fig.6 Format of the year/date counter.
handbook, full pagewidth
MSB
7
LSB
6
5
4
3
2
1
0
memory location 06 (weekdays/months)
unit months BCD
ten months
weekdays (0 to 6 binary, read as 0 if
the mask flag is set)
MBD814
Fig.7 Format of the weekdays/months counter.
1997 Mar 25
8
Philips Semiconductors
Product specification
Low power clock/calendar
Table 1
PCF8593
Cycle length of the time counters, clock modes.
UNIT
COUNTING CYCLE
CONTENTS OF THE
MONTH COUNTER
CARRY TO NEXT UNIT
Hundredths of a second
00 to 99
99 to 00
−
Seconds
00 to 59
59 to 00
−
Minutes
00 to 59
59 to 00
−
Hours (24 h)
00 to 23
23 to 00
−
Hours (12 h)
12 AM
−
−
01 AM to 11 AM
−
−
12 PM
−
−
01 PM to 11 PM
11 PM to 12 AM
−
01 to 31
31 to 01
1, 3, 5, 7, 8, 10 and 12
01 to 30
30 to 01
4, 6, 9 and 11
01 to 29
29 to 01
2, year = 0
01 to 28
28 to 01
2, year = 1, 2 and 3
Months
01 to 12
12 to 01
−
Year
0 to 3
−
−
Weekdays
0 to 6
6 to 0
−
Timer
00 to 99
no carry
−
Date
7.5
An alarm signal is generated when the contents of the
alarm registers matches bit-by-bit the contents of the
involved counter registers. The year and weekday bits are
ignored in a dated alarm. A daily alarm ignores the month
and date bits. When a weekday alarm is selected, the
contents of the alarm weekday/month register will select
the weekdays on which an alarm is activated (see Fig.9).
Alarm control register
When the alarm enable bit of the control/status register is
set (address 00, bit 2) the alarm control register
(address 08) is activated. All alarm, timer, and interrupt
output functions are controlled by the contents of the alarm
control register (see Fig.8).
7.6
Remark: in the 12 h mode, bits 6 and 7 of the alarm hours
register must be the same as the hours counter.
Alarm registers
All alarm registers are allocated with a constant address
offset of hexadecimal 08 to the corresponding counter
registers (see Fig.4,Register arrangement).
1997 Mar 25
9
Philips Semiconductors
Product specification
Low power clock/calendar
handbook, full pagewidth
PCF8593
MSB
7
LSB
6
5
4
3
2
1
0
memory location 08
timer function :
000
001
010
011
100
101
110
111
no timer
hundredths of a second
seconds
minutes
hours
days
not used
test mode, all counters
in parallel
timer interrupt enable :
0
1
timer flag, no interrupt
timer flag, interrupt
clock alarm function :
00
01
10
11
no clock alarm
daily alarm
weekday alarm
dated alarm
timer alarm enable :
0
1
no timer alarm
timer alarm
alarm interrupt enable :
MBD815
(valid only when 'alarm enable' in
control/status register is set)
0
1
Fig.8 Alarm control register, clock mode.
1997 Mar 25
10
alarm flag, no interrupt
alarm flag, interrupt
Philips Semiconductors
Product specification
Low power clock/calendar
handbook, full pagewidth
PCF8593
MSB
7
LSB
6
5
4
3
2
1
0
memory location 0E (alarm weekday/month)
weekday 0 enabled when set
weekday 1 enabled when set
weekday 2 enabled when set
weekday 3 enabled when set
weekday 4 enabled when set
weekday 5 enabled when set
weekday 6 enabled when set
not used
MBD816
Fig.9 Selection of alarm weekdays.
7.7
Timer
7.8
The timer (location 07) is enabled by setting the
control/status register = XX0X X1XX. The timer counts up
from 0 (or a programmed value) to 99. On overflow, the
timer resets to 0. The timer flag (LSB of control/status
register) is set on overflow of the timer. This flag must be
reset by software. The inverted value of this flag can be
transferred to the external interrupt by setting bit 3 of the
alarm control register.
Event counter mode is selected by bits 4 and 5 which are
logic 1, 0 in the control/status register. The event counter
mode is used to count pulses externally applied to the
oscillator input (OSCO left open-circuit). The event counter
stores up to 6 digits of data, which are stored as
6 hexadecimal values located in locations 1, 2, and 3.
Thus, up to 1 million events may be recorded.
An event counter alarm occurs when the event counter
registers match the value programmed in locations 9, A,
and B, and the event alarm is enabled (bits 4 and 5 which
are logic 0, 1 in the alarm control register). In this event,
the alarm flag (bit 1 of the control/status register) is set.
The inverted value of this flag can be transferred to the
interrupt pin (pin 7) by setting the alarm interrupt enable in
the alarm control register. In this mode, the timer
(location 07) increments once for every one, one-hundred,
ten thousand, or 1 million events, depending on the value
programmed in bits 0,1 and 2 of the alarm control register.
In all other events, the timer functions are as in the clock
mode.
Additionally, a timer alarm can be programmed by setting
the timer alarm enable (bit 6 of the alarm control register).
When the value of the timer equals a pre-programmed
value in the alarm timer register (location 0F), the alarm
flag is set (bit 1 of the control/status register). The inverted
value of the alarm flag can be transferred to the external
interrupt by enabling the alarm interrupt (bit 6 of the alarm
control register).
Resolution of the timer is programmed via the 3 LSBs of
the alarm control register (see Fig.11, Alarm and timer
Interrupt logic diagram).
1997 Mar 25
Event counter mode
11
Philips Semiconductors
Product specification
Low power clock/calendar
handbook, full pagewidth
PCF8593
MSB
7
LSB
6
5
4
3
2
1
0
memory location 08
timer function :
000
001
010
011
100
101
110
111
no timer
units
100
10 000
1 000 000
not allowed
not allowed
test mode, all counters
in parallel
timer interrupt enable :
0
1
timer flag, no interrupt
timer flag, interrupt
clock alarm function :
00
no event alarm
01
event alarm
10
not allowed
11not allowed
timer alarm enable :
0
1
no timer alarm
timer alarm
alarm interrupt enable :
MBD817
0
1
alarm flag, no interrupt
alarm flag, interrupt
Fig.10 Alarm control register, event-counter mode.
7.9
In the clock mode, if the alarm enable is not activated
(alarm enable bit of control/status register is logic 0), the
interrupt output toggles at 1 Hz with a 50% duty cycle (may
be used for calibration). The OFF voltage of the interrupt
output may exceed the supply voltage, up to a maximum
of 6.0 V. A logic diagram of the interrupt output is shown in
Fig.11.
Interrupt output
The conditions for activating the open-drain n-channel
interrupt output INT (active LOW) are determined by
appropriate programming of the alarm control register.
These conditions are clock alarm, timer alarm, timer
overflow, and event counter alarm. An interrupt occurs
when the alarm flag or the timer flag is set, and the
corresponding interrupt is enabled. In all events, the
interrupt is cleared only by software resetting of the flag
which initiated the interrupt.
1997 Mar 25
12
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
handbook, full pagewidth
MUX
oscillator
mode
select
counter
CLOCK/CALENDAR
control
TIMER
ALARM
clock
alarm
7
6
alarm
control
5
4
3
2
1
timer
alarm
0
timer
control
overflow
7
6
5
4
CONTROL/STATUS
3
2
1
0
ALARM
CONTROL
REGISTER
REGISTER (1)
alarm
interrupt
timer overflow
interrupt
INT
MBD818
(1) If the alarm enable bit of the control/status register is reset (logic 0), a 1 Hz signal can be observed on the interrupt pin INT.
Fig.11 Alarm and timer interrupt logic diagram.
1997 Mar 25
13
Philips Semiconductors
Product specification
Low power clock/calendar
7.10
PCF8593
Oscillator and divider
A 32.768 kHz quartz crystal has to be connected to OSCI
(pin 1) and OSCO (pin 2). A trimmer capacitor between
OSCI and VDD is used for tuning the oscillator (see
Chapter 14, Section 14.1). A 100 Hz clock signal is derived
from the quartz oscillator for the clock counters.
handbook, halfpage
VDD
8
RR
In the 50 Hz clock mode or event-counter mode the
oscillator is disabled and the oscillator input is switched to
a high-impedance state. This allows the user to feed the
50 Hz reference frequency or an external high-speed
event signal into the input OSCI.
reset
input
VDD
3
RESET
CR
PCF8593
7.10.1
DESIGNING
When designing the printed-circuit board layout, keep the
oscillator components as close to the IC package as
possible, and keep all other signal lines as far away as
possible. In applications involving tight packing of
components, shielding of the oscillator may be necessary.
AC coupling of extraneous signals can introduce oscillator
inaccuracy.
MBD819
To avoid overload of the internal diode by falling VDD, an external
diode should be added in parallel to RR if CR ≥ 0.2 µF. Note that RC
must be evaluated with the actual VDD of the application, as their
value will be VDD rise-time dependent.
Fig.12 RC reset.
7.11
Initialization (see Fig.12)
Note that immediately following power-on, all internal
registers are undefined and, following a RESET pulse on
pin 3, must be defined via software. Attention should be
paid to the possibility that the device may be initially in
event-counter mode, in which event the oscillator will not
operate. Over-ride can be achieved via software.
An RC combination can also be utilized to provide a
power-on RESET signal at pin 3. In this event, the values
of the RC must fulfil the following relationship to guarantee
power-on reset (see Fig.12).
RESET input must be ≤0.3VDD when VDD reaches VDDmin
(or higher).
Reset is accomplished by applying an external RESET
pulse (active LOW) at pin 3. When reset occurs only the
I2C-bus interface is reset. The control/status register and
all clock counters are not affected by RESET. RESET
must return HIGH during device operation.
1997 Mar 25
It is recommended to set the stop counting flag of the
control/status register before loading the actual time into
the counters. Loading of illegal states may lead to a
temporary clock malfunction.
14
Philips Semiconductors
Product specification
Low power clock/calendar
8
PCF8593
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data
transfer may be initiated only when the bus is not busy.
8.1
Bit transfer (see Fig.13)
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as a control signal.
SDA
SCL
change
of data
allowed
data line
stable;
data valid
MBC621
Fig.13 Bit transfer.
8.2
Start and stop conditions (see Fig.14)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Fig.14 Definition of start and stop conditions.
1997 Mar 25
15
MBC622
Philips Semiconductors
Product specification
Low power clock/calendar
8.3
PCF8593
System configuration (see Fig.15)
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MBA605
Fig.15 System configuration.
8.4
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.
Acknowledge (see Fig.16)
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
START
CONDITION
MBC602
Fig.16 Acknowledgment on the I2C-bus.
1997 Mar 25
16
clock pulse for
acknowledgement
Philips Semiconductors
Product specification
Low power clock/calendar
9
9.1
PCF8593
I2C-BUS PROTOCOL
Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the start procedure.
The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal,
but the data signal SDA is a bidirectional line. The clock/calendar slave address is shown in Fig.17.
handbook, halfpage
1
0
1
0
0
0
1 R/W
group 2
group 1
MBD821
Fig.17 Slave address.
9.2
The
Clock/calendar READ/WRITE cycles
I2C-bus
configuration for the different PCF8593 READ and WRITE cycles is shown in Figs 18, 19 and 20.
acknowledgement
from slave
acknowledgement
from slave
handbook, full pagewidth
S
SLAVE ADDRESS
0 A
WORD ADDRESS
R/W
A
acknowledgement
from slave
DATA
A
P
n bytes
auto increment
memory word address
MBD822
Fig.18 Master transmits to slave receiver (WRITE) mode.
1997 Mar 25
17
Philips Semiconductors
Product specification
Low power clock/calendar
handbook, full pagewidth
S
acknowledgement
from slave
acknowledgement
from slave
SLAVE ADDRESS
0 A
PCF8593
WORD ADDRESS
R/W
A
S
acknowledgement
from slave
SLAVE ADDRESS
at this moment master transmitter becomes
master - receiver and
PCF8593 slave - receiver
becomes slave - transmitter
1 A
R/W
acknowledgement
from master
DATA
A
n bytes
auto increment
memory word address
no acknowledgement
from master
DATA
1
P
last byte
auto increment
memory word address
MBD823
Fig.19 Master reads after setting word address (write word address, READ data).
acknowledgement
from slave
acknowledgement
from slave
handbook, full pagewidth
S
SLAVE ADDRESS
1 A
R/W
DATA
A
n bytes
acknowledgement
from slave
DATA
1
P
last bytes
auto increment
word address
auto increment
word address
MBD824
Fig.20 Master reads slave immediately after first byte (READ mode).
1997 Mar 25
18
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage (pin 8)
−0.8
+7.0
V
IDD
supply current (pin 8)
−
50
mA
ISS
supply current (pin 4)
−
50
mA
VI
input voltage
−0.8
VDD + 0.8
V
II
input current
−
10
mA
IO
DC output current
−
10
mA
Ptot
total power dissipation per package
−
300
mW
PO
power dissipation per output
−
50
mW
Tamb
operating ambient temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take precautions appropriate to handling MOS devices Advice can be found in Data Handbook IC12 under
“Handling MOS Devices”.
12 DC CHARACTERISTICS
VDD = 2.5 to 6.0 V; VSS = 0 V; Tamb = −40 to +85 °C; fosc = 32 kHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.(1)
MAX.
UNIT
Supply
VDD
VDDosc
supply voltage
(operating mode)
supply voltage
(quartz oscillator)
I2C-bus active
2.5
−
6.0
V
I2C-bus
1.0
−
6.0
V
Tamb = 0 to 70 °C
1.0
−
6.0
V
Tamb = −40 to 85 °C
1.2
−
6.0
V
−
−
200
µA
VDD = 2 V
−
1.0
8.0
µA
VDD = 5 V
−
4.0
15
µA
0
−
0.3VDD
V
inactive
note 2
IDD
supply current
(operating mode)
fscl = 100 kHz; clock mode;
note 3
IDDO
supply current
(clock mode with I2C-bus
inactive)
fscl = 0 Hz;
inputs at VDD or VSS
SDA, SCL, INT and RESET
VIL
LOW level input voltage
VIH
HIGH level input voltage
0.7VDD
−
VDD
V
IOL
LOW level output current
VOL = 0.4 V
3
−
−
mA
ILI
input leakage current
VI = VDD or VSS
−1
−
+1
µA
1997 Mar 25
19
Philips Semiconductors
Product specification
Low power clock/calendar
SYMBOL
Ci
PCF8593
PARAMETER
CONDITIONS
input capacitance
MIN.
TYP.(1)
MAX.
UNIT
note 4
−
−
7
pF
Vl = VDD or VSS
−250
−
+250
nA
OSCI and RESET
input leakage current
ILI
INT
IOL
LOW level output current
VOL = 0.4 V
1
−
−
mA
ILI
input leakage current
Vl = VDD or VSS
−1
−
+1
µA
Ci
input capacitance
note 4
−
−
7
pF
ILI
input leakage current
VI = VDD or VSS
−1
−
+1
µA
SCL
Notes
1. Typical values measured at Tamb = 25 °C.
2. When powering up the device, VDD must exceed the specified minimum value by 300 mV to guarantee correct
start-up of the oscillator.
3. Event counter mode: supply current dependent upon input frequency.
4. Tested on sample basis.
MBD826
12
handbook, halfpage
IDDO
(µA)
8
4
0
0
2
4
VDD (V)
6
fSCL = 32 kHz; Tamb = 25 °C.
Fig.21 Typical supply current in clock mode as a function of supply voltage.
1997 Mar 25
20
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
13 AC CHARACTERISTICS
VDD = 2.5 to 6.0 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Oscillator
Cosc
integrated oscillator
capacitance
∆fosc
oscillator stability
fi
input frequency
20
25
30
pF
for ∆VDD = 100 mV;
Tamb = 25 °C; VDD = 1.5 V
−
2 × 10−7
−
note 1
−
−
1
MHz
Quartz crystal parameters (f = 32.768 kHz)
Rs
series resistance
−
−
40
kΩ
CL
parallel load capacitance
−
10
−
pF
CT
trimmer capacitance
5
−
25
pF
−
−
100
kHz
I2C-bus
timing (see Fig.22; notes 2 and 3)
fSCL
SCL clock frequency
tSP
tolerable spike width on bus
−
−
100
ns
tBUF
bus free time
4.7
−
−
µs
tSU;STA
START condition set-up time
4.7
−
−
µs
tHD;STA
START condition hold time
4.0
−
−
µs
tLOW
SCL LOW time
4.7
−
−
µs
tHIGH
SCL HIGH time
4.0
−
−
µs
tr
SCL and SDA rise time
−
−
1.0
µs
tf
SCL and SDA fall time
−
−
0.3
µs
tSU;DAT
data set-up time
250
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tVD;DAT
SCL LOW to data out valid
−
−
3.4
µs
tSU;STO
STOP condition set-up time
4.0
−
−
µs
Notes
1. Event counter mode only.
2. All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL
and VIH with an input voltage swing of VSS to VDD.
3. A detailed description of the I2C-bus specification, with applications, is given in brochure “The I2C-bus and how to
use it”. This brochure may be ordered using the code 9398 393 40011.
1997 Mar 25
21
Philips Semiconductors
Product specification
Low power clock/calendar
handbook, full pagewidth
t SU;STA
BIT 6
(A6)
BIT 7
MSB
(A7)
START
CONDITION
(S)
PROTOCOL
PCF8593
t LOW
t HIGH
BIT 0
LSB
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
1 / f SCL
SCL
t
tr
BUF
tf
SDA
t HD;STA
t SU;DAT
t
HD;DAT
t VD;DAT
MBD820
Fig.22 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
1997 Mar 25
22
t SU;STO
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
14 APPLICATION INFORMATION
Procedure:
14.1
• Power-on
14.1.1
Quartz frequency adjustment
• Apply RESET
METHOD 1: FIXED OSCI CAPACITOR
• Initialization (alarm functions).
By evaluating the average capacitance necessary for the
application layout a fixed capacitor can be used. The
frequency is best measured via the 1 Hz signal which can
be programmed to occur at the interrupt output (pin 7). The
frequency tolerance depends on the quartz crystal
tolerance, the capacitor tolerance and the
device-to-device tolerance (on average ±5 × 10−6).
Average deviations of ±5 minutes per year can be
achieved.
14.1.2
Routine:
• Set clock to time T and set alarm to time T + ∆T
• At time T + ∆T (interrupt) repeat routine.
14.1.3
METHOD 3: DIRECT OUTPUT
Direct measurement of oscillator output (accounting for
test probe capacitance).
METHOD 2: OSCI TRIMMER
Using the alarm function (via the I2C-bus) a signal faster
than 1 Hz can be generated at the interrupt output for fast
setting of a trimmer.
RESET
handbook, full pagewidth
V DD
SDA
(1)
1F
SCL
RESET
MASTER
TRANSMITTER/
RECEIVER
SCL
CLOCK CALENDAR
OSCI
OSCO
PCF8593
V SS
V DD
SDA
R
SDA
SCL
(I 2C-bus)
(1) Example Philips DLC 196 Double-Layer Capacitor family.
Fig.23 Application diagram.
1997 Mar 25
23
R
R: pull-up resistor
tr
R=
C BUS
MBD825
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
15 PACKAGE OUTLINES
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
ME
seating plane
D
A2
A
A1
L
c
Z
w M
b1
e
(e 1)
b
MH
b2
5
8
pin 1 index
E
1
4
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.14
0.53
0.38
1.07
0.89
0.36
0.23
9.8
9.2
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
1.15
inches
0.17
0.020
0.13
0.068
0.045
0.021
0.015
0.042
0.035
0.014
0.009
0.39
0.36
0.26
0.24
0.10
0.30
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.045
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT97-1
050G01
MO-001AN
1997 Mar 25
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-02-04
24
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0098
0.014 0.0075
0.20
0.19
0.16
0.15
0.050
0.24
0.23
0.039 0.028
0.041
0.016 0.024
inches
0.0098 0.057
0.069
0.0039 0.049
0.01
0.01
0.028
0.004
0.012
θ
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03S
MS-012AA
1997 Mar 25
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-02-04
25
o
8
0o
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
16 SOLDERING
16.1
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
16.3.2 WAVE SOLDERING
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
16.2
16.2.1
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
16.2.2
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
16.3
16.3.1
16.3.3
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1997 Mar 25
REPAIRING SOLDERED JOINTS
26
Philips Semiconductors
Product specification
Low power clock/calendar
PCF8593
17 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Mar 25
27
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TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874
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Uruguay: see South America
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Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/03/pp28
Date of release: 1997 Mar 25
Document order number:
9397 750 01652