Philips Semiconductors Linear Products Product specification Sample-and-hold amplifiers LF198/LF298/LF398 DESCRIPTION PIN CONFIGURATIONS The LF198/LF298/LF398 are monolithic sample-and-hold circuits which utilize high-voltage ion-implant JFET technology to obtain ultra-high DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, DC gain accuracy is 0.002% typical and acquisition time is as low as 6µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin and does not degrade input offset drift. The wide bandwidth allows the LF198 to be included inside the feedback loop of 1MHz op amps without having stability problems. Input impedance of 1010Ω allows high source impedances to be used without degrading accuracy. FE, N Packages V+ 1 8 LOGIC OFFSET VOLTAGE 2 7 LOGIC REFERENCE INPUT 3 6 Ch V– 4 5 OUTPUT TOP VIEW P-channel junction FETs are combined with bipolar devices in the output amplifier to give droop rates as low as 5mV/min with a 1µF hold capacitor. The JFETs have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design guarantees no feedthrough from input to output in the hold mode even for input signals equal to the supply voltages. D1 Package 14 V OS Adj INPUT 1 Logic inputs are fully differential with low input current, allowing direct connection to TTL, PMOS, and CMOS; differential threshold is 1.4V. The LF198/LF298/LF398 will operate from ±5V to ±18V supplies. They are available in 8-pin plastic DIP, 8-pin Cerdip, and 14-pin plastic SO packages. NC 2 13 NC V– 3 12 V+ NC 4 11 LOGIC NC 5 10 LOGIC REF NC 6 9 NC 7 8 Ch OUTPUT TOP VIEW FEATURES NOTE: 1. SO and non-standard pinouts. • Operates from ±5V to ±18V supplies • Less than 10µs acquisition time • TTL, PMOS, CMOS compatible logic input • 0.5mV typical hold step at CH=0.01µF • Low input offset • 0.002% gain accuracy • Low output noise in hold mode • Input characteristics do not change during hold mode • High supply rejection ratio in sample or hold • Wide bandwidth APPLICATION • The LF198/LF298/LF398 are ideally suited for a wide variety of sample-and-hold applications, including data acquisition, analog-to-digital conversion, synchronous demodulation, and automatic test setup ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE -55°C to +125°C LF198FE 0580A 14-Pin Plastic Small Outline (SO) Package 0 to +70°C LF398D 0175D 8-Pin Ceramic Dual In-Line Package (CERDIP) 0 to +70°C LF398FE 0580A 8-Pin Plastic Dual In-Line Package (DIP) 0 to +70°C LF398N 0404B 8-Pin Ceramic Dual In-Line Package (CERDIP) -25°C to +85°C LF298FE 0580A 8-Pin Plastic Dual In-Line Package (DIP) -25°C to +85°C LF298N 0404B 8-Pin Ceramic Dual In-Line Package (CERDIP) August 31, 1994 879 DWG # 853-0135 13721 Philips Semiconductors Linear Products Product specification Sample-and-hold amplifiers LF198/LF298/LF398 FUNCTIONAL DIAGRAM TYPICAL APPLICATIONS OFFSET V+ 30k – V– 5 1 OUTPUT + 4 3 3 INPUT 5 S/H ANALOG INPUT LOGIC 7 300 HOLD 0V Ch 8 SAMPLE 5V LOGIC 7 REFERENCE OUTPUT 6 8 LOGIC INPUT 6 HOLD CAPACITOR ABSOLUTE MAXIMUM RATINGS SYMBOL VS PARAMETER RATING UNIT ±18 V F package 780 mW N package 1160 mW D package 1040 mW LF198 -55 to +125 °C LF298 -25 to +85 °C LF398 0 to +70 °C -65 to +150 °C Supply voltage Maximum power dissipation TA=25°C (still-air)3 TA TSTG VIN Operating ambient temperature range Storage temperature range Equal to supply voltage Input voltage Logic-to-logic reference differential voltage2 +7, -30 Output short-circuit duration TSOLD V Indefinite Hold capacitor short-circuit duration 10 sec Lead soldering temperature (10sec max) 300 °C NOTES: 1. The maximum junction temperature of the LF398 is 150°C. When operating at elevated ambient temperature, the packages must be derated based on the thermal resistance specified. 2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins must always be at least 2V below the positive supply and 3V above the negative supply. 3. Derate above 25°C, at the following rates: F package at 6.2mW/°C N package at 9.3mW/°C D package at 8.3mW/°C August 31, 1994 880 Philips Semiconductors Linear Products Product specification Sample-and-hold amplifiers LF198/LF298/LF398 DC ELECTRICAL CHARACTERISTICS Unless otherwise specified, the following conditions apply: unit is in “sample” mode; VS = ±15V; TJ = 25°C; -11.5V3 VIN ≤ +11.5V; CH=0.01µF; and RL = 10kΩ. Logic reference voltage = 0V and logic voltage = 2.5V. SYMBOL PARAMETER VOS Input offset voltage4 IBIAS Input bias current4 Input impedance Gain error Feedthrough attenuation ratio at 1kHz Output impedance “HOLD“ step2 ICC tAC TEST CONDITIONS LF198/LF298 Min TJ=25°C Max 1 3 Full temperature range Min TJ=25°C 5 2 25 10 0.002 Full temperature range 0.005 96 0.5 TJ=25°C, “HOLD“ mode Full temperature range 50 0.004 0.01 0.02 80 2 90 0.5 4 UNIT mV nA Ω 1010 0.02 86 7 100 1010 RL=10k Max 10 75 TJ=25°C TJ=25°C, Ch=0.01µF Typ 5 Full temperature range TJ=25°C, LF398 Typ % dB 4 6 Ω TJ=25°C, Ch=0.01µF, VOUT=0 0.5 2.0 1.0 2.5 mV Supply current4 TJ ≤ 25°C 4.5 5.5 4.5 6.5 mA Logic and logic reference input current TJ = 25°C 2 10 2 10 µA Leakage current into hold capacitor4 TJ=25°C, “HOLD“ mode 30 100 30 200 pA ∆VOUT=10V, Ch=1000pF 4 4 Ch=0.01µF 20 20 Hold capacitor charging current VIN-VOUT=2V 5 5 mA Supply voltage rejection ratio VOUT=0 80 110 80 110 dB Differential logic threshold TJ=25°C 0.8 1.4 0.8 1.4 Acquisition time to 0.1% 2.4 µs 2.4 V NOTES: 1. Unless otherwise specified, the following conditions apply. Unit is in “sample“ mode, VS=±15V, TJ=25°C, -11.5V ≤ VIN ≤ +11.5V, Ch = 0.01µF, and RL = 10kΩ. Logic reference voltage = 0V and logic voltage = 2.5V. 2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an additional 0.5mV step with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. 3. Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input signal range. 4. The parameters are guaranteed over a supply voltage of ±5 to ±18V. August 31, 1994 881 Philips Semiconductors Linear Products Product specification Sample-and-hold amplifiers LF198/LF298/LF398 TYPICAL DC PERFORMANCE CHARACTERISTICS Output Short Circuit Current 20 20 18 16 CURRENT (mA) CURRENT (mA) 15 10 5 0 14 SOURCING 12 10 8 SINKING 6 –5 4 –10 2 –15 –25 0 25 50 75 100 0 –50 125 150 JUNCTION TEMPERATURE (°C) 25 50 75 100 0.8 TJ = 25°C RL = 10k 0.6 SAMPLE MODE 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 –15 125 150 TJ = 25°C VOUT = 0 HOLD MODE CURRENT (nA) 10 1 1 10–1 0.1 0.01µF 0.1µF 1µF 0 5 10 15 2 VS = ±15V 10 –5 Hold Step Input Voltage 100 V+ = V– = 15V 1000pF –10 INPUT VOLTAGE (V) Leakage Current Into Hold Capacitor 100 HOLD STEP (mV) 0 1 JUNCTION TEMPERATURE (°C) Hold Step 0.01 100pF –25 NORMALIZED HOLD STEP AMPLITUDE –50 Gain Error INPUT VOLTAGE — OUTPUT VOLTAGE (mV) Input Bias Current 25 10–2 –50 1.8 1.6 1.4 TJ = 100°C 1.2 1 TJ = 25°C 0.8 0.6 0.4 TJ = 55°C 0.2 0 –25 0 25 50 75 100 125 150 –15 JUNCTION TEMPERATURE (°C) HOLD CAPACITOR –10 –5 0 5 10 15 INPUT VOLTAGE (V) TYPICAL AC PERFORMANCE CHARACTERISTICS Acquisition Time 1 1% Aperture Time VIN = 0 TO ±10V 250 TJ = 25°C 225 10 ∆VOUT ≤ 1mV 175 TIME (ns) 0.1% TIME ( µ s) 100 V+ = V– = 15V 200 0.01% 150 125 ∆VIN = 10V NEGATIVE INPUT STEP 1 75 50 POSITIVE INPUT STEP 25 0.01 HOLD CAPACITOR (µF) 0.1 0 –50 0.1 –25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) August 31, 1994 10 100 100 1000 0.001 Capacitor Hysteresis 882 0.1 1 10 SAMPLE TIME (ms) 100 Philips Semiconductors Linear Products Product specification Sample-and-hold amplifiers LF198/LF298/LF398 TYPICAL AC PERFORMANCE CHARACTERISTICS (Continued) Dynamic Sampling Error 100 Output Droop Rate ‘Hold’ Sampling Time 10 0 330pF 2 V+ = V– = 15V SETTLING TIME 1.8 ±1 TIME ( µs) 330pF 1.4 TJ =85°C ∆ V/ ∆ T (V/SEC) ERROR (mV) 1.6 10–1 10 10–2 TJ =25°C 1 0.8 0.6 10–3 –10 1.2 0.4 1000pF 0.2 10–4 –100 1 10 100 1000 0 100pF 1000pF INPUT SLEW RATE (V/ms) 70 Ch = 1000pF 60 Ch ≥ 0.01µF 50 Ch = 1000pF 40 Ch = 0.01µF 30 20 Ch ≥ 0.01µF 10 Ch = 0 100k 1M 120 140 VOUT = 0°C 120 100 POSITIVE MODE 80 NEGATIVE MODE 60 100 125 150 ‘HOLD’ MODE 80 60 40 20 20 10k 100k 1M –130 V+ = V– = 15V –120 TJ =25°C VIN = 10Vp-p –110 V7.8 = 0 Ch = 0.1µF –100 Ch = 0.01µF –90 –80 Ch = 1000pF –70 –60 –50 100 100 1k 10k 100k FREQUENCY (Hz) 883 10 100 1k 10k FREQUENCY (Hz) Feedthrough Rejection Ratio (Hold Mode) 10 SAMPLE MODE 0 1k FREQUENCY (Hz) RATIO (dB) 75 100 40 FREQUENCY (Hz) August 31, 1994 50 Output Noise TJ =25°C V+ = V– = 15V 0 100 10M 25 160 140 0 10k 0 JUNCTION TEMPERATURE (°C) 160 REJECTION RATIO (dB) GAIN — INPUT TO OUTPUT (dB) 0 INPUT TO OUTPUT PHASE DELAY ( o ) 80 Ch = 0 1k –50 –25 1µF Power Supply Rejection 5 –10 0.1µF HOLD CAPACITOR Phase And Gain (Input to Output, Small-Signal) –5 0.01µF NOISE (nV/ Hz) 0.1 1M 100k