Supertex inc. HV513 8-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs, POL, Hi-Z, and Short Circuit Detect Features ►► HVCMOS® technology ►► Operating output voltage of 250V ►► Low power level shifting from 5.0 to 250V ►► Shift register speed 8.0MHz @ VDD = 5.0V ►► 8 latch data outputs ►► Output polarity and blanking ►► Output short circuit detect ►► Output high-Z control ►► CMOS compatible inputs Applications ►► ►► ►► ►► ►► ►► Piezoelectric transducer driver Braille driver Weaving applications Printer drivers MEMs Displays General Description The HV513 is a low voltage serial to high voltage parallel converter with 8 high voltage push-pull outputs. This device has been designed to drive small capacitve loads such as piezoelectric transducers. It can also be used in any application requiring multiple high voltage outputs, with medium current source and sink capabilities. The device consists of an 8-bit shift register, 8 latches, and control logic to perform the polarity select and blanking of the outputs. Data is shifted through the shift register on the low to high transition of the clock. A data output buffer is provided for cascading devices. Operation of the shift register is not affected by the LE, BL, POL, or the HI-Z control inputs. Transfer of data from the shift register to the latch occurs when the LE is high. The data in the latch is stored when LE is low. A high-Z (HI-Z) pin is provided to set all the outputs in a high-Z state. All outputs have short circuit protection that detects if the outputs have reached the required output state. If output does not track the required state, then the SHORT pin will be low. This output will pulse low during the output transistion period under normal operation; see SC Timing Diagram for details. All outputs will have a break-before-make circuitry to reduce cross-over current during output state changes. The POL, BL, LE, and HI-Z inputs have an internal pull up resistor. Typical Application Circuit Low Voltage Power Supply High Voltage Power Supply HVOUT1 DIN CLK FPGA Low Voltage High Voltage Shift Register Latches Output Controller Level Translators & Push-Pull Output Buffers LE BL POL HiZ 8 / DOUT DIN Doc.# DSFP-HV513 C072413 to the next HV513 for cascading HVOUT8 SHORT Piezo Element Supertex HV513 Supertex inc. www.supertex.com HV513 Pin Configuration Ordering Information Part Number Package Packing HV513K7-G 32-Lead QFN 400/Tray HV513K7-G M935 32-Lead QFN 2000/Reel HV513WG-G 24-Lead SOW 1000/Reel 1 32 24 1 -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value Logic supply, VDD -0.5V to 6.0V High voltage supply, VPP Logic input levels Ground current 32-Lead QFN VDD to 275V -0.5V to VDD +0.5V 0.3A 1 Continuous total power dissipation2 Operating junction temperature L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging HV513 750mW LLLLLL YYWW AAACCC -40°C to +85°C Storage temperature range (top view) Product Marking 0.25A High voltage supply current1 24-Lead SOW (top view) -65°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the Package may or may not include the following marks: Si or device may occur. Functional operation under these conditions is not implied. 32-Lead QFN Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Top Marking Notes: 1. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package. 2. For operation above 25°C ambient derate linearly to 85°C at 12mW/°C. H V 513W G LLLLLLLLLL Bottom Marking Typical Thermal Resistance Package θja 32-Lead QFN 22OC/W 24-Lead SOW 44OC/W YY = Year Sealed WW = Week Sealed A = Assembler ID L = Lot Number C = Country of Origin* = “Green” Packaging YYWW AAA CCCCCCCCCCC *May be part of top marking Package may or may not include the following marks: Si or 24-Lead SOW Typical Operating Conditions Sym Parameter Min Typ Max Units Conditions VDD Logic supply voltage 4.5 5.0 5.5 V --- VPP High voltage supply 50 - 250 V Note 1 VIH High-level input voltage VDD -0.9 - VDD V --- VIL Low-level input voltage 0 - 0.9 V --- TJ Operating junction temperature -40 - +85 °C --- Notes: 1. Below minimum VPP the output may not switch. 2. Power-up sequence should be the following: 1. Connect ground 2. Apply VDD 3. Set all inputs (Data, CLK, Enable, etc.) to a known state 4. Apply VPP Power-down sequence should be the reverse of the above Doc.# DSFP-HV513 C072413 2 Supertex inc. www.supertex.com HV513 DC Electrical Characteristics Sym (Over typical operating conditions unless otherwise specified, TJ = 25OC) Parameter Min Typ Max Units - - 4.0 mA - - 0.1 - - 2.0 Conditions IDD VDD supply current IDDQ Quiescent VDD supply current IPP VPP supply current - - 100 µA VPP = 250V, fOUT = 300Hz, no load IPPQ Quiescent VPP supply current - - 100 µA VPP = 240V, outputs are static IIH High-level logic input current - - 10 µA VIH = VDD IIL Low-level logic input current VOH High level output VOL Low level output -10 - - -350 140 - - VDD -1.0V - - HVOUT - - 60 Data out - - 1.0 HVOUT Data out mA µA V V fCLK = 8.0Hz, LE = Low All VIN = VDD All VIN = 0V VIL = 0V VIL = 0V, for inputs w/pull-up resistors VPP = 200V, IHVOUT = -20mA IDOUT = -0.1mA VDD = 4.5V, IHVOUT = 20mA IDOUT = 0.1mA AC Electrical Characteristics (Over typical operating conditions unless otherwise specified, T = 25 C) J Sym Parameter O Min Typ Max Units Conditions --- fCLK Clock frequency 0 - 8.0 MHz fOUT Output switching frequency (SOA limited) - 300 - Hz CL = 50nF, VPP = 200V tW Clock width high and low 62 - - ns --- tSU Data setup time before clock rises 15 - - ns --- tH Data hold time after clock rises 30 - - ns --- tWLE Width of latch enable pulse 80 - - ns --- tDLE LE delay time after rising edge of clock 35 - - ns --- tSLE LE setup time before rising edge of clock 40 - - ns --- tOR, tOF HVOUT rise/fall time - - 1000 µs CL = 100nF, VPP = 200V td ON/OFF Delay time for output to start rise/fall - - 500 ns --- tDHL Delay time clock to DOUT high to low - - 110 ns CL = 15pF tDLH Delay time clock to DOUT low to high - - 110 ns CL = 15pF tR, tF All logic inputs - - 5.0 ns --- tSD Output short circuit detection - - 500 ns tSC Output short circuit clear - - 3000 ns tHI-Z Output HI-Z state - - 500 ns Doc.# DSFP-HV513 C072413 3 CL = 15pF, Short to output fall of SHORT Short clear to output rise of SHORT --- Supertex inc. www.supertex.com HV513 Input and Output Equivalent Circuits VDD VDD VPP 20kΩ* DATA OUT INPUT GND HVGND GND Logic Data Output Logic Inputs HVOUT High Voltage Outputs Short Circuit Detect Detail Timing LE VH POL VL BL VIH HI-Z VIL tHi-Z HVOUT Short Detect VOH Within xV of rail tSD tSC VOL VH VL Note: For VPP greater than 150V: Short detect output will flag short conditions - HVOUT is higher than 10V when expected low - HVOUT is lower than VPP - 100V when expected high Short detect output will stay clear - HVOUT is lower than 2.0V when expected low - HVOUT is higher than VPP - 60V when expected high Doc.# DSFP-HV513 C072413 4 Supertex inc. www.supertex.com HV513 Switching Waveforms VIH DATA INPUT Data Valid 50% tSU CLK 50% VIL tH VIH 50% 50% 50% 50% tWH tWL VOH 50% VOL tDLH DATA OUT VOH 50% VOL tDHL tWLE tDLE td(OFF) 10% td(ON) Doc.# DSFP-HV513 C072413 5 VIL tSLE 90% 10% HVOUT w/S/R Low HVOUT w/S/R High VIH 50% 50% LE VIL VOH VOL tOR 90% VOH VOL tOR Supertex inc. www.supertex.com HV513 Functional Block Diagram POL VPP BL LE DIN CLK HVOUT1 • • • 6 Additional Outputs • • • HVOUT8 L/T 8-Bit Static Shift Register 8 Latches L/T DOUT HI-Z Short Detect Short Note: POL, BL, LE, and Hi-Z have internal 20kΩ pull-up resistors. Function Table Inputs Function Outputs Shift Reg 1 2...8 HV Outputs 1 2...8 Data Out ● Data CLK LE BL POL HI-Z All on X X X L L H ● ●...● H H...H ● All off X X X L H H ● ●...● L L...L ● Invert mode X X L H L H ● ●...● ●...● (b) ● Load S/R H OR L ↑ L H H H H or L ● ●...● ● Store data in latches X X L H H H ● ●...● ● ●...● ● X X L H L H ● ●...● ●...● (b) ● Transparent mode L ↑ H H H H L ●...● L ●...● ● H ↑ H H H H H ●...● H ●...● ● Outputs High-Z X X X X X L ● ●...● Outputs on X X X X X H ● ●...● ● ●...● ● High impedence outputs ● ●...● ● ● Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition ● = dependent on previous stage’s state before the last CLK or last LE high. Doc.# DSFP-HV513 C072413 6 Supertex inc. www.supertex.com HV513 Pin Description - 32-Lead QFN Pin # Function Description 1 2 NC No internal connection 3 4 5 6 LGND Low voltage ground HVGND High voltage ground 7 NC 8 No internal connection 9 HVOUT1 High voltage push-pull output 10 HVOUT2 High voltage push-pull output 11 HVOUT3 High voltage push-pull output 12 HVOUT4 High voltage push-pull output 13 HVOUT5 High voltage push-pull output 14 HVOUT6 High voltage push-pull output 15 HVOUT7 High voltage push-pull output 16 HVOUT8 High voltage push-pull output 17 NC No internal connection VPP High voltage supply 21 VDD Logic supply voltage 22 DOUT 18 19 20 23 Data output NC No internal connection 25 BL Blanking pin, logic input low sets all HVOUTS low 26 NC No internal connection 27 POL Polarity bar input logic 28 CLK Clock pin, shift registers shifts data on rising edge of input clock 29 LE 30 SHORT 31 HI-Z High impedance pin, logic input low sets all outputs in a high impedance state 32 DIN Data input Center Pad VPP Center pad is at VPP potential. Connect to VPP or leave floating. 24 Doc.# DSFP-HV513 C072413 Latch enable bar input logic If output does not reach its required state, SHORT pin will output logic low 7 Supertex inc. www.supertex.com HV513 Pin Description - 24-Lead SOW Pin # Function 1 NC 2 VDD 3 DOUT 4 BL 5 POL Polarity bar input logic 6 CLK Clock pin, shift registers shifts data on rising edge of input clock 7 LE 8 SHORT 9 HI-Z High impedance pin, logic input LOW sets all outputs in a high impedance state 10 DIN Data input 11 LGND 12 NC 13 Description No internal connection Logic supply voltage Data output Blanking pin, logic input LOW sets all HVOUTS low Latch enable bar input logic If output does not reach its required state, SHORT pin will output logic LOW Low voltage ground No internal connection HVGND High voltage ground 15 HVOUT1 High voltage push-pull output 16 HVOUT2 High voltage push-pull output 17 HVOUT3 High voltage push-pull output 18 HVOUT4 High voltage push-pull output 19 HVOUT5 High voltage push-pull output 20 HVOUT6 High voltage push-pull output 21 HVOUT7 High voltage push-pull output 22 HVOUT8 High voltage push-pull output 14 23 24 Doc.# DSFP-HV513 C072413 VPP High voltage supply 8 Supertex inc. www.supertex.com HV513 32-Lead QFN Package Outline (K7) 6.00x6.00mm body, 0.80mm height (max), 0.50mm pitch Detail Bx32 D 32 25 L1 D1 32 L1 Detail C (note 2) e1 1 1 24 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) 7xe E E1 e 17 8 e1 L1 16 L1 e2 Top View b Seating Plane A A1 e2 Bottom View LC1 LC LC LC L 0.30x45 Side View Detail A Detail Ax3 (note 2) 9 7xe Detail B O Detail C Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. The 4 corner pads are for mechanical placement only, they are not internally connected. Symbol Dimension (mm) A A1 b D D1 E E1 MIN 0.70 0.00 0.20 5.90 3.20 5.90 4.30 NOM 0.75 - 0.30 6.00 3.30 6.00 4.40 MAX 0.80 0.05 0.40 6.10 3.40 6.10 4.50 e e1 e2 0.50 BSC 1.00 REF 0.975 REF L 0.20 0.30 0.40 L1 0.10 REF LC LC1 0.20 0.25 0.30 0.35 0.40 0.45 Drawings not to scale. Supertex Doc. #: DSPD-32QFNK76X6P050, Version B092309. Doc.# DSFP-HV513 C072413 9 Supertex inc. www.supertex.com HV513 24-Lead SOW (Wide Body) Package Outline (WG) 15.40x7.50 body, 2.65mm height (max), 1.27mm pitch D 24 θ1 E1 E Note 1 (Index Area 0.25D x 0.75E1) L L1 e 1 b Top View Gauge Plane L2 Seating Plane θ View B View B Note 1 A h h A A2 Seating Plane A1 Side View View A-A A Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b D E E1 2.15* 0.10 2.05 0.31 15.20* 9.97* 7.40* - - - - 15.40 10.30 7.50 2.65 0.30 2.55* 0.51 15.60* 10.63* 7.60* e 1.27 BSC h L 0.25 0.40 - - 0.75 1.27 L1 1.40 REF L2 0.25 BSC θ θ1 0O 5O - - 8O 15O JEDEC Registration MS-013, Variation AD, Issue E, Sep. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-24SOWWG, Version E041309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV513 C072413 10 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com