Multistandard Sound IF TDA 6160-2S Preliminary Data Bipolar IC Features ● ● ● ● ● ● ● ● Sound carrier mixer VCO Programmable Divider Reference divider with crystal oscillator Phase comparator Operational amplifier for PLL filter I2C bus interface 3 identical FM channels with limiter amplifiers and coincidence demodulators. P-SDIP-30 Type Ordering Code Package TDA 6160-2S Q67000-A5184 P-SDIP-30 Functional Description Multistandard sound IF-device consisting of a mixer as a frequency converter, a voltage-controlled oscillator (VCO) that can be continously tuned in 10-kHz increments with crystal accuracy by means of a PLL, and three following parallel FM-limiter amplifiers with coincidence demodulators. The switching functions and setting of the PLL are controlled on an I2C bus. Application For use in satellite receivers. Semiconductor Group 126 08.93 TDA 6160-2S Pin Functions Pin No. Function 1 Quartz oscillator 2 PD-output / integrator input (fREF, fCy) 3 Integrator output (VD) 4 VCO 5 Chip address switching (CA) 6 Demodulator circuit (IF-1) 7 Demodulator circuit (IF-1) 8 AF-output 1 9 Demodulator circuit (IF-2) 10 Demodulator circuit (IF-2) 11 AF-output 2 12 Demodulator circuit (IF-3) 13 Demodulator circuit (IF-3) 14 AF-output 3 15 NC 16 NC 17 IF-input 3 18 VS (analog) 19 IF-input 2 20 Ground (analog) 21 IF-input 1 22 IF-reference 23 Mixer output 2 24 Mixer output 1 25 Mixer input (reference) 26 Mixer input 27 Ground (digital) 28 VS (digital) 29 I2C bus (SCL) 30 I2C bus (SDA) Semiconductor Group 127 TDA 6160-2S Pin Functions Pin 1 Pin 2/3 Semiconductor Group 128 TDA 6160-2S Pin 4 Pin 6/7/8; 9/10/11; 12/13/14 Semiconductor Group 129 TDA 6160-2S Pin 21; 19; 17/22 Pin 23/24/25/26 Semiconductor Group 130 TDA 6160-2S Pin 5; 29 Pin 30 Semiconductor Group 131 TDA 6160-2S Block Diagram Semiconductor Group 132 TDA 6160-2S Circuit Description The sound intermediate frequencies contained in the baseband of a demodulated FM satellite signal can lie between 5 and 9 MHz. This band of frequencies is applied ready filtered to the input of the converter mixer. The purpose of this mixer is to convert the different sound IFs in the baseband to fixed output frequencies (eg 10.7/10.52 MHz). These frequencies are then fed by external filters to the inputs of the three sound IF-amplifiers. The VCO of the mixer can be continuously tuned between 14.5 and 20 MHz in 10-kHz increments with crystal accuracy by means of a PLL-circuit. The setting of the programmable divider and the cutting in and out of the sound IF-amplifiers are controlled on the I2C bus. Pin 5 (CA) offers two switchable chip addresses to enable parallel operation of two devices. All pins are guarded against electrostatic discharge. SCL and SDA include special protective structures to permit continued bus operation when the device is switched off. PLL The VCO-signal, DC coupled internally, is applied to the PLL-input. It passes through a programmable divider (N = 1024 to 2047) and is then compared to a reference frequency (fREF = 10 kHz) in a digital frequency/phase detector. This frequency is derived from a 4-MHz crystal oscillator whose signal is divided by 400. The phase detector has a charge-pump push-pull current output. If the negative edge of the divided VCO-signal appears before the negative edge of the reference signal, the current source I+ will pulse for the duration of the phase difference. In the reverse case it is the current sink I–. If both signals are in-phase, the output is high-impedance and the PLL is locked in. The current pulses are filtered by means of an integrator (internal operational amplifier with external RC-circuitry). The pump current can be switched between the two values 1 and 5 by software with a control bit 5I. This permits a change in the control response during and after the lock-in state. I2C Bus Interface Information is exchanged between the processor and the sound IF-device on an asynchronous bidirectional data bus. The timing for this comes from the processor (input SCL), while pin SDAfunctions as an input or output depending on the direction of the data (open collector; external pull-up resistor). The data from the processor go to an I2C bus controller and are filled in registers (latches 0 to 2) according to their function. When the bus is not busy, both lines are in marking state (SDA, SCL are high). Each telegram begins with the start condition: SDA goes low while SCL remains high. All further exchanges of information are while SCL is low and are read by the controller with the positive clock edge. If SDA goes high while the clock is high, the PLL recognizes this as a stop condition and thus the end of the telegram. For what follows, refer to the table of logic assignments below. All telegrams are transferred byte by byte, followed by a ninth clock pulse during which the controller pulls the SDA-line to low (i.e. acknowledge condition). The first byte consists of seven address bits with which the processor selects the PLL from among several peripheral devices (chip select). The Semiconductor Group 133 TDA 6160-2S eighth bit is always low. The first bit of the first or third data byte in the data part of the telegram determines whether a divider ratio or control information will follow. In every case the first byte must be followed by a byte of the same data type (or a stop condition). When the supply voltage is applied, a power-on reset circuit prevents the PLL from pulling the SDA-line to low and thus blocking the bus. Logic Allocations Address byte 0 1 0 0 0 MA1 MA0 R/W A Progr. divider byte 1 0 0 n10 n9 n8 n7 n6 n5 A Progr. divider byte 2 n4 n3 n2 n1 n0 0 0 0 A Control information 1 5I Z2 Z1 Z0 T2 T1 T0 A Address byte 1 0 1 0 0 0 1 0 0 A = H44 Address byte 2 0 1 0 0 0 1 1 0 A = H46 Chip address (CA) pin 5 on: ground = address byte 1 VS or open = address byte 2 Test Mode T2, T1, T0 = 0, 0, 0 T2, T1, T0 = 1, 0, 0 T2, T1, T0 = 1, 1, 0 T2, T1, T0 = 1, 1, 1 T2, T1, T0 = 0, 1, 1 normal operation pin 2 = fREF pin 2 = fCy pin 2 = tristate pin 2 = high-impedance = pin 3 high-impedance IF-Muting Circuits Z2, Z1, Z0 = 0, 0, 0 Z2, Z1, Z0 = 0, 0, 1 Z2, Z1, Z0 = 0, 1, 0 Z2, Z1, Z0 = 0, 1, 1 Z2, Z1, Z0 = 1, 0, 0 Z2, Z1, Z0 = 1, 0, 1 Z2, Z1, Z0 = 1, 1, 0 Z2, Z1, Z0 = 1, 1, 1 Semiconductor Group normal operation IF 3 IF 2 IF 1 = on; IF 2/IF 3 = off IF 1 IF 1 = off; IF 2 = on; IF 3 = off IF 3 = on; IF 1/IF 2 = off IF 1, IF 2, IF 3 = off 134 = off (output 14 high-impedance) = off (output 11 high-impedance) = off (output 8 high-impedance) TDA 6160-2S Telegram Examples Start-AB-DB1-DB2-CI-Stop Start-AB-CI-DB1-DB2-Stop Start-AB-DB1-Stop Start-AB-CI-Stop Start AB DB1 DB2 CI Stop = start condition = address byte = divider byte 1 = divider byte 2 = control information = stop condition Converter Mixer + VCO In the converter mixer the sound subcarriers (frequency band approx. 5 to 9 MHz) contained in the baseband of the received composite signal are converted to an output frequency of 10.52 MHz or 10.7 MHz for example. The two mixer outputs are designed as open-collector outputs. The VCO has internal feedback and its frequency of 15.5 to 19.7 MHz is determined by an external resonant circuit with a varactor diode that is tuned by the PLL. The resonant circuit is connected to the supply voltage by its low side. IF-Limiter with Demodulators The limiter amplifiers are implemented as balanced five-stage, capacitively coupled differential amplifiers. All there limiter inputs have a common reference (pin 22). The output signals of the limiter amplifiers are fed direct and via an external phase-shifter circuit to the coincidence demodulators. The AF-signals can be brought out an disconnectible (by Z2, Z1, Z0) AF output stages. The outputs are high-impedance when they are disconnected. Semiconductor Group 135 TDA 6160-2S Absolute Maximum Ratings TA = 0 to 70 °C Parameter Symbol Limit Values min. max. Unit Supply voltage V18, V28 0 6 V AF-output I8, I11, I14 – 1.5 3 mA AF-output V8, V11, V14 V16 V Demodulators V6/7, V9/10, V12/13 0 V16 V IF-inputs V17, V19, V21 0 V16 V Mixer outputs V23, V24 7 V VCO V4 7 V Crystal oscillator V1 1.5 V Junction temperature Tj 150 °C Storage temperature Tstg 125 °C Thermal resistance Rth SA 65 K/W 0 0 All voltage values are referred to ground (pin 20, pin 27), unless stated otherwise. All currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign, and if it is a source (the current flows from VS across the designated pin), it has a positive sign. Operating Range Supply voltage V18, V28 4.5 5.5 V Input frequency range of converter mixer fI26 5 9 MHz Input frequency range of sound IF-amplifiers (– 3 dB) fI17, 19, 21 5 15 MHz VCO-frequency fO4 5 20 MHz Ambient temperature TA 0 70 °C Semiconductor Group 136 TDA 6160-2S Characteristics VS = 5 V; TA = 25 °C Parameter Symbol Limit Values min. Unit typ. max. 33 42 mA Test Condition Current drain (analog section) I18 Current drain (digital section) I28 20 35 44 mA Phase-detector charge current IPD ± 32 ± 160 ± 40 ± 250 ± 75 ± 360 µA µA I 5I 3.5 mA V25 = V26 V25 = V26 Mixer Static Characteristics Mixer output currents I23, 24 1.1 Output-current difference I23 – I24 100 µA Mixer inputs V25, 26 3 V Input voltage for IMA > 60 dB V26 180 Input-frequency band fI26 Input-resistance R25/26 4 kΩ Output-frequency band f023/24 11 MHz Frequency band of VCO ∆f4 15 Mixer gain GMi –8 Dynamic Characteristics Output-voltage range on mixer Semiconductor Group 5 230 mVrms SC1 = 6 MHz; SC2 = 6.5 MHz; SC3 = 7 MHz; VSC1 = VSC2 = VSC3 9 MHz 20 MHz –2 dB RL = 470 Ω V18 V18 V – 0.4 max IMA > 55 dB; V25/26 < 180 mVrms 137 –4 TDA 6160-2S Characteristics (cont’d) Parameter Symbol Limit Values min. typ. Unit Test Condition max. Sound IF (for all three amplifiers) Static and Dynamic Characteristics Input-frequency band f17, 19, 21 5 15 MHz fI17, 19, 21 Input voltage to activate limiting (VqAF – 3 dB) V17, 19, 21 AF-output voltage V8, 11, 14 150 70 250 µV = 10.7 MHz; ∆f = 30 kHz; fmod = 1 kHz 220 300 mV fI17, 19, 21 = 10.7 MHz; ∆f = 30 kHz; VI17, 19, 21 = 10 mV, fmod = 1 kHz Distortion factor THD8, 11, 14 0.2 % fI17, 19, 21 = 10.7 MHz; ∆f = 30 kHz; VI17, 19, 21 = 10 mV, fmod = 1 kHz AM-rejection aAM 45 dB VI17, 19, 21 = 20 to 100 mV; m = 30% AM-rejection aAM 25 dB VI17 = 2 mV; m = 30% 2.2 V AF-output DC-voltage Design Notes Sound IF-input resistance R17/22 R19/22 R21/22 800 Ω Demodulator input resistance R6/7 R9/10 R12/13 30 kΩ AF-output resistance R8, 11, 14 100 Ω Residual IF-voltage VIF8, 11, 14 Hum suppression (without deemphasis) aH Semiconductor Group 5 25 138 mV dB VS = 5 V; VH = 250 mVpp; fH = 50 Hz TDA 6160-2S Characteristics (cont’d) Parameter Symbol Limit Values min. typ. Unit Test Condition max. I2C Bus (SCL, SDA) Edges SCL, SDA Rise time Fall time tR tF Shift clock SCL Frequency H-pulse width L-pulse width fSCL tH tL 0 4 4 Start Setup time Hold time tSUSTA tHDSTA 4 4 µs µs Stop Setup time Bus free tSUSTO tBUF 4 4 µs µs Data change Setup time Hold time tSUDAT tHDDAT 1 1 µs µs VIH VIL 2.4 Inputs SCL, SDA Input voltage 1 300 µs ns 100 kHz µs µs 5.5 1 V V 10 10 µA µA Input current IIH IIL Output SDA (open collector) Output voltage VQH VQL 4.5 5.5 0.4 V V Address byte 1 = L V5L 0 1 V Address byte 2 = H or open V5H 2.4 5.5 V Semiconductor Group 139 RL = 2.5 kΩ IQL = 3 mA TDA 6160-2S Test Circuit Semiconductor Group 140 TDA 6160-2S Application Circuit Semiconductor Group 141 TDA 6160-2S I2C Bus Timing Diagram tSUSTA tHDSTA tH tL tSUDAT tHDDAT tSUSTO tBUF tF tR Setup time (start) Hold time (start) H-pulse width (clock) L-pulse width (clock) Setup time (data change) Hold time (data change) Setup time (stop) Bus free time Fall time Rise time All times referred to VIH and VIL values Semiconductor Group 142 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.