Supertex inc. HV230 Low Charge Injection, 8-Channel, High Voltage Analog Switches with Bleed Resistors Features General Description XHVCMOS X technology for high performance XVery X low quiescent power dissipation (-10µA max.) XOutput X on-resistance typically (22Ω typ.) XIntegrated X bleed resistors on the outputs XLow X parasitic capacitances ►► DC to 50MHz small signal frequency response X-60dB X typical output OFF isolation at 5.0MHz XCMOS X logic circuitry for low power XExcellent X noise immunity XON-chip X shift register, latch and clear logic circuitry XFlexible X high voltage supplies The Supertex HV230 is a low charge injection 8-channel, high-voltage, analog switch integrated circuit (IC) with bleed resistors. This device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, Latch Enable (LE) should be left high until all bits are clocked in. Using HVCMOS® technology, this switch combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. ® Applications XX Medical ultrasound imaging XX Piezoelectric transducer drivers This IC is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +50V/-150V, or +100V/-100V. Block Diagram Latches Level Shifters D LE CL DIN CLK 8-Bit Shift Register DOUT VDD Doc.# DSFP-HV230 C071613 LE CL Output Switches SW0 D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 VNN VPP RGND Supertex inc. www.supertex.com HV230 Pin Configuration Ordering Information 26 Part Number Package Option Packing HV230G1-G 26-Lead LLGA 400/Tray HV230GA-G 26-Ball fpBGA Consult factory 18 1 -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings 2 Parameter Value VDD logic power supply voltage 10 26-Lead LLGA -0.5V to +15V VPP - VNN supply voltage (top view) 220V VPP positive high voltage supply 1 -0.5V to VNN +200V +0.5V to -200V B Logic input voltages -0.5V to VDD +0.3V D Analog signal range VNN to VPP VNN negative high voltage supply Peak analog signal current/channel 1.0W 1.0W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Typical Thermal Resistance Package θja 26-Lead LLGA 41OC/W 26-Ball fpBGA - 4 5 6 7 8 9 E F G H -65OC to +150OC Power dissipation: 26-Lead LLGA 26-Ball fpBGA 3 C 3.0A Storage temperature 2 A 26-Ball fpBGA (top view) Product Marking YYWW HV230G1 LLLLLLLL YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging Package may or may not include the following marks: Si or 26-Lead LLGA YYWW HV230GA LLLLLLL YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging Package may or may not include the following marks: Si or 26-Ball fpBGA Operating Conditions Sym Parameter Value VDD Logic power supply voltage 1,3 VPP Positive high voltage supply VNN Negative high voltage supply VIH High level input voltage VIL Low-level input voltage VSIG Analog signal voltage peak-to-peak TA 4.5V to 13.2V 40V to VNN +200V 1,3 -40V to -160V 1,3 VDD -1.5V to VDD 0V to 1.5V VNN +10V to VPP -10V 2 Operating free air temperature 0OC to 70OC Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Doc.# DSFP-HV230 C071613 2 Supertex inc. www.supertex.com HV230 DC Electrical Characteristics (Over operating conditions unless otherwise specified ) Sym Parameter 0OC +25OC Min Max Min +70OC Typ Max Min Max Unit Conditions - 30 - - 38 - 48 - 25 - - 27 - 32 - 25 - - 27 - 30 - 18 - - 24 - 27 - 23 - - 25 - 30 - 22 - - 25 - 27 Small signal switch ON-resistance matching - 20 - - 20 - 20 % RONL Large signal switch ON-resistance ISIG = 5.0mA, VPP = +100V, VNN = -100V - - - 15 - - - Ω VSIG = VPP -10V, ISIG = 1.0A RINT Output switch shunt resistance - - 20 - 50 - - KΩ ISOL Switch OFF leakage per switch Output switch to RGND IRINT = 0.5mA - 5.0 - - 10 - 15 μA VSIG = VPP -10V DC offset switch OFF - 300 - - 300 - 300 mV No load DC offset switch ON - 500 - - 500 - 500 mV No load IPPQ Quiescent VPP supply current - - - - 50 - - μA All switches OFF INNQ Quiescent VNN supply current - - - - -50 - - μA All switches OFF IPPQ Quiescent VPP supply current - - - - 50 - - μA All switches ON, ISW = 5.0mA INNQ Quiescent VNN supply current - - - - -50 - - μA All switches ON, ISW = 5.0mA ISW Switch output peak current - 3.0 - 2.0 - 2.0 A VSIG duty cycle -0.1% fSW Output switching frequency - - - - 50 - - kHz - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 RONS ΔRONS VOS IPP INN Small signal switch ON-resistance Supply current Supply current ISIG = 5.0mA VPP = +40V ISIG = 200mA VNN = -160V Ω ISIG = 5.0mA VPP = +100V ISIG = 200mA VNN = -100V ISIG = 5.0mA VPP = +160V ISIG = 200mA VNN = -40V Duty cycle = 50% VPP = +40V VNN = -160V mA All output switches are VPP = +100V turning On and Off at VNN = -100V 50kHz with VPP = +160V no load VNN = -40V VPP = +40V VNN = -160V mA All output switches are VPP = +100V turning On and Off at VNN = -100V 50kHz with VPP = +160V no load VNN = -40V IDD Logic supply average current - 4.0 - - 4.0 - 4.0 mA fCLK = 5.0MHz, VDD = 5.0V IDDQ Logic supply quiescent current - 10 - - 10 - 10 μA --- ISOR Data out source current 0.45 - 0.45 - - 0.40 - mA VOUT = VDD -0.7V ISINK Data out sink current 0.45 - 0.45 - - 0.40 - mA VOUT = 0.7V CIN Logic input capacitance - 10 - - 10 - 10 pF --- Doc.# DSFP-HV230 C071613 3 Supertex inc. www.supertex.com HV230 AC Electrical Characteristics (Over recommended operating conditions, V 0 C +25 C O Sym Parameter Min Max Min DD = 5.0V, unless otherwise specified) +70 C O O Typ Max Min Max Unit Conditions tSD Set up time before LE rises 150 - 150 - - 150 - ns --- tWLE Time width of LE 150 - 150 - - 150 - ns --- tDO Clock delay time to data out 55 150 60 - 150 70 150 ns --- tWCL Time width of CL 150 - 150 - - 150 - ns --- tSU Set up time data to clock 15 - 15 - - 20 - ns --- tH Hold time data from clock 35 - 35 - - 35 - ns --50% Duty cycle, fDATA = fCLK/2 fCLK Clock frequency - 5.0 - - 5.0 - 5.0 MHz tR, tF Clock rise and fall times - 1.0 - - 1.0 - 1.0 μs --- tON Turn ON time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP - 10V, RL = 10kΩ tOFF Turn OFF time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP - 10V, RL = 10kΩ - 20 - - 20 - 20 - 20 - - 20 - 20 - 20 - - 20 - 20 -30 - -30 - - -30 - -58 - -58 - - -58 - -60 - -60 - - -60 - dB f = 5.0MHz, 50Ω load - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle CSG(OFF) OFF capacitance SW to GND 5.0 17 5.0 - 17 5.0 17 pF 0V, f = 1.0MHz CSG(ON) 25 50 25 - 50 25 50 pF 0V, f = 1.0MHz +VSPK - - - - 150 - - -VSPK - - - - 150 - - - - - - 150 - - - - - - 150 - - +VSPK - - - - 150 - - -VSPK - - - - 150 - - dv/dt Maximum VSIG slew rate KO OFF isolation KCR Switch crosstalk IID +VSPK -VSPK Output switch isolation diode current ON capacitance SW to GND Output voltage spike Doc.# DSFP-HV230 C071613 4 VPP = +160V, VNN = -40V V/ns VPP = +100V, VNN = -100V VPP = +40V, VNN = -160V dB f = 5.0MHz, 1.0kΩ/15pF load f = 5.0MHz, 50Ω load VPP = +40V, VNN = -160V, RL = 50Ω mV VPP = +100V, VNN = -100V, RL = 50Ω VPP = +160V, VNN = -40V, RL = 50Ω Supertex inc. www.supertex.com HV230 Truth Table D0 D1 D2 D3 D4 D5 D6 D7 LE CLK SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF H L L ON L L L OFF H L L ON L L OFF ON L H L L L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON X X X X X X X X H L Hold Previous State X X X X X X X X X H All Switches OFF Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch. 4. DOUT is high when data in the shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. Logic Timing Waveforms DN+1 DN DATA IN 50% LE 50% DN-1 50% 50% tWLE tSD 50% CLOCK 50% tSU th tDO DATA OUT VOUT (typ) tOFF OFF tON 90% 10% ON CLR Doc.# DSFP-HV230 C071613 50% 50% tWCL 50% 5 Supertex inc. www.supertex.com HV230 Test Circuits VPP –10V VPP –10V ISOL RL 10KΩ VOUT VOUT Open RGND Open RGND VPP VPP VDD VNN VNN GND 5.0V RGND VPP VPP VDD VNN VNN GND 5.0V VPP VPP VDD VNN VNN GND TON/TOFF Test Circuit DC Offset ON/OFF Switch OFF Leakage 5.0V VIN = 10 VP–P @5MHz VIN = 10 VP–P @5MHz VSIG 50Ω IID VOUT VNN RL RGND VPP VNN 50Ω RGND RGND VPP NC VDD VNN 5.0V GND KO = 20Log VPP VPP VDD VNN VNN GND 5.0V VPP VPP VDD VNN VNN GND VOUT VIN KCR = 20Log OFF Isolation Isolation Diode Current 5.0V VOUT VIN Crosstalk +VSPK DVOUT VOUT VOUT –VSPK 1000pF RL 50Ω RGND VSIG 1KΩ RGND VPP VPP VDD VNN VNN GND 5.0V VPP VPP VDD VNN VNN GND 5.0V Q = 1000pF x DVOUT Charge Injection Doc.# DSFP-HV230 C071613 Output Voltage Spike 6 Supertex inc. www.supertex.com HV230 Pin Description (26-Lead LLGA) Pin Function Pin Function 1 SW4 14 VDD 2 SW3 15 DIN 3 SW3 16 CLK 4 SW2 17 LE 5 SW2 18 CL 6 SW1 19 DOUT 7 SW1 20 SW7 8 SW0 21 SW7 9 SW0 22 SW6 10 VPP 23 SW6 11 VNN 24 SW5 12 RGND 25 SW5 13 GND 26 SW4 Pin Description (26-Ball fpBGA) Ball Location Function Ball Location Function A4 SW1 E1 SW4 C3 SW2 E3 SW4 C4 SW1 E4 SW5 C5 SW0 E5 SW7 C6 VPP E6 LE C7 VNN E7 CLK D1 SW3 E9 DIN D3 SW3 F3 SW5 D4 SW2 F4 SW6 D5 SW0 F5 SW7 D6 RGND F6 DOUT D7 GND F7 CLR D9 VDD H4 SW6 Doc.# DSFP-HV230 C071613 7 Supertex inc. www.supertex.com HV230 26-Lead LLGA Package Outline (G1) 6.00x6.00mm body, 0.60mm height (max), 0.65mm pitch D 26 e d2 d3 Note 1 (Index Area D/2 x E/2) 1 d1 L1 d4 Note 1 (Index Area D/2 x E/2) E Pin 1 Detail B 7xe e Detail A x25 Pin 2 2 d4 d3 L1 Top View d1 7xe b Seating Plane A d2 Bottom View b L A1 Side View L Detail A Detail B 0.10 x 45O Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 Identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A A1 b D MIN 0.50 0.00 0.25 5.90 NOM 0.55 - 0.35 6.00 MAX 0.60 0.05 0.45 6.10 d1 1.050 REF d2 0.400 REF d3 0.725 REF d4 0.925 REF E 5.90 6.00 6.10 e 0.65 BSC L 0.25 0.35 0.45 L1 0.10 REF Drawings not to scale. Supertex Doc. #: DSPD-26LLGAG1, Version A090808. Doc.# DSFP-HV230 C071613 8 Supertex inc. www.supertex.com HV230 26-Ball fpBGA Package Outline (GA) 6.00x5.35mm body, 1.20mm height (max), 0.65mm pitch D 9 8 7 6 5 4 3 2 1 Note 2 A B Terminal A1 Corner Index Area (D/4 x E/4) Note 1 C E E1 D SE E e F G H e Top View SD D1 Bottom View A2 View B Seating Plane A A1 Φb View B Side View Notes: 1. A Ball A1 identifier must be located in the index area indicated. The Ball A1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Corner A1 identifier (actual shape may vary). A A1 A2 Φb D MIN 0.844 0.18 0.664 0.25 5.90 NOM 0.994 0.23 0.764 0.30 6.00 MAX 1.200 0.28 0.864 0.35 6.10 Symbol Dimension (mm) D1 5.20 BSC E 5.25 5.35 5.45 E1 e SD SE 4.55 BSC 0.65 BSC 0.65 BSC 0.325 BSC Drawings not to scale. Supertex Doc. #: DSPD-26fpBGAGA, Version A092208. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV230 C071613 9 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com