NTE7133 Integrated Circuit Horizontal and Vertical Deflection Controller for VGA/XGA and Autosync Monitors Description: The NTE7133 is an integrated circuit in a 20–Lead DIP type package. This device is designed to provide an economical solution in VGA/XGA and autosync monitors by incorporating complete horizontal and vertical small signal processing. VGA–dependent mode detection and setting are performed on–chip. Features: D VGA Operation Fully Implemented Including Alignment–Free Vertical and E/W Amplitude Pre–Settings D 4th VGA Mode Easy Applicable (XGA, Super VGA) D Autosync Operation Externally Selectable D Low Jitter D All Adjustments DC–Controllable D Alignment–Free Oscillators D Sync Separators for Video or Horizontal and Vertical TTL Sync Levels Regardless or Polarity D Horizontal Oscillator with PLL1 for Sync and PLL2 for Flyback D Constant Vertical and E/W Amplitude in Multi–Frequency Operation D DC–Coupling to Vertical Power Amplifier D Internal Supply Voltage Stabilization with Excellent Ripple Rejection to Ensure Stable Geometrical Adjustments Absolute Maximum Ratings: Supply Voltage (Pin1), VP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to +16V Voltage (Pin3, Pin7), V3, V7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to +16V Voltage (Pin8), V8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to +7V Voltage (Pin5, Pin6, Pin9, Pin10, Pin13, Pin14, Pin18), Vn . . . . . . . . . . . . . . . . . . . . . . –0.5 to +6.5V Current (Pin2), I2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Current (Pin3), I3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Current (Pin7), I7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Current (Pin8), I8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10mA Electrostatic Handling for All Pins (Note 1), Vesd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400V Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Operating Ambient Temperatrure Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Thermal Resistance, Junction–to–Ambient (In Free Air), RthJA . . . . . . . . . . . . . . . . . . . . . . . . 65K/W Note 1. Equivalent to discharging a 200pF capacitor through a 0Ω series resistor. Electrical Characteristics: (VP = 12V, TA = +25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 9.2 12.0 16.0 V I18 = –1.05mA – 36 44 mA I18 = –3.388mA – 40 49 mA 6.0 6.25 6.5 V Supply Positive Supply Voltage (Pin1) VP Supply Current IP Internal Reference Voltage Internal Reference Voltage Temperature Coefficient Power Supply Ripple Rejection Supply Voltage (Pin1) to Ensure All Internal Reference Voltages Vref TC TA = +20° to +100°C – – ±90 10–6/K PSRR f = 1kHz Sine Wave 60 75 – dB f = 1MHz Sine Wave 25 35 – dB 9.2 – 16.0 V – 300 – mV 1.1 1.28 1.5 V Sync on Green, RS = 50Ω 90 120 150 mV VP Composite Sync Input (AC–Coupled, V10 = 5V) Sync Amplitude of Video Input Signal (Pin9) Vi sync Sync on Green Top Sync Clamping Level Slicing Level Above Top Sync Level Allowed Source Resistance for 7% Duty Cycle RS Vi sync > 200mV – – 1.5 kΩ Differential Input Resistance r9 During Sync – 80 – Ω Charging Current of Coupling Capacitor I9 V9 > 1.5V 1.3 2.0 3.0 µA Vertical Sync Integration Time to Generate Sync Pulse tint fH = 31kHz, I18 = –1.050mA 7 10 13 µs fH = 64kHz, I18 = –2.169mA 3.5 5.0 6.5 µs fH = 100kHz, I18 = –3.388mA 2.5 3.4 4.5 µs 1.7 – – V 1.2 1.4 1.6 V tp 700 – – ns tr, tf 10 – 500 ns V9 = 0.8V – – –200 µA V9 5.5V – – 10 µA tp H/tH – – 30 % tp 0.3 – 1.8 ms 1.7 – – V 1.2 1.4 1.6 V – – ±10 µA – – 300 µs 0.275 0.33 V Horizontal Sync Input (DC–Coupled, TTL–Compatible) Sync Input Signal (Peak Value, Pin9) Vu sync Slicing Level Minimum Pulse Width Rise Time and Fall Time Input Current I9 Automatic Horizontal Polarity Switch (H–Sync on Pin9) Horizontal Sync Pulse Width Related to tH (Duty Cycle for Automatic Polarity Correction) Delay Time for Changing Sync Polarity Vertical Sync Input (DC–Coupled, TTL–Compatible,,V–Sync on Pin10) Sync Input Signal (Peak Value, Pin10) Vi sync Slicing Level Input Current I10 Maximum Vertical Sync Pulse Width for Automatic Vertical Polarity Switch tp V 0 < V10 < 5.5V Horizontal Mode Detector Output (VGA Mode) Output Saturation Voltage LOW (For Modes 1, 2, and 3) V7 Output Voltage HIGH Load Current to Force VGA Mode–Dependent Vertical and Parabola Amplitudes Output Current I7 I7 = 6mA – Mode 4 – – VP V Modes 1, 2, and 3 2 – 6 mA Mode 4 – 0 – mA Electrical Characteristics (Cont’d): (VP = 12V, TA = +25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit V7 0 – 50 mV Upper Control Voltage Limitation Lower Control Voltage Limitation V17 – 5.9 – V – 5.1 – V Control Current I17 – ±0.083I18 – µA – 31.45 – kHz ±3.0 % VGA/Autosync Mode Switch Input Voltage LOW to Force Autosync Mode Horizontal Comparator PLL1 Horizontal Oscillator Center Frequency fOSC Deviation of Center Frequency ∆fOSC – – TC – +200 +300 10–6/K ϕH/tH ±6.0 ±6.5 ±7.3 % External Oscillator Current I18 –0.5 – –4.3 mA Voltage at Reference Current Input (Pin18) V18 2.35 2.5 2.65 V I2 = 6mA – 5.5 – V I2 = –1mA – –0.75 – V – 3.0 – V Temperature Coefficient Relative Holding/Catching Range R18 = 2.4kΩ (Pin18), C19 = 10nF (Pin19) Horizontal PLL2 Upper Clamping Level of Flyback Input V2 Lower Clamping Level of Flyback Input H–Flyback Slicing Level Delay Between Middle of Sync and Middle of H–Flyback Related to tH td/tH – 3.0 – % Upper Control Voltage Limitation V20 – 6.2 – V – 4.8 – V I20 – ±0.083I18 – µA ∆t/tH 30 – – % I3 = 20mA – – 0.3 V I3 = 60mA – – 0.8 V 42 45 48 % Horizontal Output OFF – 5.6 – V Horizontal Output ON – 5.8 – V f = 31kHz – – 3.5 ns f = 64kHz – – 1.9 ns f = 100kHz – – 1.2 ns – – 0.9 V Lower Control Voltage Limitation Control Current PLL2 Control range Related to tH Horizontal Output (Open–Collector) Output Voltage LOW V3 tH Duty Cycle tp/tH Threshold to Activate Too Low Supply Voltage Protection VP Threshold to Activate Too Low Supply Voltage Protection Jitter of Horizontal Output ∆tH Horizontal Clamping/Blanking Generator Output Output Voltage LOW V8 Blanking Output Voltage Internal V Blanking 1.6 1.9 2.2 V Clamping Output Voltage H–Sync on Pin9 5.15 5.4 5.65 V H and V Scanning 2.3 2.9 3.5 mA – – –3.0 mA Internal Sink Current for All Output Levels I8 External Load Current Clamping Pulse Start t8 With End of H–Sync Clamping Pulse Width tclp 0.8 1.0 1.2 µs Steepness of Rise and Fall Times S – 60 75 ns/V Electrical Characteristics (Cont’d): (VP = 12V, TA = +25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Vertical Oscillator (Vref = 6.25V) Vertical Free–Running Frequency fo R15 = 22kΩ, C16 = 0.1µF – 42 – Hz Nominal Vertical Sync Range fV No fo Adjustment 50 – 110 Hz R15 = 22kΩ 2.8 3.0 3.2 V Measured on Pin8, Activated by an External Resistor on Pin7 500 575 650 µs Measured on Pin8, V7 < 50mV 240 300 360 µs Voltage on Pin15 Delay Between Sync Pulse and Start of Vertical Scan in VGA/XGA Mode V15 td Delay Between Sync Pulse and Start of Vertical Scan in Autosync Mode Control Current for Amplitude Control I12 – ±200 – µA Capacitor for Amplitude Control C12 – – 0.18 µF 0.9 1.0 1.1 mA – – ±2.5 % – – ±1.5 % – 5.0 – V –110 –120 –135 µA – 0 – µA Vertical Differential Output Differential Output Current Between Pin5 and Pin6 (Peak–to–Peak Value) Io Maximum Offset Current Error Mode 3, I13 > –135µA, R15 = 22kΩ Io = 1mA Maximum Linearity Error Vertical Amplitude Adjustment (In Percent of Output Signal) Input Voltage V13 Adjustment Current I13 Iomax (100%) Iomin (Typically 58%) VGA Mode–Dependent Pre–Settings Activated by an External Resistor on Pin7 Mode 1 ∆Io/∆t Table 2,Note 2 Mode 2 116.1 116.8 117.4 % 101.6 102.2 102.8 % Mode 3 – 100 – % Mode 4 – 100 – % – 100 – % 1.05 1.2 1.35 V 4.2 4.5 4.8 V Autosync Operation (VGA Operation Disabled) Table 2, Note 2, V7 < 50mV E/W Output (Note 2) Bottom Output Signal During Mid–Scan (Pin11) V11 Internally Stabilized Top Output Signal During Flyback TC – – 250 10–6/K Input Voltage (Pin14) V14 – 5.0 – V Adjustment Current I14 –110 –120 –135 µA – 0 – µA Temperature Coefficient of Output Signal E/W Amplitude Adjustment (Parabola) 100% Parabola Typicall 28% Parabola Note 2. ∆Io/∆t relative to value of Mode 3. Note 3. Parabola amplitude tracks with mode–dependent vertical amplitude but not with vertical amplitude adjustment. Tracking can be achieved by a resistor from vertical amplitude potentiometer to Pin14. Functional Description: Horizontal Sync Separator and Polarity Correction An AC–coupled video signal or a DC–coupled TTL sync signal (H only or composite sync) is input on Pin9. Video signals are clamped with top sync on 12.8V, and are sliced at 1.4V. This results in a fixed absolute slicing level of 120mV relative to top sync. DC–coupled TTL sync signals are also sliced at 1.4V, however with the clamping circuit in current limitation. The polarity of the separated sync is detected by internal integration of the signal, then the polarity is corrected. The polarity information is fed to the VGA mode detector. The corrected sync is the input signal for the vertical sync integrator and the PLL1 stage. Vertical Sync Separaztor, Polarity Correction and Vertical Sync Integrator DC–coupled vertical TTL sync signals may be applied to Pin10. They are sliced at 1.4V. The polarity of the separated sync is detected by internal integration, then polarity is corrected. The polarity information is fed to the VGA mode detector. If Pin10 is not used, it must be connected to GND. The separated Vi sync signal from Pin10, or the integrated composite sync signal from Pin9 (TTL or video) directly triggers the vertical oscillator. VGA Mode Detector and Mode Output The three standard VGA modes and a 4th not fixed mode are decoded by the polarities of the horizontal and the vertical sync input signals. An external resistor (from VP to Pin7) is necessary to match this function. In all three VGA modes the correxct amplitudes are activated. The presence of the 4th mode is indicated by HIGH on Pin7. This signal can be used externally to switch any horizontal or vertical parameters. VGA Mode Detector Input For autosync operation the voltage on Pin7 must be externally forced to a level of < 50mV. Vertical amplitude pre–settings for VGA are then inhibited. The delay time between vertical trigger pulse and the start of vertical deflection changes from 575 to 300µs (575µs is needed for VGA). The vertical amplitude then remains constant in a frequency range from 50 to 110Hz. Clamping and V–Blanking Generator A combined clamping and V–blanking pulse is available on Pin8. The lower level of 1.9V is the blanking signal derived from the vertical blanking pulse from the internal vertical oscillator. Vertical blanking equals the delay between vertical sync and the start of vertical scan. By this, an optimum blanking is acheived for VGA/XGA as well as for multi–frequency operation (selectable via Pin7). The upper level of 5.4V is the horizontal clamping pulse with internally fixed pulse width of 0.8µs. A mono flop, which is triggered by the trailing edge of the horizontal sync pulse, generates this pulse. If composite sync is applied one clamping pulse per H–period is generated during V–sync. The pahse of the clamping pulse may change during V–sync. PLL1 Phase Detector The phase detector is a standard one using switched current sources. The middle of the sync is compared with a fixed point of the oscillator sawtooth voltage. The PLL filter is connected to Pin17. If composite sync is applied, the distributed control voltage is corrected during V–sync. Horizontal Oscillator This oscillator is a relaxation type and requires a fixed capacitor of 10nF at Pin19. By changing the current into Pin18 the whole frequency range from 13 to 100kHz can be covered. The current can be generated either by a frequency to voltage converter or by a resistor. A frequency adjustment may also be added if necessary. The PLL1 control voltage at Pin17 moduloates via a buffer stage the oscillator thresholds. A high DC– loop gaqin ensures a stable phase relationship between horizontal sunc and line flyback pulses. Functional Description (Cont’d): PLL2 Phase Detector This pahse detector is similar to the PLL1 phase detector. Line flyback signals (Pin2) are compared with a fixed point of the oscillator sawtooth voltage. Delays in the horizontal deflection circuit are compensated by adjusting the phase relationship between horizontal sync and horizontal output pulses. A certain amount of phase adjustment is possible by injecting a DC current froma an external source into the PLL2 filter capacitor on Pin20. Horizontal Driver This open–collector output stage (Pin3) can directly drive an external driver transistor. The saturation voltage is 300mV at 20mA. To protect the line deflection transistor, the horizontal output stage does not conduct at VP < 6.4V (Pin1). Vertical Oscillator and Amplitude Control This stage is designed for fast stabilization of the vertical amplitude after changes in sync conditions. The free–running frequency fo is determined by the values of RVOS and CVOS. The recommended values should be altered marginally only to preserve the excellent linearity and noise performance. The vertical drive currents I5 and I6 are in relation to the value of RVOS. Therefore, the oscillator frequency must be determined only by CVOS on Pin16. 1 10.8 x RVOS x CVOS fo = To acheive a stabilized amplitude the free–running frequency fo (without adjustment) must be lower than the lowest occurring sync frequency. The contributions shown in Table 1 can be assumed. Table 1. Calculation of fo Total Spread Contributing Elements % Minimum Frequency Offset Between fo and the Lowest Trigger Frequency 10 Spread of IC ±3 Spread of R (22kΩ) ±1 Spread of C (0.1µF) ±5 Total 19 Results for 50 to 110Hz application: fo = 50Hz = 42Hz 1.19 Table 2. VGA Modes Mode Horizontal/Vertical Sync Polarity Horizontal Frequency (kHz) Vertical Frequency (Hz) Number of Active Lines Output Mode Pin7 1 +/– 31.45 70 350 LOW 2 –/+ 31.45 70 400 LOW 3 –/– 31.45 60 480 LOW 4 +/+ Fixed by External Circuitry – – HIGH Autosync */* Fixed by External Circuitry – – Forced to GND Pin Connection Diagram VP 1 Horiz Flyback Input 2 Horiz Output 3 GND (0V) 4 Vert Output 1/Neg–Going Sawtooth 5 Vert Output 2/Pos–Going Sawtooth 6 4th Mode Output/Autosync In 7 Clamping/Blanking Pulse Out 8 Horiz Sync/Video In 9 Vert Sync In 10 20 20 19 18 17 16 15 14 13 12 11 PLL2 Phase Horiz OSC Capacitor Horiz OSC Resistor PLL1 Phase Vert OSC Capacitor Vert OSC Resistor E/W Amp Adj Input (Parabola) Vert Amp Adj Input Cap for Amp Control E/W Output (Parabola to Driver Stage) 11 .280 (7.12) Max 1 10 .995 (25.3) Max .300 (7.62) .280 (7.1) .100 (2.54) .125 (3.17) Min .385 (9.8)