STEVAL-VNH5019A Motor driver evaluation board based on VNH5019A Data brief Description STEVAL-VNH5019A offers dedicated power stage and controls suitable for electric DC motor driving. This evaluation board comes pre-assembled with VNH5019A H-bridge belonging to the VNH Motor Driver series based on VIPower® proprietary technology. Typical applications are Windows Lift, Sliding Door, Seat regulation. This Evaluation Board consists of a motherboard (STM8 Universal Board) and a daughterboard. Features Type RDS(on) Iout VCC(max) VNH5019A-E 18 mΩ typ (per leg) 30 A 41 V • Handling up to 30 A of maximum motor current output • Undervoltage and overvoltage shutdown • Device thermal protection • Cross-conduction protection The motherboard, based on STM8 microcontroller, provides the logic section for monitoring and driving the VNH5019A assembled in the daughterboard. With the aim to make simpler the board usage and settings, ST provides a dedicated and userfriendly software with a Graphic User Interface (GUI). This enables the user to set VNH5019A parameters (PWM, Motor direction…) and at the same time it shows real time device diagnostic information like current output evolution, battery voltage monitoring, board temperature and much more. • Very low standby power consumption • Programmable PWM operation (up to 20 kHz) • Protection against loss of ground and loss of VCC • Motor current monitoring (thanks to VNH5019A current sense output) • On-board charge pump output for reverse polarity protection • Device output protected against short to ground and short to VCC • Graphic User Interface (GUI) September 2013 Table 1. Device summary Order code STEVAL-VNH5019A DocID025030 Rev 3 For further information contact your local STMicroelectronics sales office. Reference VNH5019A evaluation board 1/12 www.st.com Application schematics and layouts 1.1 VNH5019A daughterboard Figure 1. VNH5019A daughterboard top layer Application schematics and layouts 2/12 1 DocID025030 Rev 3 STEVAL-VNH5019A STEVAL-VNH5019A Figure 2. VNH5019A daughterboard bottom layer DocID025030 Rev 3 Application schematics and layouts 3/12 Daughterboard Socket1 STM8UB_DB1 2 DocID025030 Rev 3 VBAT_SENSE IN_B/I NP UT2 IN_A/I NP UT1 EN/DI G_A/STATUS3 CS_DI S INP UT3 INP UT4 EN/DI G_B/STATUS4 (I N_)P WM ID3 ID2 ID1 ID0 +5V_DB +5V_P erm PB0/AI N0/TI M1_NCC1 PB1/AI N1/TI M1_NCC2 PB2/AI N2/TI M1_NCC3 PB3/AI N3 PB4/AI N4 PB5/AI N5 PB6/AI N6 PB7/AI N7 PE7/AI N8 PE6/AI N9 PF0/AI N10 PF3/AI N11 PF4/AI N12 PF5/AI N13 PF6/AI N14 PF7/AI N15 PA3/TI M2_CC3 PC0/ADC_ETR PC1(HS)/TI M1_CC1 PC2(HS)/TI M1_CC2 PC3(HS)/TI M1_CC3 PC4(HS)/TI M1_CC4 PD0(HS)/TI M3_CC2 PD2(HS)/TI M3_CC1 PD3(HS)/TI M2_CC2 PD4(HS)TI M2_CC1 PD7/TL I PE0/CL K _CCO PE3/TI M1_BK IN PE4 PH7/TI M1_NCC1 PH6/TI M1_NCC2 PH5/TI M1_NCC3 PH4/TI M1_ETR PH3 PH2 PH1(HS) PH0(HS) 1 J1 VCC NR E SE T PA 6/USA R T _C X PA 5/USA R T _T X PA 4/USA R T _R X PD5/LI NUA R T _T X PD6/LI NUA R T _R X PG0/CA N_T X PG1/CA N_R X PE 5/SPI_NSS PC5/SPI_SC K PC6/SPI_MOSI PC7/SPI_MI SO PE 1/I2C_SC L PE 2/I2C_SDA L IN L IN_PU USB _C B 2 USB _C B 3 CA N_HI CA N_L O +5V _SW B T N_COM B T N_A B T N_B L E D1 L E D2 L E D3 L E D4 IO_CON1 IO_CON2 IO_CON3 IO_CON4 IO_CON5 IO_CON6 IO_CON7 IO_CON8 IO_CON9 IO_CON10 IO_CON11 IO_CON12 TEMP A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 STEVAL-VNH5019A B1 B2 B3 B4 B5 B6 B7 B8 B9 B 10 B 11 B 12 B 13 B 14 B 15 B 16 B 17 B 18 B 19 B 20 B 21 B 22 B 23 B 24 B 25 B 26 B 27 B 28 B 29 B 30 B 31 B 32 B 33 B 34 B 35 B 36 B 37 B 38 B 39 B 40 +5V CS ext1 ext2 ext3 ext4 ext5 ext6 ext7 ext8 ext9 ext10 GND GND GND GND GND GND GND GND GND GND GND_V IP V s_A V s_A V s_A V s_B V s_B V s_B V s_B V s_B V s_B V s_B V s_B V s_B V s_B V s_B V s_B V s_B V S_B V s_Per CP D40 D39 D38 D37 D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DGND Application schematics and layouts 4/12 Figure 3. VNH5019A daughterboard application schematic (part 1) - ,' ,' ,' ,' 287$ 287$ 9 5 - 287% 287% . &21 9&& $' 5 '*1' 73 9&& 9 5 7HPSHUDWXUH 6HQVRU 7(03 . $ &3 & 9 9 /0 67'1) 4 9&& [ *1' 9 9&& 8 &21 3: 5(6 9%$7 STEVAL-VNH5019A Figure 4. VNH5019A daughterboard application schematic (part 2) &6', 6 287$ ,1B$, 1387 . 5 &6B', 6 5 (1%',$*% ,1% ,1B%, 1387 5 5 . &3 . 9%$7 & 9&& X) 9 9 9 287$ 1& *1'$ *1'$ *1'$ 287$ 1& 9&& 1& 287% *1'% *1'% *1'% 1& 287% 5 [ 287$ 287% *1' *1' 9&& ,1$ (1$',$*$ 3:0 &6B (1%',$*% ,1% 9&& 9%$7 9&& - 287% *1' - 91+ 287$ 1& 9&& ,1$ (1$',$*$ &6B', 6 3:0 &6 (1%',$*% ,1% &3 9%$7 9&& 1& 287% 287$ 1& *1'$ *1'$ *1'$ 287$ 1& 9&& 1& 287% *1'% *1'% *1'% 1& 287% *1' 287$ 9&& 287% *1' 287% &3 9%$7B6(16( [ & 5 . $ *1' ,1 5 '*1' 5 3*1' 3*1' 5 5 '*1' Q - 5 915+( '*1' $ ' '=! 9 & . ' *)% 3: 5(6 5 5 . 4 67'1) 1& 6RXUFH 6RXUFH 6RXUFH 6RXUFH 9%$7 'UDLQ '= & Q 9&& 5 . 60$-&$75 . '*1' 9%$7 3*1' 5/12 Application schematics and layouts &6 &6B - 8 9&& 5 . (1', *B%67$786 ,1$ (1$',$*$ &6', 6 3:0 &6B . DocID025030 Rev 3 ,1B3:0 5 . 287$ 1& 9&& ,1$ (1$',$*$ &6B', 6 3:0 &6 (1%',$*% ,1% &3 9%$7 9&& 1& 287% . 8 5 (1', *B$67$786 5 & 91+ 9&& 8 5 . 5 [ 287$ X) 9 6/12 Figure 5. STM8 motherboard top layer Application schematics and layouts STM8 motherboard 1.2 DocID025030 Rev 3 STEVAL-VNH5019A STEVAL-VNH5019A Figure 6. STM8 motherboard bottom layer DocID025030 Rev 3 Application schematics and layouts 7/12 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 (;7B% 9VB3(50 9VB3(50 9VB&KB$ 9VB&KB$ 9VB&KB% 9VB&KB% 9B3(50 9B3(50 9B'% 9B'% 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 9VB&KB$ 9VB&KB% 9VB3(50 9B3(50 9B'% 9B6: (;B, &&B5(6( 7 (;B, &&B'$7$ 6:,0 (;B, &&B&/ 2&. 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/,1B8$57B5 ; 3'7/ , 5 =' %=9& 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3'+67, 0B&& 5 5 5 *1' 5 *1' 5 5 *1' & & 9 5 =' %=9& *1' 5 & & 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 &$1B+, &$1B/2 5 5 5 5 3' 3' 3' 3' 3' 3' 3' 3&$'&B(75 3&+67 , 0B&& 3&+67 , 0B&& 3&+67 , 0B&& 3&+67 , 0B&& 63,B6&. 63,B026, 63,B0, 62 5 5 5 5 5 5 5 5 9VB3(50 *1' %71B&20 %71B$ %71B% /('B$ /('B% /('B& /('B' ,2B&21B ,2B&21B ,2B&21B ,2B&21B ,2B&21B ,2B&21B ,2B&21B ,2B&21B ,2B&21B ,2B&21B ,2B&21B ,2B&21B *1' 5 5 5 5 5 5 5 5 5 +HDGHU +HDGHU 9 H[W H[W H[W H[W H[W H[W H[W H[W H[W H[W *1' *1' *1' *1' *1' *1' *1' *1' *1' *1' *1'B9,3 9VB$ 9VB$ 9VB$ 9VB% 9VB% 9VB% 9VB% 9VB% 9VB% 9VB% 9VB% 9VB% 9VB% 9VB% 9VB% 9VB% 96B% 9VB3HU &3 5 5 =' %=9& & & *1' ' ' % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % 5 3% 3% 3% 3% 3% 3% 3% 3% 3& 3& 3& 3& 3& 3& 3& 3& 5 5 5 =' %=9& 5 *1' *1' & & 3$7, 0B&& 86$57B5 ; 86$57B7 ; 86$57B& ; ([WB ([WB ([WB ([WB ([WB ([WB ([WB ([WB ([WB ([WB 15HVHW 86$57B&; 86$57B7; 86$57B5; /,1B8$57B7; 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STM8 motherboard - USB Interface application schematic STEVAL-VNH5019A 2 Revision history Revision history Table 2. Document revision history Date Revision Changes 22-Jul-2013 1 Initial release. 06-Sep-2013 2 Updated Section 1.2: STM8 motherboard 16-Sep-2013 3 Updated disclaimer. DocID025030 Rev 3 11/12 11 STEVAL-VNH5019A Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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