PHILIPS 74ALVT162823DL

INTEGRATED CIRCUITS
74ALVT162823
18-bit bus-interface D-type flip-flop
with reset and enable
with 30Ω termination resistors (3-State)
Product specification
IC24 Data Handbook
1998 Aug 27
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30Ω termination resistors (3-State)
FEATURES
74ALVT162823
DESCRIPTION
• Two sets of high speed parallel registers with positive
The 74ALVT162823 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
edge-triggered D-type flip-flops
• 5V I/O Compatible
• Ideal where high speed, light loading, or increased fan-in are
The 74ALVT162823 has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
required with MOS microprocessors
• Live insertion/extraction permitted
• Power-up 3-State
• Power-up Reset
• Output capability: +12mA/–12mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 74ALVT162823 is designed with 30Ω series resistance in both
the pull-up and pull-down output structures. This design reduces line
noise in applications such as memory address drivers, clock drivers,
and bus receivers/transmitters.
and 200 V per Machine Model
• Bus hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
• Outputs include series resistance of 30Ω making external
termination resistors unnecessary
QUICK REFERENCE DATA
SYMBOL
TYPICAL
CONDITIONS
Tamb = 25°C; GND = 0V
PARAMETER
UNIT
2.5V
3.3V
4.2
3.4
3.0
2.8
ns
tPLH
tPHL
Propagation delay
nCP to nQx
CL = 50pF
CIN
Input capacitance
VI = 0V or VCC
3
3
pF
COUT
Output capacitance
VI/O = 0V or 3.0V
9
9
pF
ICCZ
Total supply current
Outputs disabled
40
70
µA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40°C to +85°C
74ALVT162823 DL
AV162823 DL
SOT371–1
56-Pin Plastic TSSOP Type II
–40°C to +85°C
74ALVT162823 DGG
AV162823 DGG
SOT364–1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
2, 27
1OE, 2OE
Output enable input (active-Low)
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
1D0-1D8
2D0-2D8
Data inputs
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
1Q0-1Q8
2Q0-2Q8
Data outputs
56, 29
1CP, 2CP
Clock pulse input (active rising edge)
55, 30
1CE, 2CE
Clock enable input (active-Low)
Master reset input (active-Low)
1, 28
1MR, 2MR
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
VCC
Positive supply voltage
1998 Aug 27
2
853-2114 19927
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30Ω termination resistors (3-State)
PIN CONFIGURATION
74ALVT162823
LOGIC SYMBOL (IEEE/IEC)
1MR
1
56
1CP
1OE
2
55
1CE
1Q0
3
54
1D0
GND
4
53
GND
1Q1
5
52
1Q2
6
VCC
7
1Q3
1OE
2
EN1
1MR
1
R2
1CE
55
G3
1CP
56
1D1
2OE
27
EN5
51
1D2
2MR
28
R6
50
VCC
2CE
30
G7
8
49
1D3
2CP
29
1Q4
9
48
1D4
3
10
47
1D5
1D0
54
1Q5
1Q0
1D1
52
5
1Q1
1D2
51
6
1Q2
1D3
49
8
1Q3
1D4
48
9
1Q4
1D5
47
10
1Q5
1D6
45
12
1Q6
1D7
44
13
1Q7
1D8
43
14
1Q8
15
2Q0
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
11
GND
46
12
1D6
45
13
1D7
44
14
1D8
43
15
2D0
42
16
2D1
41
17
2D2
40
18
GND
39
19
2D3
38
2Q4
20
37
2D4
2Q5
21
36
2D5
VCC
22
35
VCC
2Q6
23
34
2D6
2Q7
24
33
2D7
GND
25
32
GND
2Q8
26
31
2D8
2OE
27
30
2CE
2MR
28
29
2CP
7C8
1, 2 ∇
4D
42
2D0
2Q3
3C4
5, 6 ∇
8D
2D1
41
16
2Q1
2D2
40
17
2Q2
2D3
38
19
2Q3
2D4
37
20
2Q4
2D5
36
21
2Q5
2D6
34
23
2Q6
2D7
33
24
2Q7
2D8
31
25
2Q8
SH00015
SH00014
LOGIC DIAGRAM
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nCP
nD
R
CP
nD
R
Q
CP
nD
R
Q
CP
Q
CP
nD
nD
R
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
Q
nMR
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
n = 1 or 2
SH00016
1998 Aug 27
3
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30Ω termination resistors (3-State)
74ALVT162823
FUNCTION TABLE
INPUTS
OUTPUTS
nOE
nMR
nCE
nCP
nDx
nQ0 – nQ8
L
L
X
X
X
L
L
H
L
↑
h
H
L
H
L
↑
l
L
L
H
H
↑
X
NC
H =
h =
L =
l =
NC=
X =
Z =
↑ =
↑ =
OPERATING MODE
Clear
Load and read data
Hold
H
X
X
X
X
Z
High voltage level
High voltage level one set-up time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low to High clock transition
Not a Low-to-High clock transition
SCHEMATIC OF EACH OUTPUT
High impedance
BUS HOLD CIRCUIT
VCC
VCC
VCC
Data Input
27Ω
To internal circuit
OUTPUT
27Ω
SW00007
SW00044
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL
VCC
PARAMETER
IIK
DC input diode current
VI
DC input voltage3
IOK
DC output diode current
VOUT
IOUT
O
CONDITIONS
DC supply voltage
DC output voltage3
DC output current
VI < 0
RATING
UNIT
-0.5 to +4.6
V
-50
mA
-0.5 to +7.0
V
VO < 0
-50
mA
Output in Off or High state
-0.5 to +7.0
V
Output in Low state
128
Output in High state
-64
mA
Tstg
Storage temperature range
-65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
1998 Aug 27
4
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30Ω termination resistors (3-State)
74ALVT162823
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
2.5V RANGE LIMITS
PARAMETER
DC supply voltage
3.3V RANGE LIMITS
UNIT
MIN
MAX
MIN
MAX
2.3
2.7
3.0
3.6
V
0
5.5
0
5.5
V
VI
Input voltage
VIH
High-level input voltage
VIL
Input voltage
0.7
0.8
V
IOH
High-level output current
–8
–12
mA
IOL
Low-level output current
12
12
mA
10
ns/V
+85
°C
1.7
∆t/∆v
Input transition rise or fall rate; Outputs enabled
Tamb
Operating free-air temperature range
2.0
V
10
–40
+85
–40
DC ELECTRICAL CHARACTERISTICS (3.3V 0.3V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
VIK
Input clamp voltage
VCC = 3.0V; IIK = –18mA
VOH
High-level output voltage
VCC = 3.0V; IOH = –12mA
VOL
output
Low-level out
ut voltage
0V; IOL = 12mA
VCC = 3
3.0V;
VRST
Power-up output low
voltage6
VCC = 0 or 3.6V; VI = 5.5V
Input leakage current
IHOLD
Off current
Bus Hold current
D inputs7
–0.85
–1.2
2.3
05
0.5
Control pins
ins
VCC = 3.6V; VI = 5.5V
Data pins4
VCC = 3.6V; VI = VCC
IOFF
MAX
VCC = 3.6V; IO = 1mA; VI = VCC or GND
VCC = 3.6V; VI = VCC or GND
II
2.0
TYP1
V
V
08
0.8
V
0.55
V
0.1
±1
µA
0.1
10
0.1
10
0.5
1
VCC = 3.6V; VI = 0
0.1
-5
VCC = 0V; VI or VO = 0 to 4.5V
0.1
±100
VCC = 3V; VI = 0.8V
UNIT
75
130
VCC = 3V; VI = 2.0V
–75
–140
VCC = 0V to 3.6V; VCC = 3.6V
±500
µA
µA
µA
Current into an output in the
High state when VO > VCC
VO = 5.5V; VCC = 3.0V
10
125
µA
Power up/down 3-State output
current3
VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC
OE/OE = Don’t care
1
±100
µA
IOZH
3-State output High current
VCC = 3.6V; VO = 3.0V; VI = VIL or VIH
0.5
5
µA
IOZL
3-State output Low current
VCC = 3.6V; VO = 0.5V; VI = VIL or VIH
0.5
–5
µA
VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0
0.05
0.1
VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0
3.9
5.5
VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05
0.06
0.1
VCC = 3V to 3.6V; One input at VCC–0.6V,
Other inputs at VCC or GND
0.04
0.4
IEX
IPU/PD
ICCH
ICCL
Quiescent supply current
ICCZ
∆ICC
Additional supply current per
input pin2
mA
mA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND
3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a
transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only.
4. Unused pins at VCC or GND.
5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground.
6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Aug 27
5
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30Ω termination resistors (3-State)
74ALVT162823
AC CHARACTERISTICS (3.3V 0.3V RANGE)
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
Tamb = –40°C
to +85°C
VCC = +3.3V ±0.3V
WAVEFORM
MIN
TYP
UNIT
MAX
fMAX
Maximum clock frequency
1
MHz
tPLH
tPHL
Propagation delay
nCP to nQx
1
1.8
1.8
3.0
2.8
4.7
4.0
ns
tPHL
Propagation delay
nMR to nQx
2
1.8
2.8
4.0
ns
tPZH
tPZL
Output enable time
to High and Low level
4
5
1.9
1.6
3.5
2.6
5.7
3.8
ns
tPHZ
tPLZ
Output disable time
from High and Low level
4
5
1.9
1.5
3.4
2.5
5.2
3.8
ns
AC SETUP REQUIREMENTS (3.3V 0.3V RANGE)
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Tamb = -40 to +85oC
VCC = +3.3V ±0.3V
MIN
TYP
UNIT
ts(H)
ts(L)
Setup time, High or Low
nDx to nCP
3
1.0
1.2
0.6
0.7
ns
th(H)
th(L)
Hold time, High or Low
nDx to nCP
3
0.1
0.1
–0.8
–0.6
ns
tw(H)
tw(L)
nCP pulse width
High or Low
1
1.5
2.5
0.7
1.7
ns
ts(H)
ts(L)
Setup time, High or Low
nCE to nCP
3
1.0
0.5
0.2
–0.5
ns
th(H)
th(L)
Hold time, High or Low
nCE to nCP
3
1.0
1.0
0.5
–0.1
ns
tw(L)
nMR pulse width, Low
2
2.0
1.5
ns
trec
Recovery time
nMR to nCP
2
2.0
1.4
ns
1998 Aug 27
6
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30Ω termination resistors (3-State)
74ALVT162823
DC ELECTRICAL CHARACTERISTICS (2.5V 0.2V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
TYP1
MAX
–0.85
–1.2
UNIT
VIK
Input clamp voltage
VCC = 2.3V; IIK = –18mA
VOH
output
High-level out
ut voltage
3V; IOH = –8mA
VCC = 2
2.3V;
VOL
Low-level output voltage
VCC = 2.3V; IOL = 12mA
0.3
0.5
VCC = 2.7V; IO = 1mA; VI = VCC or GND
0.2
0.55
V
VCC = 2.7V; VI = GND
0.1
±1
µA
0.1
10
0.1
10
0.5
1
VRST
Power-up output low
voltage7
Control pins
ins
VCC = 2.7V; VI = 5.5V
II
Input leakage current
17
1.7
VCC = 3.6V; VI = 5.5V
Data pins4
VCC = 3.6V; VI = VCC
25
2.5
V
V
V
µA
VCC = 3.6V; VI = 0
0.1
-5
Off current
VCC = 0V; VI or VO = 0 to 4.5V
0.1
±100
Bus Hold current
VCC = 2.5V; VI = 0.7V
100
µA
D inputs6
VCC = 2.5V; VI = 1.7V
–70
µA
Current into an output in the
High state when VO > VCC
VO = 5.5V; VCC = 2.5V
10
125
µA
Power up/down 3-State output
current3
VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC;
OE/OE = Don’t care
1
±100
µA
IOZH
3-State output High current
VCC = 2.7V; VO = 2.3V; VI = VIL or VIH
0.5
5
µA
IOZL
3-State output Low current
VCC = 2.7V; VO = 0.5V; VI = VIL or VIH
0.5
–5
µA
VCC = 2.7V; Outputs High, VI = GND or VCC, IO = 0
0.04
0.1
VCC = 2.7V; Outputs Low, VI = GND or VCC, IO = 0
2.7
4.5
VCC = 2.7V; Outputs Disabled; VI = GND or VCC, IO = 05
0.04
0.1
VCC = 2.3V to 2.7V; One input at VCC–0.6V,
Other inputs at VCC or GND
0.04
0.4
IOFF
IHOLD
IEX
IPU/PD
ICCH
ICCL
Quiescent supply current
ICCZ
∆ICC
Additional supply current per
input pin2
µA
mA
mA
NOTES:
1. All typical values are at VCC = 2.5V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND
3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 2.5V ± 0.2V a
transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only.
4. Unused pins at VCC or GND.
5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground.
6. Not guaranteed.
7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
1998 Aug 27
7
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30Ω termination resistors (3-State)
74ALVT162823
AC CHARACTERISTICS (2.5V 0.2V RANGE)
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
Tamb = –40°C
to +85°C
VCC = +2.5V ±0.2V
WAVEFORM
MIN
TYP
UNIT
MAX
fMAX
Maximum clock frequency
1
MHz
tPLH
tPHL
Propagation delay
nCP to nQx
1
2.5
2.0
4.2
3.4
6.3
5.0
ns
tPHL
Propagation delay
nMR to nQx
2
2.0
3.4
4.6
ns
tPZH
tPZL
Output enable time
to High and Low level
4
5
3.0
2.0
4.8
3.2
7.6
5.2
ns
tPHZ
tPLZ
Output disable time
from High and Low level
4
5
2.5
2.0
4.4
3.3
6.7
5.2
ns
AC SETUP REQUIREMENTS (2.5V 0.2V RANGE)
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Tamb = -40 to +85oC
VCC = +2.5V ±0.2V
MIN
TYP
UNIT
ts(H)
ts(L)
Setup time, High or Low
nDx to nCP
3
1.0
2.0
0.6
1.4
ns
th(H)
th(L)
Hold time, High or Low
nDx to nCP
3
0.1
0.1
–1.5
–0.6
ns
tw(H)
tw(L)
nCP pulse width
High or Low
1
2.0
3.0
0.8
2.1
ns
ts(H)
ts(L)
Setup time, High or Low
nCE to nCP
3
1.0
0.5
0.2
–0.2
ns
th(H)
th(L)
Hold time, High or Low
nCE to nCP
3
1.0
1.0
0.2
–0.1
ns
tw(L)
nMR pulse width, Low
2
2.5
1.6
ns
trec
Recovery time
nMR to nCP
2
2.3
1.7
ns
1998 Aug 27
8
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30Ω termination resistors (3-State)
74ALVT162823
AC WAVEFORMS
For all waveforms, VM = 1.5V or VCC/2 whichever is less
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX
nCP
VM
VM
VM
VM
0V
tPZH
0V
tw
3.0V or VCC
whichever
is less
nOE
3.0V or VCC
whichever
is less
tPLH
tPHZ
VOH
VOH–0.3V
tPHL
VOH
nQn
VM
VM
nQx
VM
0V
0V
SH00020
SH00017
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
VM
nMR
3.0V or VCC
whichever
is less
3.0V or VCC
whichever
is less
VM
nOE
tREC
tPZL
3.0V or VCC
whichever
is less
VM
nCP
nQx
0V
tPHL
SH00021
Waveform 2. Master Reset Pulse WIdth, Master Reset to
Output Delay and Master Reset to Clock Recovery Time
VM
VM
3.0V or VCC
whichever
is less
VM
0V
nCP
th(H)
VM
ts(L)
th(L)
VM
3.0V or VCC
whichever
is less
0V
SH00019
Waveform 3. Data Setup and Hold Times
1998 Aug 27
VOL +0.3V
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
0V
SH00018
ts(H)
VM
3.0V or VCC
whichever
is less
VOL
VM
VM
tPLZ
VOH
nQn
nDx,
nCE
VM
0V
0V
tw
VM
9
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30Ω termination resistors (3-State)
74ALVT162823
TEST CIRCUIT AND WAVEFORM
6V or
VCC x 2
VCC
VIN
VOUT
PULSE
GENERATOR
RL
GND
tW
90%
OPEN
VM
NEGATIVE
PULSE
10%
0V
tTHL (tF)
CL
tTLH (tR)
tTLH (tR)
RL
tTHL (tF)
90%
POSITIVE
PULSE
Test Circuit for 3-State Outputs
VM
GND
tPLZ/tPZL
6V or VCC x 2
tPLH/tPHL
open
10%
0V
VM = 1.5V or VCC / 2, whichever is less
Input Pulse Definition
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
VM
tW
SWITCH
tPHZ/tPZH
AMP (V)
90%
10%
SWITCH POSITION
TEST
AMP (V)
VM
10%
D.U.T.
RT
90%
74ALVT16
RT = Termination resistance should be equal to ZOUT of
pulse generators.
Amplitude
Rep. Rate
tW
tR
3.0V or VCC
whichever
is less
≤10MHz
500ns
≤2.5ns
tF
≤2.5ns
SW00162
1998 Aug 27
10
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and
enable with 30Ω termination resistors (3-State)
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
1998 Aug 27
11
74ALVT162823
SOT371-1
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and
enable with 30Ω termination resistors (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
1998 Aug 27
12
74ALVT162823
SOT364-1
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and
enable with 30Ω termination resistors (3-State)
NOTES
1998 Aug 27
13
74ALVT162823
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and
enable with 30Ω termination resistors (3-State)
74ALVT162823
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
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14
Date of release: 05-96
9397-750-03577