INTEGRATED CIRCUITS DATA SHEET TDA9885; TDA9886 I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators Product specification Supersedes data of 2002 Mar 05 2003 Oct 02 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 APPLICATIONS 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 VIF amplifier Tuner AGC and VIF-AGC VIF-AGC detector FPLL detector VCO and divider AFC and digital acquisition help Video demodulator and amplifier Sound carrier trap SIF amplifier SIF-AGC detector Single reference QSS mixer AM demodulator FM demodulator and acquisition help Audio amplifier and mute time constant Internal voltage stabilizer I2C-bus transceiver and module address 9 I2C-BUS CONTROL 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 9.2.3 9.2.4 Read format Slave address Data byte Write format Subaddress Data byte for switching mode Data byte for adjust mode Data byte for data mode 2003 Oct 02 10 LIMITING VALUES 11 THERMAL CHARACTERISTICS 12 CHARACTERISTICS 13 TEST AND APPLICATION INFORMATION 14 PACKAGE OUTLINES 15 SOLDERING 15.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 15.2 15.3 15.4 15.5 2 TDA9885; TDA9886 16 DATA SHEET STATUS 17 DEFINITIONS 18 DISCLAIMERS 19 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 1 TDA9885; TDA9886 FEATURES • 5 V supply voltage • Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier, AC-coupled • Multistandard true synchronous demodulation with active carrier regeneration: very linear demodulation, good intermodulation figures, reduced harmonics, and excellent pulse response • SIF-AGC for gain controlled SIF amplifier, single reference QSS mixer able to operate in high performance single reference QSS mode and in intercarrier mode, switchable via I2C-bus • Gated phase detector for L and L-accent standard • Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free, frequencies switchable for all negative and positive modulated standards via I2C-bus • AM demodulator without extra reference circuit • Alignment-free selective FM-PLL demodulator with high linearity and low noise • Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75, and 58.75 MHz • Four selectable I2C-bus addresses • I2C-bus control for all functions • 4 MHz reference frequency input: signal from Phase-Locked Loop (PLL) tuning system or operating as crystal oscillator • I2C-bus transceiver with pin programmable Module Address (MAD). • VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals 2 GENERAL DESCRIPTION The TDA9885 is an alignment-free multistandard (PAL and NTSC) vision and sound IF signal PLL demodulator for negative modulation only and FM processing. • External AGC setting via pin OP1 • Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter, AFC bits readable via I2C-bus • TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL demodulator for positive and negative modulation, including sound AM and FM processing. • Fully integrated sound carrier trap for 4.5, 5.5, 6.0, and 6.5 MHz, controlled by FM-PLL oscillator 3 • Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode, PLL controlled 4 APPLICATIONS • TV, VTR, PC, and STB applications. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA9885T/V3 SO24 TDA9885TS/V3 SSOP24 TDA9885HN/V3 HVQFN32 TDA9886T/V4 SO24 TDA9886TS/V4 SSOP24 TDA9886HN/V4 HVQFN32 2003 Oct 02 DESCRIPTION plastic small outline package; 24 leads; body width 7.5 mm VERSION SOT137-1 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 × 5 × 0.85 mm SOT617-3 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 × 5 × 0.85 mm SOT617-3 3 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 5 TDA9885; TDA9886 QUICK REFERENCE DATA SYMBOL PARAMETER VP supply voltage IP supply current CONDITIONS notes 1 and 2 MIN. TYP. MAX. UNIT 4.5 5.0 5.5 V 52 63 70 mA Video part Vi(VIF)(rms) VIF input voltage sensitivity (RMS value) −1 dB video at output − 60 100 µV GVIF(cr) VIF gain control range see Fig.7 60 66 − dB fVIF vision carrier operating frequencies see Table 14 − 33.4 − MHz − 33.9 − MHz − 38.0 − MHz − 38.9 − MHz − 45.75 − MHz − 58.75 − MHz − ±2.3 − MHz normal mode 1.7 2.0 2.3 V trap bypass mode 0.95 1.10 1.25 V B/G standard − − 5 % L standard − − 7 % ∆fVIF VIF frequency window of digital acquisition help related to fVIF; see Fig.10 Vo(v)(p-p) video signal output voltage (peak-to-peak value) see Fig.5 Gdif differential gain “CCIR 330”; note 3 ϕdif differential phase “CCIR 330” − 2 4 deg Bv(−1dB) −1 dB video bandwidth trap bypass mode; AC load; CL < 20 pF; RL > 1 kΩ 5 6 − MHz Bv(−3dB)(trap) −3 dB video bandwidth including sound carrier trap note 4 ftrap = 4.5 MHz 3.95 4.05 − MHz ftrap = 5.5 MHz 4.90 5.00 − MHz ftrap = 6.0 MHz 5.40 5.50 − MHz 5.50 5.95 − MHz trap attenuation at first sound carrier M/N standard 30 36 − dB B/G standard 30 36 − dB S/NW weighted signal-to-noise ratio weighted in accordance with 56 “CCIR 567”; see Fig.11; note 5 59 − dB PSRRCVBS power supply ripple rejection at pin CVBS fripple = 70 Hz; video signal; grey level; positive and negative modulation; see Fig.6 20 25 − dB AFCstps AFC control steepness definition: ∆IAFC/∆fVIF 0.85 1.05 1.25 µA/kHz ftrap = 6.5 MHz αSC1 2003 Oct 02 4 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL PARAMETER CONDITIONS TDA9885; TDA9886 MIN. TYP. MAX. UNIT Audio part Vo(AF)(rms) AF output voltage (RMS value) 27 kHz FM deviation; 50 µs de-emphasis 430 540 650 mV THD total harmonic distortion of audio signal FM: 27 kHz FM deviation; 50 µs de-emphasis − 0.15 0.50 % AM: m = 54 % − 0.5 1.0 % BAF(−3dB) −3 dB AF bandwidth without de-emphasis; dependent on FM-PLL filter 80 100 − kHz S/NW(AF) weighted signal-to-noise ratio of audio signal FM: 27 kHz FM deviation; 50 µs de-emphasis; vision carrier unmodulated 52 56 − dB AM: m = 54 % 45 50 − dB αAM(sup) AM suppression of FM demodulator 50 µs de-emphasis; AM: f = 1 kHz and m = 54 %; referenced to 27 kHz FM deviation 40 46 − dB PSRRAUD power supply ripple rejection on pin AUD fripple = 70 Hz; see Fig.6 for AM 20 26 − dB for FM 14 20 − dB QSS mode; SC1; SC2 off 90 140 180 mV L standard; without modulation 90 140 180 mV intercarrier mode; PC/SC1 = 20 dB; SC2 off; note 6 − 75 − mV Vo(intc)(rms) IF intercarrier output level (RMS value) Reference frequency fref reference signal frequency note 7 − 4 − MHz Vref(rms) reference signal voltage (RMS value) operation as input terminal 80 − 400 mV Notes 1. Values of video and sound parameters can be decreased at VP = 4.5 V. 2. For applications without I2C-bus, the time constant (R × C) at the supply must be >1.2 µs (e.g. 1 Ω and 2.2 µF). 3. Condition: luminance range (5 steps) from 0 % to 100 %. 4. AC load: CL < 20 pF and RL > 1 kΩ. The sound carrier frequencies (depending on the TV standard) are attenuated by the integrated sound carrier traps (see Figs 13 to 18; H (s) is the absolute value of transfer function). 5. S/NW is the ratio of the black-to-white amplitude to the black level noise voltage (RMS value measured on pin CVBS). B = 5 MHz weighted in accordance with “CCIR 567”. 2003 Oct 02 5 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 6. The intercarrier output signal at pin SIOMAD can be calculated by the following formula taking into account the internal video signal with 1.1 V (p-p) as a reference: 1 r V o(intc)(rms) = 1.1 × ----------- × 10 V 2 2 V i(SC) 1 and r = ------ × -------------- ( dB ) + 6 dB ± 3 dB V i(PC) 20 where: V i ( SC ) 1 ----------- is the correction term for RMS value, --------------- ( dB ) is the sound-to-picture carrier ratio at pins VIF1 and VIF2 V i ( PC ) 2 2 in dB, 6 dB is the correction term of internal circuitry and ±3 dB is the tolerance of video output and intercarrier output Vo(intc)(rms). 7. Pin REF is able to operate as a 1-pin crystal oscillator input as well as an external reference signal input, e.g. from the tuning system. 2003 Oct 02 6 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... TAGC VAGC (1) VPLL REF AFC 14 (15) 16 (17) 19 (21) 15 (16) 21 (23) CBL VIF-AGC DIGITAL VCO CONTROL RC VCO AFC DETECTOR SOUND CARRIER TRAPS 4.5 to 6.5 MHz VIF-PLL (18) 17 video output: 2 V (p-p) [1.1 V (p-p) without trap] TDA9885 TDA9886 7 SIF2 24 (27) SIF1 23 (26) SINGLE REFERENCE QSS MIXER INTERCARRIER MIXER AND AM DEMODULATOR CVBS AUDIO PROCESSING AND SWITCHES (7) 8 AUD (3) 5 DEEM de-emphasis network MAD (4) 6 SUPPLY SIF-AGC OUTPUT PORTS audio output NARROW-BAND FM-PLL DEMODULATOR I 2C-BUS TRANSCEIVER Philips Semiconductors TOP I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 1 (30) BLOCK DIAGRAM VIF1 external reference signal or 4 MHz crystal 9 (8) TUNER AGC 2 (31) 6 VIF-PLL filter CAGC(neg) VIF2 handbook, full pagewidth 2003 Oct 02 CVAGC(pos) AFD CAF CAGC 18 (20) VP AGND n.c. 3 (1) 22 (24) 11 (10) OP1 OP2 SCL 10 (9) 7 (5) 12 (11) 4 (2) SDA DGND SIOMAD FMPLL (1) Not connected for TDA9885. Pin numbers for TDA9885HN and TDA9886HN in parenthesis. Fig.1 Block diagram. FM-PLL filter Product specification sound intercarrier output and MAD select MHC108 TDA9885; TDA9886 20 (22) (6, 12, 13, 14, 17, 19, 25, 28, 29, 32) 13 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 7 TDA9885; TDA9886 PINNING PIN SYMBOL DESCRIPTION TDA9885T TDA9886T TDA9885HN TDA9886HN TDA9885TS TDA9886TS VIF1 1 1 30 30 VIF differential input 1 VIF2 2 2 31 31 VIF differential input 2 n.c. − − 32 32 not connected OP1 3 3 1 1 output port 1; open-collector FMPLL 4 4 2 2 FM-PLL for loop filter DEEM 5 5 3 3 de-emphasis output for capacitor AFD 6 6 4 4 AF decoupling input for capacitor DGND 7 7 5 5 digital ground n.c. − − 6 6 not connected AUD 8 8 7 7 audio output TOP 9 9 8 8 tuner AGC TakeOver Point (TOP) for resistor adjustment SDA 10 10 9 9 I2C-bus data input and output SCL 11 11 10 10 I2C-bus clock input SIOMAD 12 12 11 11 sound intercarrier output and MAD select with resistor n.c. − − 12 12 not connected n.c. 13 13 13 13 not connected n.c. − − 14 14 not connected TAGC 14 14 15 15 tuner AGC output REF 15 15 16 16 4 MHz crystal or reference signal input VAGC − 16 − 17 VIF-AGC for capacitor n.c. 16 − 17 − not connected CVBS 17 17 18 18 composite video output n.c. − − 19 19 not connected AGND 18 18 20 20 analog ground VPLL 19 19 21 21 VIF-PLL for loop filter VP 20 20 22 22 supply voltage AFC 21 21 23 23 AFC output OP2 22 22 24 24 output port 2; open-collector n.c. − − 25 25 not connected SIF1 23 23 26 26 SIF differential input 1 and MAD select with resistor SIF2 24 24 27 27 SIF differential input 2 and MAD select with resistor n.c. − − 28 28 not connected n.c. − − 29 29 not connected 2003 Oct 02 8 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators handbook, halfpage TDA9885; TDA9886 handbook, halfpage VIF1 1 24 SIF2 VIF1 1 24 SIF2 VIF2 2 23 SIF1 VIF2 2 23 SIF1 OP1 3 22 OP2 OP1 3 22 OP2 FMPLL 4 21 AFC FMPLL 4 21 AFC DEEM 5 20 VP DEEM 5 20 VP DGND 7 19 VPLL TDA9885T TDA9886T 18 AGND DGND 7 19 VPLL TDA9885TS TDA9886TS 18 AGND AUD 8 17 CVBS AUD 8 17 CVBS TOP 9 16 VAGC (1) TOP 9 16 VAGC (1) SDA 10 15 REF SDA 10 15 REF SCL 11 14 TAGC SCL 11 14 TAGC AFD 6 SIOMAD 12 AFD 6 13 n.c. SIOMAD 12 MHC109 MHC110 (1) Not connected for TDA9885T. (1) Not connected for TDA9885TS. TOP 8 17 VAGC(1) AUD 7 18 CVBS n.c. 6 DGND 5 AFD 4 DEEM 3 FMPLL 2 22 VP 23 AFC OP1 1 24 OP2 19 n.c. 20 AGND n.c. 25 21 VPLL SIF1 26 SIF2 27 n.c. 28 n.c. 29 VIF1 30 n.c. 32 TDA9885HN TDA9886HN VIF2 31 terminal 1 index area Fig.3 Pin configuration for SSOP24. 16 REF 15 TAGC 14 n.c. 13 n.c. 12 n.c. 11 SIOMAD SDA 9 10 SCL Fig.2 Pin configuration for SO24. handbook, halfpage MHC111 Bottom view. (1) Not connected for TDA9885HN. Fig.4 Pin configuration for HVQFN32. 2003 Oct 02 13 n.c. 9 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 8 8.3 FUNCTIONAL DESCRIPTION • VIF amplifier For negative modulation, the sync level voltage is stored at an integrated capacitor by means of a fast peak detector. This voltage is compared with a reference voltage (nominal sync level) by a comparator which charges or discharges the integrated AGC capacitor for the generation of the required VIF gain. The time constants for decreasing or increasing the gain are nearly equal and the total AGC reaction time is fast to cope with ‘aeroplane fluttering’. • Tuner AGC and VIF-AGC • VIF-AGC detector • Frequency Phase-Locked Loop (FPLL) detector • VCO and divider • AFC and digital acquisition help • Video demodulator and amplifier • Sound carrier trap For positive modulation, the white peak level voltage is compared with a reference voltage (nominal white level) by a comparator which charges (fast) or discharges (slow) the external AGC capacitor directly for the generation of the required VIF gain. The need of a very long time constant for VIF gain increase is because the peak white level may appear only once in a field. In order to reduce this time constant, an additional level detector increases the discharging current of the AGC capacitor (fast mode) in the event of a decreasing VIF amplitude step controlled by the detected actual black level voltage. The threshold level for fast mode AGC is typically −6 dB video amplitude. The fast mode state is also transferred to the SIF-AGC detector for speed-up. In case of missing peak white pulses, the VIF gain increase is limited to typically +3 dB by comparing the detected actual black level voltage with a corresponding reference voltage. • SIF amplifier • SIF-AGC detector • Single reference QSS mixer • AM demodulator • FM demodulator and acquisition help • Audio amplifier and mute time constant • Internal voltage stabilizer • I2C-bus transceiver and MAD (module address). VIF amplifier The VIF amplifier consists of three AC-coupled differential stages. Gain control is performed by emitter degeneration. The total gain control range is typically 66 dB. The differential input impedance is typically 2 kΩ in parallel with 3 pF. 8.2 8.4 Tuner AGC and VIF-AGC FPLL detector The VIF amplifier output signal is fed into a frequency detector and into a phase detector via a limiting amplifier for removing the video AM. This block adapts the voltages, generated at the VIF-AGC and SIF-AGC detectors, to the internal signal processing at the VIF and SIF amplifiers and performs the tuner AGC control current generation. The onset of the tuner AGC control current generation can be set either via the I2C-bus (see Table 13) or optionally by a potentiometer at pin TOP (in case that the I2C-bus information cannot be stored, related to the device). The presence of a potentiometer is automatically detected and the I2C-bus setting is disabled. During acquisition the frequency detector produces a current proportional to the frequency difference between the VIF and the VCO signals. After frequency lock-in the phase detector produces a current proportional to the phase difference between the VIF and the VCO signals. The currents from the frequency and phase detectors are charged into the loop filter which controls the VIF VCO and locks it to the frequency and phase of the VIF carrier. Furthermore, derived from the AGC detector voltage, a comparator is used to test if the corresponding VIF input voltage is higher than 200 µV. This information can be read out via the I2C-bus (bit VIFLEV = 1). 2003 Oct 02 VIF-AGC detector Gain control is performed by sync level detection (negative modulation) or peak white detection (positive modulation). Figure 1 shows the simplified block diagram of the device which comprises the following functional blocks: 8.1 TDA9885; TDA9886 For a positive modulated VIF signal, the charging currents are gated by the composite sync in order to avoid signal distortion in case of overmodulation. The gating depth is switchable via the I2C-bus. 10 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 8.5 8.7 VCO and divider The demodulator output signal is fed into the video preamplifier via a level shift stage with integrated low-pass filter to achieve carrier harmonics attenuation. The oscillator frequency is divided-by-two to provide two differential square wave signals with exactly 90 degrees phase difference, independent of the frequency, for use in the FPLL detectors, the video demodulator and the intercarrier mixer. The output signal of the preamplifier is fed to the VIF-AGC detector (see Section 8.3) and in the sound trap mode also fed internally to the integrated sound carrier trap (see Section 8.8). The differential trap output signal is converted and amplified by the following postamplifier. The video output level at pin CVBS is 2 V (p-p). AFC and digital acquisition help Each relaxation oscillator of the VIF-PLL and FM-PLL demodulator has a wide frequency range. To prevent false locking of the PLLs and with respect to the catching range, the digital acquisition help provides an individual control, until the frequency of the VCO is within the preselected standard dependent lock-in window of the PLL. In the bypass mode the output signal of the preamplifier is fed directly through the postamplifier to pin CVBS. The output video level is 1.1 V (p-p) for using an external sound trap with 10 % overall loss. Noise clipping is provided in both cases. The in-window and out-window control at the FM-PLL is additionally used to mute the audio stage (if auto mute is selected via the I2C-bus). 8.8 Sound carrier trap The sound carrier trap consists of a reference filter, a phase detector and the sound trap itself. The working principle of the digital acquisition help is as follows. The PLL VCO output is connected to a down counter which has a predefined start value (standard dependent). The VCO frequency clocks the down counter for a fixed gate time. Thereafter, the down counter stop value is analysed. In case the stop value is higher (lower) than the expected value range, the VCO frequency is lower (higher) than the wanted lock-in window frequency range. A positive (negative) control current is injected into the PLL loop filter and consequently the VCO frequency is increased (decreased) and a new counting cycle starts. A sound carrier reference signal is fed into the reference low-pass filter and is shifted by nominal 90 degrees. The phase detector compares the original reference signal with the signal shifted by the reference filter and produces a DC voltage by charging or discharging an integrated capacitor with a current proportional to the phase difference between both signals, respectively to the frequency error of the integrated filters. The DC voltage controls the frequency position of the reference filter and the sound trap. So the accurate frequency position for the different standards is set by the sound carrier reference signal. The gate time as well as the control logic of the acquisition help circuit is dependent on the precision of the reference signal at pin REF. Operation as a crystal oscillator is possible as well as connecting this input via a serial capacitor to an external reference frequency, e.g. the tuning system oscillator. The sound trap itself is constructed of three separate traps to realize sufficient suppression of the first and second sound carriers. 8.9 The AFC signal is derived from the corresponding down counter stop value after a counting cycle. The last four bits are latched and can be read out via the I2C-bus (see Table 7). Also the digital-to-analog converted value is given as current at pin AFC. 2003 Oct 02 Video demodulator and amplifier The video demodulator is realized by a multiplier which is designed for low distortion and large bandwidth. The VIF signal is multiplied with the ‘in phase’ signal of the VIF-PLL VCO. The VCO of the VIF-FPLL operates as an integrated low radiation relaxation oscillator at double the picture carrier frequency. The control voltage, required to tune the VCO to double the picture carrier frequency, is generated at the loop filter by the frequency phase detector. The possible frequency range is 50 to 140 MHz (typical value). 8.6 TDA9885; TDA9886 SIF amplifier The SIF amplifier consists of three AC-coupled differential stages. Gain control is performed by emitter degeneration. The total gain control range is typically 66 dB. The differential input impedance is typically 2 kΩ in parallel with 3 pF. 11 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 8.10 8.12 SIF-AGC detector AM demodulator The amplitude modulated SIF amplifier output signal is fed both to a two-stage limiting amplifier that removes the AM and to a linear multiplier. The result of the multiplication of the SIF signal with the limiter output signal is AM demodulation (passive synchronous demodulator). The demodulator output signal is fed via a low-pass filter that attenuates the carrier harmonics and via the input amplifier of the SIF-AGC detector to the audio amplifier. SIF gain control is performed by the detection of the DC component of the AM demodulator output signal. This DC signal corresponds directly to the SIF voltage at the output of the SIF amplifier so that a constant SIF signal is supplied to the AM demodulator and to the single reference QSS mixer. By switching the gain of the input amplifier of the SIF-AGC detector via the I2C-bus, the internal SIF level for FM sound is 5.5 dB lower than for AM sound. This is to adapt the SIF-AGC characteristic to the VIF-AGC characteristic. The adaption is ideal for a picture-to-sound FM carrier ratio of 13 dB. 8.13 FM demodulator and acquisition help The narrow-band FM-PLL detector consists of: • Gain controlled FM amplifier and AGC detector • Narrow-band PLL. Via a comparator, the integrated AGC capacitor is charged or discharged for the generation of the required SIF gain. Due to AM sound, the AGC reaction time is slow (fc < 20 Hz for the closed AGC loop). For reducing this AM sound time constant in the event of a decreasing IF amplitude step, the load current of the AGC capacitor is increased (fast mode) when the VIF-AGC detector (at positive modulation mode) operates in the fast mode too. An additional circuit (threshold approximately 7 dB) ensures a very fast gain reduction for a large increasing IF amplitude step. 8.11 TDA9885; TDA9886 The intercarrier signal from the intercarrier mixer is fed to the input of an AC-coupled gain controlled amplifier with two stages. The gain controlled output signal is fed to the phase detector of the narrow-band FM-PLL (FM demodulator). For good selectivity and robustness against disturbance caused by the video signal, a high linearity of the gain controlled FM amplifier and of the phase detector as well as a constant signal level are required. The gain control is done by means of an ‘in phase’ demodulator for the FM carrier (from the output of the FM amplifier). The demodulation output is fed into a comparator for charging or discharging the integrated AGC capacitor. This leads to a mean value AGC loop to control the gain of the FM amplifier. Single reference QSS mixer With the present system a high performance Hi-Fi stereo sound processing can be achieved. For a simplified application without a SIF SAW filter, the single reference QSS mixer can be switched to the intercarrier mode via the I2C-bus. The FM demodulator is realized as a narrow-band PLL with an external loop filter, which provides the necessary selectivity (bandwidth approximately 100 kHz). To achieve good selectivity, a linear phase detector and a constant input level are required. The gain controlled intercarrier signal from the FM amplifier is fed to the phase detector. The phase detector controls via the loop filter the integrated low radiation relaxation oscillator. The designed frequency range is from 4 to 7 MHz. The single reference QSS mixer generates the 2nd FM TV sound intercarrier signal. It is realized by a linear multiplier which multiplies the SIF amplifier output signal and the VIF-PLL VCO signal (90 degrees output) which is locked to the picture carrier. In this way the QSS mixer operates as a quadrature mixer in the intercarrier mode and provides suppression of the low frequency video signals. The VCO within the FM-PLL is phase-locked to the incoming 2nd SIF signal, which is frequency modulated. As well as this, the VCO control voltage is superimposed by the AF voltage. Therefore, the VCO tracks with the FM of the 2nd SIF signal. So, the AF voltage is present at the loop filter and is typically 5 mV (RMS) for 27 kHz FM deviation. This AF signal is fed via a buffer to the audio amplifier. The QSS mixer output signal is fed internally via a high-pass and low-pass combination to the FM demodulator as well as via an operational amplifier to the intercarrier output pin SIOMAD. The correct locking of the PLL is supported by the digital acquisition help circuit (see Section 8.6). 2003 Oct 02 12 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 8.14 8.15 Audio amplifier and mute time constant Internal voltage stabilizer The band gap circuit internally generates a voltage of approximately 2.4 V, independent of supply voltage and temperature. A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.55 V which is used as an internal reference voltage. The audio amplifier consists of two parts: • AF preamplifier • AF output amplifier. The AF preamplifier used for FM sound is an operational amplifier with internal feedback, high gain and high common mode rejection. The AF voltage from the PLL demodulator is 5 mV (RMS) for a frequency deviation of 27 kHz and is amplified by 30 dB. By the use of a DC operating point control circuit (with external capacitor CAF), the AF preamplifier is decoupled from the PLL DC voltage. The low-pass characteristic of the amplifier reduces the harmonics of the sound intercarrier signal at the AF output terminal. 8.16 I2C-bus transceiver and module address The device can be controlled via the 2-wire I2C-bus by a microcontroller. Two wires carry serial data (SDA) and serial clock (SCL) information between the devices connected to the I2C-bus. The device has an I2C-bus slave transceiver with auto-increment. The circuit operates up to clock frequencies of 400 kHz. For FM sound a switchable de-emphasis network (with external capacitor) is implemented between the preamplifier and the output amplifier. A slave address is sent from the master to the slave receiver. To avoid conflicts in a real application with other devices providing similar or complementing functions, there are four possible slave addresses available. These Module Addresses (MADs) can be selected by connecting resistors on pin SIOMAD and/or pins SIF1 and SIF2 (see Fig.23). Pin SIOMAD relates with bit A0 and pins SIF1 and SIF2 relate with bit A3. The slave addresses of this device are given in Table 1. The AF output amplifier provides the required AF output level by a rail-to-rail output stage. A preceding stage makes use of an input selector for switching between FM sound, AM sound and mute state. The gain can be switched between 10 dB (normal) and 4 dB (reduced). Switching to the mute state is controlled automatically, dependent on the digital acquisition help in case the VCO of the FM-PLL is not in the required frequency window. This is done by a time constant: fast for switching to the mute state and slow (typically 40 ms) for switching to the no-mute state. The power-on preset value is dependent on the use of pin SIOMAD and can be chosen for 45.75 MHz NTSC as default (pin SIOMAD left open-circuit) or 58.75 MHz NTSC (resistor on pin SIOMAD). In this way the device can be used without the I2C-bus as an NTSC only device. All switching functions are controlled via the I2C-bus: Remark: In case of using the device without the I2C-bus, then the rise time of the supply voltage after switching on power must be longer than 1.2 µs. • AM sound, FM sound and forced mute • Auto mute enable or disable • De-emphasis off or on with 50 or 75 µs • Audio gain normal or reduced. 2003 Oct 02 TDA9885; TDA9886 13 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators Table 1 TDA9885; TDA9886 Slave address detection SELECTABLE ADDRESS BIT RESISTOR ON PIN SLAVE ADDRESS A3 A0 SIF1 AND SIF2 SIOMAD MAD1 0 1 no no MAD2 0 0 no yes MAD3 1 1 yes no MAD4 1 0 yes yes I2C-BUS CONTROL 9 9.1 Read format Table 2 I2C-bus read format (slave transmits data) S BYTE 1 A6 A5 A4 A3 A2 slave address Table 3 A A1 A0 BYTE 2 R/W D7 D6 D5 1 D4 D3 AN D2 D1 D0 data Explanation of Table 2 SYMBOL FUNCTION S START condition, generated by the master Slave address see Table 4 R/W = 1 read command, generated by the master A acknowledge bit, generated by the slave Data 8-bit data word, transmitted by the slave (see Table 5) AN acknowledge-not bit, generated by the master P STOP condition, generated by the master The master generates an acknowledge when it has received the dataword READ. The master next generates an acknowledge, then slave begins transmitting the dataword READ, and so on until the master generates an acknowledge-not bit and transmits a STOP condition. 2003 Oct 02 14 P Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 9.1.1 TDA9885; TDA9886 SLAVE ADDRESS The first module address MAD1 is the standard address (see Table 1). Table 4 Slave addresses; notes 1 and 2 SLAVE ADDRESS NAME BIT VALUE (HEX) A6 A5 A4 A3 A2 A1 A0 43 1 0 0 0 0 1 1 MAD2 42 1 0 0 0 0 1 0 MAD3 4B 1 0 0 1 0 1 1 MAD4 4A 1 0 0 1 0 1 0 MAD1 Notes 1. For MAD activation via external resistor: see Table 1 and Fig.23. 2. For applications without I2C-bus: see Tables 17 and 18. 9.1.2 DATA BYTE Table 5 Data read register (status register) MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 AFCWIN VIFLEV CARRDET AFC4 AFC3 AFC2 AFC1 PONR Table 6 Description of status register bits BIT VALUE AFCWIN DESCRIPTION AFC window 1 0 VIFLEV VCO in ±1.6 MHz AFC window; note 1 VCO out of ±1.6 MHz AFC window VIF input level 1 high level; VIF input voltage ≥200 µV (typically) 0 low level CARRDET FM carrier detection 1 detection 0 no detection AFC[4:1] Automatic frequency control see Table 7 PONR Power-on reset 1 after Power-on reset or after supply breakdown 0 after a successful reading of the status register Note 1. If no IF input is applied, then bit AFCWIN = 1 due to the fact that the VCO is forced to the AFC window border for fast lock-in behaviour. 2003 Oct 02 15 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators Table 7 TDA9885; TDA9886 Automatic frequency control bits; note 1 BIT AFC4 AFC3 AFC2 fVIF AFC1 0 1 1 1 ≤ (f0 − 187.5 kHz) 0 1 1 0 f0 − 162.5 kHz 0 1 0 1 f0 − 137.5 kHz 0 1 0 0 f0 − 112.5 kHz 0 0 1 1 f0 − 87.5 kHz 0 0 1 0 f0 − 62.5 kHz 0 0 0 1 f0 − 37.5 kHz 0 0 0 0 f0 − 12.5 kHz 1 1 1 1 f0 + 12.5 kHz 1 1 1 0 f0 + 37.5 kHz 1 1 0 1 f0 + 62.5 kHz 1 1 0 0 f0 + 87.5 kHz 1 0 1 1 f0 + 112.5 kHz 1 0 1 0 f0 + 137.5 kHz 1 0 0 1 f0 + 162.5 kHz 1 0 0 0 ≥ (f0 + 187.5 kHz) Note 1. f0 is the nominal frequency of fVIF. 9.2 Write format Table 8 I2C-bus write format (slave receives data); note 1 S BYTE 1 A BYTE 2 A BYTE 3 A BYTE n A6 to A0 R/W A7 to A0 bits 7 to 0 bits 7 to 0 slave address 0 subaddress data 1 data n Note 1. The auto-increment of the subaddress stops if the subaddress is 3. Table 9 Explanation of Table 8 SYMBOL FUNCTION S START condition, generated by the master Slave address see Table 4 R/W = 0 write command, generated by the master A acknowledge bit, generated by the slave Subaddress (SAD) see Table 10 Data 1, data n 8-bit data words, transmitted by the master (see Tables 11, 12 and 14) P STOP condition 2003 Oct 02 16 A P Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 9.2.1 TDA9885; TDA9886 SUBADDRESS If more than one data byte is transmitted, then auto-increment is performed: starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of Table 10. Table 10 Definition of the subaddress (second byte after slave address); note 1 MSB REGISTER LSB A7(2) A6(3) A5(3) A4(3) A3(3) A2(3) A1 A0 0 X X X X X 0 0 SAD for adjust mode 0 X X X X X 0 1 SAD for data mode 0 X X X X X 1 0 SAD for switching mode Notes 1. X = don’t care. 2. Bit A7 = 1 is not allowed. 3. Bits A6 to A2 will be ignored by the internal hardware. 9.2.2 DATA BYTE FOR SWITCHING MODE Table 11 Bit description of SAD register for switching mode (SAD = 00) BIT VALUE B7 Output port 2 for SAW switching or monitoring 1 high-impedance, disabled or HIGH 0 low-impedance, active or LOW B6 Output port 1 for SAW switching or external input 1 high-impedance, disabled or HIGH 0 low-impedance, active or LOW B5 Forced audio mute 1 on 0 off B4 and B3 TV standard modulation 00 positive AM TV; note 1 01 not used 10 negative FM TV 11 not used 1 QSS mode 0 intercarrier mode B2 Carrier mode B1 2003 Oct 02 DESCRIPTION Auto mute of FM AF output 1 active 0 inactive 17 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators BIT VALUE B0 DESCRIPTION Video mode (sound trap) 1 sound trap bypass 0 sound trap active Note 1. For positive AM TV choose 6.5 MHz for the second SIF. 9.2.3 DATA BYTE FOR ADJUST MODE Table 12 Bit description of SAD register for adjust mode (SAD = 01) BIT VALUE C7 Audio gain 1 −6 dB 0 0 dB C6 De-emphasis time constant 1 50 µs 0 75 µs C5 C4 to C0 DESCRIPTION De-emphasis 1 on 0 off Tuner takeover point adjustment see Table 13 2003 Oct 02 18 TDA9885; TDA9886 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 Table 13 Tuner takeover point adjustment bits BIT TOP ADJUSTMENT (dB) C4 C3 C2 C1 C0 1 1 1 1 1 +15 1 1 1 1 0 +14 1 1 1 0 1 +13 1 1 1 0 0 +12 1 1 0 1 1 +11 1 1 0 1 0 +10 1 1 0 0 1 +9 1 1 0 0 0 +8 1 0 1 1 1 +7 1 0 1 1 0 +6 1 0 1 0 1 +5 1 0 1 0 0 +4 1 0 0 1 1 +3 1 0 0 1 0 +2 1 0 0 0 1 +1 1 0 0 0 0 0(1) 0 1 1 1 1 −1 0 1 1 1 0 −2 0 1 1 0 1 −3 0 1 1 0 0 −4 0 1 0 1 1 −5 0 1 0 1 0 −6 0 1 0 0 1 −7 0 1 0 0 0 −8 0 0 1 1 1 −9 0 0 1 1 0 −10 0 0 1 0 1 −11 0 0 1 0 0 −12 0 0 0 1 1 −13 0 0 0 1 0 −14 0 0 0 0 1 −15 0 0 0 0 0 −16 Note 1. 0 dB is equal to 17 mV (RMS). 2003 Oct 02 19 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 9.2.4 TDA9885; TDA9886 DATA BYTE FOR DATA MODE Table 14 Bit description of SAD register for data mode (SAD = 10) BIT VALUE E7 DESCRIPTION VIF-AGC and port features dependent on bit E5; see Table 15 E6 L standard PLL gating 1 gating in case of 36 % positive modulation 0 gating in case of 0 % positive modulation E5 VIF, SIF and tuner minimum gain dependent on bit E7; see Table 15 E4 to E2 Vision intermediate frequency selection see Table 16 E1 and E0 Sound intercarrier frequency selection (sound 2nd IF) 00 fFM = 4.5 MHz 01 fFM = 5.5 MHz 10 fFM = 6.0 MHz 11 fFM = 6.5 MHz; note 1 Note 1. For positive modulation choose 6.5 MHz. Table 15 Options in extended TV mode; bit B3 = 0 of SAD 00 register BIT E7 = 0 BIT E7 = 1 FUNCTION BIT E5 = 0 BIT E5 = 1 BIT E5 = 0 BIT E5 = 1 Pin OP1 port function port function port function VIF-AGC external input(1) Pin OP2 port function port function VIF-AGC output(1) port function Gain normal gain minimum gain normal gain external gain Note 1. The corresponding port function has to be disabled (set to ‘high-impedance’); see Table 11 and Chapter 12, Table of Characteristics, note 12. 2003 Oct 02 20 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 Table 16 TV standard selection for VIF VIDEO IF SELECT BITS fVIF (MHz) E4 E3 E2 0 0 0 58.75(1) 0 0 1 45.75(1) 0 1 0 38.9 0 1 1 38.0 1 0 0 33.9 1 0 1 33.4 1 1 0 not applicable 1 1 1 not applicable Note 1. Pin SIOMAD can be used for the selection of the different NTSC standards without I2C-bus. With a resistor on pin SIOMAD, fVIF = 58.75 MHz; without a resistor on pin SIOMAD, fVIF = 45.75 MHz (NTSC-M). Table 17 Data setting after power-on reset (default setting with a resistor on pin SIOMAD) MSB LSB REGISTER D7 D6 D5 D4 D3 D2 D1 D0 Switching mode 1 1 0 1 0 1 1 0 Adjust mode 0 0 1 1 0 0 0 0 Data mode 0 0 0 0 0 0 0 0 Table 18 Data setting after power-on reset (default setting without a resistor on pin SIOMAD) MSB LSB REGISTER D7 D6 D5 D4 D3 D2 D1 D0 Switching mode 1 1 0 1 0 1 1 0 Adjust mode 0 0 1 1 0 0 0 0 Data mode 0 0 0 0 0 1 0 0 2003 Oct 02 21 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER VP supply voltage Vn voltage on CONDITIONS MIN. − MAX. UNIT 5.5 V pins VIF1, VIF2, SIF1, SIF2, OP1, OP2, VP, and FMPLL 0 VP V pin TAGC 0 8.8 V tsc short-circuit time to ground or VP − 10 s Tstg storage temperature −25 +150 °C Tamb ambient temperature TDA9885T (SO24), TDA9885TS (SSOP24), TDA9886T (SO24) and TDA9886TS (SSOP24) −20 +70 °C TDA9885HN (HVQFN32) and TDA9886HN (HVQFN32) −20 +85 °C note 1 −400 +400 V note 2 −4000 +3500 V Ves electrostatic discharge voltage on all pins Notes 1. Machine model in accordance with SNW-FQ-302B: class C, discharging a 200 pF capacitor via a 0.75 µH series inductance. 2. Human body model in accordance with SNW-FQ-302A: class 2, discharging a 100 pF capacitor via a 1.5 kΩ series resistor. 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2003 Oct 02 PARAMETER CONDITIONS VALUE UNIT TDA9885T (SO24) 76 K/W TDA9885TS (SSOP24) 118 K/W TDA9885HN (HVQFN32) 40 K/W TDA9886T (SO24) 76 K/W TDA9886TS (SSOP24) 118 K/W TDA9886HN (HVQFN32) 40 K/W thermal resistance from junction to ambient in free air 22 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 12 CHARACTERISTICS VP = 5 V; Tamb = 25 °C; see Table 20 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with “CCIR line 17 and line 330” or “NTC-7 Composite” ; measurements taken in test circuit of Fig.23; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply (pin VP) VP supply voltage IP Ptot note 1 4.5 5.0 5.5 V supply current 52 63 70 mA total power dissipation − 305 385 mW POWER-ON RESET VP(start) supply voltage for start of reset decreasing supply voltage 2.5 3.0 3.5 V VP(stop) supply voltage for end of reset increasing supply voltage; I2C-bus transmission enable − − 4.4 V τP time constant (R × C) for network at pin VP for applications without I2C-bus 1.2 − − µs VIF amplifier (pins VIF1 and VIF2) Vi(VIF)(rms) VIF input voltage sensitivity (RMS value) −1 dB video at output − 60 100 µV Vi(max)(rms) maximum input voltage (RMS value) +1 dB video at output 150 190 − mV Vi(ovl)(rms) overload input voltage (RMS value) note 2 − − 440 mV ∆VIF(int) internal IF amplitude difference between picture and sound carrier within AGC range; ∆f = 5.5 MHz − 0.7 − dB GVIF(cr) VIF gain control range see Fig.7 60 66 − dB BVIF(−3dB)(ll) lower limit −3 dB VIF bandwidth − 15 − MHz BVIF(−3dB)(ul) upper limit −3 dB VIF bandwidth − 80 − MHz Ri(dif) differential input resistance note 3 − 2 − kΩ Ci(dif) differential input capacitance note 3 − 3 − pF VI DC input voltage − 1.93 − V FPLL and true synchronous video demodulator; note 4 fVCO(max) maximum oscillator frequency for carrier regeneration f = 2fPC 120 140 − MHz fVIF vision carrier operating frequencies see Table 14 − 33.4 − MHz − 33.9 − MHz − 38.0 − MHz − 38.9 − MHz − 45.75 − MHz − 58.75 − MHz 2003 Oct 02 23 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL PARAMETER ∆fVIF VIF frequency window of digital acquisition help TDA9885; TDA9886 CONDITIONS MIN. related to fVIF; see Fig.10 − − TYP. MAX. ±2.3 − UNIT MHz tacq acquisition time BL = 70 kHz; note 5 − 30 ms Vi(lock)(rms) input voltage sensitivity for PLL to be locked (RMS value) measured on pins VIF1 − and VIF2; maximum IF gain 30 70 µV Tcy(DAH) cycle time of digital acquisition help − 64 − µs KO(VIF) VIF VCO steepness definition: ∆fVIF/∆VVPLL − 20 − MHz/V KD(VIF) VIF phase detector steepness definition: ∆IVPLL/∆ϕVIF − 23 − µA/rad Video output 2 V (pin CVBS) NORMAL MODE (SOUND CARRIER TRAP ACTIVE) AND SOUND CARRIER ON Vo(v)(p-p) video output voltage (peak-to-peak value) see Fig.5 1.7 2.0 2.3 V ∆Vo video output voltage difference difference between L and B/G standard −12 − +12 % V/S ratio between video (black-to-white) and sync level 1.90 2.33 3.00 Vsync sync voltage level 1.0 1.2 1.4 V Vclip(u) upper video clipping voltage level VP − 1.1 VP − 1 − V Vclip(l) lower video clipping voltage level − 0.7 0.9 V Ro output resistance − − 30 Ω Ibias(int) internal DC bias current for emitter-follower 1.5 2.0 − mA Io(sink)(max) maximum AC and DC output sink current 1 − − mA Io(source)(max) maximum AC and DC output source current 3.9 − − mA ∆Vo(CVBS) deviation of CVBS output voltage 50 dB gain control − − 0.5 dB 30 dB gain control − − 0.1 dB note 3 ∆Vo(bl) black level tilt negative modulation − − 1 % ∆Vo(bl)(v) vertical black level tilt for worst case in L standard vision carrier modulated by test line (VITS) only − − 3 % Gdif differential gain “CCIR 330”; note 6 B/G standard − − 5 % L standard − − 7 % − 2 4 deg 59 − dB ϕdif differential phase “CCIR 330” S/NW weighted signal-to-noise ratio weighted in accordance 56 with “CCIR 567”; see Fig.11; note 7 2003 Oct 02 24 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL PARAMETER TDA9885; TDA9886 CONDITIONS MIN. TYP. MAX. UNIT S/NUW unweighted signal-to-noise ratio note 7 47 51 − dB αIM(blue) intermodulation attenuation at ‘blue’ f = 1.1 MHz 58 64 − dB f = 3.3 MHz 58 64 − dB f = 1.1 MHz 60 66 − dB f = 3.3 MHz 59 65 − dB αIM(yellow) intermodulation attenuation at ‘yellow’ see Fig.12; note 8 see Fig.12; note 8 ∆Vr(PC)(rms) residual picture carrier (RMS value) fundamental wave and harmonics − 2 5 mV ∆funw(p-p) robustness for unwanted frequency deviation of picture carrier (peak-to-peak value) 3 % residual carrier; 50 % serration pulses; L standard; note 3 − − 12 kHz ∆ϕ robustness for modulator imbalance 0 % residual carrier; 50 % serration pulses; L standard; L-gating = 0 %; note 3 − − 3 % αH suppression of video signal harmonics CL < 20 pF; RL > 1 kΩ; AC load; note 9a 35 40 − dB αspur suppression of spurious elements note 9b 40 − − dB PSRRCVBS power supply ripple rejection at pin CVBS fripple = 70 Hz; 20 video signal; grey level; positive and negative modulation; see Fig.6 25 − dB ftrap = 4.5 MHz; note 10 3.95 4.05 − MHz M/N STANDARD INCLUDING KOREA; see Fig 13 Bv(−3dB)(trap) −3 dB video bandwidth including sound carrier trap αSC1 attenuation at first sound carrier f = 4.5 MHz 30 36 − dB αSC1(60kHz) attenuation at first sound carrier fSC1 ± 60 kHz f = 4.5 MHz 21 27 − dB αSC2 attenuation at second sound carrier f = 4.724 MHz 21 27 − dB αSC2(60kHz) attenuation at second sound carrier fSC2 ± 60 kHz f = 4.724 MHz 15 21 − dB td(g)(cc) group delay at colour carrier frequency f = 3.58 MHz; see Fig.14 110 180 250 ns ftrap = 5.5 MHz; note 10 4.90 5.00 − MHz B/G STANDARD; see Fig.15 Bv(−3dB)(trap) −3 dB video bandwidth including sound carrier trap αSC1 attenuation at first sound carrier f = 5.5 MHz 30 36 − dB αSC1(60kHz) attenuation at first sound carrier fSC1 ± 60 kHz f = 5.5 MHz 24 30 − dB αSC2 attenuation at second sound carrier f = 5.742 MHz 21 27 − dB 2003 Oct 02 25 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL PARAMETER TDA9885; TDA9886 CONDITIONS MIN. TYP. MAX. UNIT αSC2(60kHz) attenuation at second sound carrier fSC2 ± 60 kHz f = 5.742 MHz 15 21 − dB td(g)(cc) group delay at colour carrier frequency f = 4.43 MHz; see Fig.16 110 180 250 ns ftrap = 6.0 MHz; note 10 5.40 5.50 − MHz I STANDARD; see Fig.17 Bv(−3dB)(trap) −3 dB video bandwidth including sound carrier trap αSC1 attenuation at first sound carrier f = 6.0 MHz 26 32 − dB αSC1(60kHz) attenuation at first sound carrier fSC1 ± 60 kHz f = 6.0 MHz 20 26 − dB αSC2 attenuation at second sound carrier f = 6.55 MHz 12 18 − dB αSC2(60kHz) attenuation at second sound carrier fSC2 ± 60 kHz f = 6.55 MHz 10 15 − dB td(g)(cc) group delay at colour carrier frequency f = 4.43 MHz − 90 160 ns 5.95 − MHz D/K STANDARD; see Fig.18 Bv(−3dB)(trap) −3 dB video bandwidth including sound carrier trap ftrap = 6.5 MHz; note 10 5.50 αSC1 attenuation at first sound carrier f = 6.5 MHz 26 32 − dB αSC1(60kHz) attenuation at first sound carrier fSC1 ± 60 kHz f = 6.5 MHz 20 26 − dB αSC2 attenuation at second sound carrier f = 6.742 MHz 18 24 − dB αSC2(60kHz) attenuation at second sound carrier fSC2 ± 60 kHz f = 6.742 MHz 13 18 − dB td(g)(cc) group delay at colour carrier frequency f = 4.28 MHz − 60 130 ns see Fig.5 0.95 1.10 1.25 V Video output 1.1 V (pin CVBS) TRAP BYPASS MODE AND SOUND CARRIER OFF; note 11 Vo(v)(p-p) video output voltage (peak-to-peak value) Vsync sync voltage level 1.35 1.5 1.6 V Vclip(u) upper video clipping voltage level 3.5 3.6 − V Vclip(l) lower video clipping voltage level − 0.9 1.0 V Bv(−1dB) −1 dB video bandwidth CL < 20 pF; RL > 1 kΩ; AC load 5 6 − MHz Bv(−3dB) −3 dB video bandwidth CL < 20 pF; RL > 1 kΩ; AC load 7 8 − MHz 2003 Oct 02 26 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL PARAMETER TDA9885; TDA9886 CONDITIONS MIN. TYP. MAX. UNIT 59 − dB 48 52 − dB negative modulation; 20 dB; note 13 − 4 − ms positive modulation; 20 dB; note 13 − 2.6 − ms negative modulation; 20 dB; note 13 − 3 − ms positive modulation; 20 dB; note 13 − 890 − ms L standard; fast mode − 2.6 − ms/dB L standard; normal mode; note 13 − 143 − ms/dB S/NW weighted signal-to-noise ratio weighted in accordance 56 with “CCIR 567”; see Fig.11; note 7 S/NUW unweighted signal-to-noise ratio note 7 AGC response time to an increasing VIF step VIF-AGC; note 12 tresp(inc) tresp(dec) AGC response time to a decreasing VIF step ∆Vi(VIF) VIF amplitude step for activating L standard AGC fast mode −2 −6 −10 dB VVAGC gain control voltage range see Fig.7 0.8 − 3.5 V CRstps control steepness definition: ∆GVIF/∆VVAGC; VVAGC = 2 to 3 V − −80 − dB/V Vth(VIF) threshold voltage for high level VIF input see Tables 5 and 6 120 200 320 µV PIN VAGC Ich(max) maximum charge current L standard − 100 − µA Ich(add) additional charge current L standard: in the event − of missing VITS pulses and no white video content 100 − nA Idch discharge current L standard; normal mode − 35 − nA L standard; fast mode − 1.8 − µA Tuner AGC (pin TAGC); see Figs 7 to 9 Vi(VIF)(start1)(rms) VIF input signal voltage for minimum starting point of tuner takeover at pins VIF1 and VIF2 (RMS value) ITAGC = 120 µA; − RTOP = 22 kΩ or no RTOP and −15 dB via I2C-bus (see Table 13) 2 5 mV Vi(VIF)(start2)(rms) VIF input signal voltage for maximum starting point of tuner takeover at pins VIF1 and VIF2 (RMS value) ITAGC = 120 µA; RTOP = 0 Ω or no RTOP and +15 dB via I2C-bus (see Table 13) 90 − mV 2003 Oct 02 27 45 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL PARAMETER TDA9885; TDA9886 CONDITIONS MIN. TYP. MAX. UNIT QVTOP tuner takeover point accuracy ITAGC = 120 µA; RTOP = 10 kΩ or no RTOP and 0 dB via I2C-bus (see Table 13) 7 17 43 mV ∆QVTOP/∆T takeover point variation with temperature ITAGC = 120 µA − 0.03 0.07 dB/K Vo permissible output voltage from external source − − 8.8 V Vsat saturation voltage ITAGC = 450 µA − − 0.5 V Isink sink current no tuner gain reduction; − VTAGC = 8.8 V − 0.75 µA maximum tuner gain reduction; VTAGC = 1 V 450 600 750 µA 3 5 8 dB ∆GIF IF slip by automatic gain control tuner gain current from 20 % to 80 % AFC circuit (pin AFC); see Fig.10; notes 14 and 15 Vsat(ul) upper limit saturation voltage VP − 0.6 VP − 0.3 − V Vsat(ll) lower limit saturation voltage − 0.3 0.6 V Io(source) output source current 160 200 240 µA Io(sink) output sink current 160 200 240 µA AFCstps AFC control steepness definition: ∆IAFC/∆fVIF 0.85 1.05 1.25 µA/kHz QfVIF(a) analog accuracy of AFC circuit IAFC = 0; fREF = 4 MHz −20 − +20 kHz QfVIF(d) digital accuracy of AFC circuit via I2C-bus IAFC = 0; fREF = 4 MHz; 1 digit = 25 kHz −20 − 1 digit − +20 kHz + 1 digit FM mode; −3 dB at intercarrier output pin SIOMAD − 30 70 µV AM mode; −3 dB at AF output pin AUD − 70 100 µV FM mode; +1 dB at intercarrier output pin SIOMAD 50 70 − mV AM mode; +1 dB at AF output pin AUD 80 140 − mV SIF amplifier (pins SIF1 and SIF2) Vi(SIF)(rms) Vi(max)(rms) SIF input voltage sensitivity (RMS value) maximum input voltage (RMS value) Vi(ovl)(rms) overload input voltage (RMS value) note 2 − − 320 mV GSIF(cr) SIF gain control range FM and AM mode; see Fig.9 60 66 − dB BSIF(−3dB)(ll) lower limit −3 dB SIF bandwidth − 15 − MHz BSIF(−3dB)(ul) upper limit −3 dB SIF bandwidth − 80 − MHz Ri(dif) differential input resistance note 3 − 2 − kΩ Ci(dif) differential input capacitance note 3 − 3 − pF VI DC input voltage − 1.93 − V 2003 Oct 02 28 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL PARAMETER TDA9885; TDA9886 CONDITIONS MIN. TYP. MAX. UNIT SIF-AGC detector tresp AGC response time to an increasing or decreasing SIF step of 20 dB FM or AM fast step increasing − 8 − ms decreasing − 25 − ms increasing − 80 − ms decreasing − 250 − ms QSS mode; SC1; SC2 off 90 140 180 mV L standard; without modulation 90 140 180 mV intercarrier mode; PC/SC1 = 20 dB; SC2 off; note 16 − 75 − mV 12 15 − MHz QSS mode − 2 5 mV intercarrier mode − 2 5 mV QSS mode − 2 5 mV intercarrier mode − 5 20 mV AM slow step Single reference QSS intercarrier mixer (pin SIOMAD) Vo(intc)(rms) IF intercarrier output level (RMS value) Bintc(−3dB)(ul) upper limit −3 dB intercarrier bandwidth ∆Vr(SC)(rms) residual sound carrier (RMS value) ∆Vr(PC)(rms) residual picture carrier (RMS value) fundamental wave and harmonics fundamental wave and harmonics αH suppression of video signal harmonics intercarrier mode; fvideo = 5 MHz 35 40 − dB Ro output resistance note 3 − − 30 Ω VO DC output voltage − 2 − V Ibias(int) internal DC bias current for emitter follower 0.90 1.15 − mA Io(sink)(max) maximum AC output sink current 0.6 0.8 − mA Io(source)(max) maximum AC output source current 0.6 0.8 − mA Io(source) DC output source current 0.75 0.93 1.20 mA 2003 Oct 02 MAD2 activated; note 17 29 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL PARAMETER TDA9885; TDA9886 CONDITIONS MIN. TYP. MAX. UNIT FM-PLL demodulator; notes 15 and 18 to 22 SOUND INTERCARRIER OUTPUT (PIN SIOMAD) VFM(rms) IF intercarrier level for gain controlled operation of FM-PLL (RMS value) VFM(lock)(rms) IF intercarrier level for lock-in of PLL (RMS value) VFM(det)(rms) IF intercarrier level for FM carrier detect (RMS value) fFM sound intercarrier operating FM frequencies 3.2 − 320 mV − − 2 mV see Table 6 − − 2.3 mV see Table 14 − 4.5 − MHz − 5.5 − MHz − 6.0 − MHz − 6.5 − MHz 25 kHz FM deviation; 75 µs de-emphasis 400 500 600 mV 27 kHz FM deviation; 50 µs de-emphasis 430 540 650 mV THD < 1.5 % 1.3 1.4 − V − 3 × 10−3 7 × 10−3 dB/K corresponding PC/SC ratio at input pins VIF1 and VIF2 is 7 to 47 dB AUDIO OUTPUT (PIN AUD) Vo(AF)(rms) AF output voltage (RMS value) Vo(AF)(cl)(rms) AF output clipping level (RMS value) ∆Vo(AF)/∆T AF output voltage variation with temperature THD total harmonic distortion ∆fAF frequency deviation − 0.15 0.50 % THD < 1.5 %; note 19 − − ±55 kHz −6 dB AF output via I2C-bus; note 19 − − ±110 kHz 100 − kHz 52 56 − dB black picture; see Fig.19 50 56 − dB BAF(−3dB) −3 dB AF bandwidth S/NW(AF) weighted signal-to-noise ratio of FM-PLL only; audio signal 27 kHz FM deviation; 50 µs de-emphasis without de-emphasis; 80 measured with FM-PLL filter of Fig.23 ∆Vr(SC)(rms) residual sound carrier (RMS value) fundamental wave and harmonics; without de-emphasis − − 2 mV αAM(sup) AM suppression of FM demodulator referenced to 27 kHz FM deviation; 50 µs de-emphasis; AM: f = 1 kHz; m = 54 % 40 46 − dB PSRRFM power supply ripple rejection fripple = 70 Hz; see Fig.6 14 20 − dB 2003 Oct 02 30 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL PARAMETER TDA9885; TDA9886 CONDITIONS MIN. TYP. MAX. UNIT FM-PLL FILTER (PIN FMPLL) Vloop DC loop voltage 1.5 − 3.3 V Io(source)(PD)(max) maximum phase detector output source current − 60 − µA Io(sink)(PD)(max) maximum phase detector output sink current − 60 − µA Io(source)(DAH) output source current of digital acquisition help − 55 − µA Io(sink)(DAH) output sink current of digital acquisition help − 55 − µA tW(DAH) pulse width of digital acquisition help current − 16 − µs Tcy(DAH) cycle time of digital acquisition help − 64 − µs KO(FM) VCO steepness definition: ∆fFM/∆VFMPLL − 3.3 − MHz/V KD(FM) phase detector steepness definition: ∆IFMPLL/∆ϕFM − 4 − µA/rad 50 µs de-emphasis; see Table 12 4.4 5.0 5.6 kΩ 75 µs de-emphasis; see Table 12 6.6 7.5 8.4 kΩ fAF = 400 Hz; VAUD = 500 mV − 170 − mV − 2.37 − V Audio amplifier DE-EMPHASIS NETWORK (PIN DEEM) Ro output resistance VAF(rms) audio signal (RMS value) VO DC output voltage AF DECOUPLING (PIN AFD) Vdec DC decoupling voltage dependent on fFM intercarrier frequency 1.5 − 3.3 V IL leakage current ∆VO(AUD) < ±50 mV − − ±25 nA Ich(max) maximum charge current 1.15 1.50 1.85 µA Idch(max) maximum discharge current 1.15 1.50 1.85 µA − − 300 Ω − 2.37 − V 10 − − kΩ AUDIO OUTPUT (PIN AUD) Ro output resistance VO(AUD) DC output voltage RL load resistance RL(DC) DC load resistance 100 − − kΩ CL load capacitance − − 1.5 nF BAF(−3dB)(ul) upper limit −3 dB AF bandwidth of audio amplifier 150 − − kHz BAF(−3dB)(ll) lower limit −3 dB AF bandwidth of audio amplifier note 20 − − 20 Hz αmute mute attenuation of AF signal via I2C-bus 70 75 − dB 2003 Oct 02 note 3 AC-coupled 31 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL ∆Vjump PARAMETER DC jump voltage for switching AF output to mute state or vice versa TDA9885; TDA9886 CONDITIONS MIN. TYP. MAX. UNIT − ±50 ±150 mV black picture 50 56 − dB white picture 45 51 − dB 6 kHz sine wave (black-to-white modulation) 40 46 − dB sound carrier subharmonics; f = 2.75 MHz ±3 kHz 35 40 − dB 40 − − dB activated by digital acquisition help or via I2C-bus mute FM operation; notes 21 and 23 INTERCARRIER AF PERFORMANCE; note 24 S/NW weighted signal-to-noise ratio PC/SC ratio is 21 to 27 dB at pins VIF1 and VIF2 SINGLE REFERENCE QSS AF PERFORMANCE; notes 25 and 26 S/NW(SC1) 2003 Oct 02 weighted signal-to-noise ratio for SC1 PC/SC1 ratio at pins VIF1 and VIF2; 27 kHz (54 % FM deviation); “CCIR 468” black picture 53 58 − dB white picture 50 53 − dB 6 kHz sine wave (black-to-white modulation) 44 48 − dB 250 kHz square wave 40 (black-to-white modulation) 45 − dB sound carrier subharmonics; f = 2.75 MHz ±3 kHz 45 51 − dB sound carrier subharmonics; f = 2.87 MHz ±3 kHz 46 52 − dB 32 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL S/NW(SC2) PARAMETER weighted signal-to-noise ratio for SC2 TDA9885; TDA9886 CONDITIONS PC/SC2 ratio at pins VIF1 and VIF2; 27 kHz (54 % FM deviation); “CCIR 468” MIN. 40 TYP. MAX. UNIT − − dB black picture 48 55 − dB white picture 46 51 − dB 6 kHz sine wave (black-to-white modulation) 42 46 − dB 250 kHz square wave 29 (black-to-white modulation) 34 − dB sound carrier subharmonics; f = 2.75 MHz ±3 kHz 44 50 − dB sound carrier subharmonics; f = 2.87 MHz ±3 kHz 45 51 − dB AM operation L STANDARD (PIN AUD); see Figs 20 and 21; note 27 Vo(AF)(rms) AF output voltage (RMS value) 54 % modulation 400 500 600 mV THD total harmonic distortion 54 % modulation − 0.5 1.0 % BAF(−3dB) −3 dB AF bandwidth 100 125 − kHz S/NW(AF) weighted signal-to-noise ratio of in accordance with audio signal “CCIR 468” 45 50 − dB VO(AUD) DC potential voltage − 2.37 − V PSRRAM power supply ripple rejection 20 26 − dB 2.3 2.6 2.9 V see Fig.6 Reference frequency input (pin REF) VI DC input voltage Ri input resistance note 3 − 5 − kΩ Rxtal resonance resistance of crystal operation as crystal oscillator − − 200 Ω Cx pull-up/down capacitance note 28 − − − pF fref reference signal frequency note 29 − 4 − MHz ∆fref tolerance of reference signal frequency note 15 − − ±0.1 % Vref(rms) reference signal voltage (RMS value) operation as input terminal 80 − 400 mV Ro(ref) output resistance of reference signal source − − 4.7 kΩ CK decoupling capacitance to operation as input external reference signal source terminal 22 100 − pF 2003 Oct 02 33 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators SYMBOL PARAMETER TDA9885; TDA9886 CONDITIONS MIN. TYP. MAX. UNIT I2C-bus transceiver (pins SDA and SCL); notes 30 and 31 0 − 400 kHz HIGH-level input voltage 3 − VCC V LOW-level input voltage −0.3 − +1.5 V IIH HIGH-level input current −10 − +10 µA IIL LOW-level input current −10 − +10 µA VOL LOW-level output voltage IOL = 3 mA − − 0.4 V Io(sink) output sink current VP = 0 V − − 10 µA Io(source) output source current VP = 0 V − − 10 µA IOL = 2 mA (sink current) − − 0.4 V fSCL SCL clock frequency VIH VIL Output ports (pins OP1 and OP2); note 32 VOL LOW-level output voltage VOH HIGH-level output voltage − − 6 V Io(sink) output sink current − − 2 mA Io(sink/source)(max) maximum output sink or source current − − 10 µA pin OP2 functions as VIF-AGC output Notes 1. Values of video and sound parameters can be decreased at VP = 4.5 V. 2. Level headroom for input level jumps during gain control setting. 3. This parameter is not tested during the production and is only given as application information for designing the receiver circuit. 4. Loop bandwidth BL = 70 kHz (damping factor d = 1.9; calculated with sync level within gain control range). Calculation of the VIF-PLL filter can be done by use of the following formula: 1 BL –3dB = ------- K O K D R , valid for d ≥ 1.2 2π 1 d = --- R K O K D C , 2 where: rad Hz µA KO is the VCO steepness -------- or 2π ------- ; KD is the phase detector steepness -------- ; V rad V R is the loop resistor; C is the loop capacitor; BL−3dB is the loop bandwidth for −3 dB; d is the damping factor. 5. Vi(VIF) = 10 mV (RMS); ∆f = 1 MHz (VCO frequency offset related to picture carrier frequency); white picture video modulation. 6. Condition: luminance range (5 steps) from 0 % to 100 %. 7. S/N is the ratio of black-to-white amplitude to the black level noise voltage (RMS value on pin CVBS). B = 5 MHz (B/G, I and D/K standard). Noise analyzer setting: 200 kHz high-pass and SC-trap switched on. 8. The intermodulation figures are defined for: V 0 at 4.4 MHz a) f = 1.1 MHz (referenced to black and white signal) as α IM = 20 log ------------------------------------- + 3.6 dB V 0 at 1.1 MHz V 0 at 4.4 MHz b) f = 3.3 MHz (referenced to colour carrier) as α IM = 20 log ------------------------------------- V 0 at 3.3 MHz 2003 Oct 02 34 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 9. Measurements taken with SAW filter M1963M (sound shelf: 20 dB); loop bandwidth BL = 70 kHz. a) Modulation Vestigial Side-Band (VSB); sound carrier off; fvideo > 0.5 MHz. b) Sound carrier on; fvideo = 10 kHz to 10 MHz. 10. AC load; CL < 20 pF and RL > 1 kΩ. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound carrier traps (see Figs 13 to 18; H (s) is the absolute value of transfer function). 11. The sound carrier trap can be bypassed by switching the I2C-bus. In this way the full composite video spectrum appears at pin CVBS. The amplitude is 1.1 V (p-p). 12. If selected by the I2C-bus, the VIF-AGC voltage can be monitored at pin OP2, and pin OP1 can be used as input. In this case, both pins cannot be used for the normal port function. 13. The response time is valid for a VIF input level range from 200 µV to 70 mV. 14. To match the AFC output signal to different tuning systems a current source output is provided. The test circuit is given in Fig.10. The AFC slope (voltage per frequency) can be changed by resistors R1 and R2. 15. The tolerance of the reference frequency determines the accuracy of the VIF-AFC, FM demodulator centre frequency and maximum FM deviation. 16. The intercarrier output signal at pin SIOMAD can be calculated by the following formula taking into account the internal video signal with 1.1 V (p-p) as a reference: 1 r V o(intc)(rms) = 1.1 × ----------- × 10 V 2 2 V i(SC) 1 and r = ------ × -------------- ( dB ) + 6 dB ± 3 dB 20 V i(PC) where: V i ( SC ) 1 ----------- is the correction term for RMS value, --------------- ( dB ) is the sound-to-picture carrier ratio at pins VIF1 and VIF2 V i ( PC ) 2 2 in dB, 6 dB is the correction term of internal circuitry and ±3 dB is the tolerance of video output and intercarrier output Vo(intc)(rms). 17. For normal operation (with the I2C-bus) no DC load at pin SIOMAD is allowed. The second module address (MAD2) will be activated by the application of a 2.2 kΩ resistor between pin SIOMAD and ground. If this MAD2 is activated, also the power-on set-up state activates a VIF frequency of 58.75 MHz. 18. SIF input level is 10 mV (RMS); VIF input level is 10 mV (RMS) unmodulated. 19. Measured with an FM deviation of 25 kHz and the typical AF output voltage of 500 mV (RMS). The AF output signal can be attenuated by 6 dB to 250 mV (RMS) via the I2C-bus. For handling a frequency deviation of more than 55 kHz, the AF output signal has to be reduced in order to avoid clipping (THD < 1.5 %). 20. The lower limit of the audio bandwidth depends on the value of the capacitor at pin AFD. A value of CAF = 470 nF leads to fAF(−3dB) ≈ 20 Hz and CAF = 220 nF leads to fAF(−3dB) ≈ 40 Hz. 21. For all S/N measurements the VIF modulator in use has to meet the following specifications: a) Incidental phase modulation for black-to-white jump less than 0.5 degrees. b) QSS AF performance, measured with the television demodulator AMF2 (audio output, weighted S/N ratio) better than 60 dB (at deviation 27 kHz) for 6 kHz sine wave black-to-white video modulation. c) Picture-to-sound carrier ratio PC/SC1 = 13 dB (transmitter). 2003 Oct 02 35 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 22. Calculation of the loop filter parameters can be done approximately using the following formulae: 1 KO KD f o = ------- --------------2π C P 1 ϑ = -----------------------------------2R K O K D C P 2 BL –3dB = f o ( 1.55 – ϑ ) The formulae are only valid under the following conditions: ϑ ≤ 1 and CS > 5CP where: rad Hz KO is the VCO steepness -------- or 2π ------- ; V V µA KD is the phase detector steepness -------- ; rad R is the loop resistor; CS is the series capacitor; CP is the parallel capacitor; fo is the natural frequency of PLL; BL−3dB is the loop bandwidth for −3 dB; ϑ is the damping factor. For examples, see Table 19. 23. The PC/SC ratio is calculated as the addition of TV transmitter PC/SC1 ratio and SAW filter PC/SC1 ratio. This PC/SC ratio is necessary to achieve the S/NW values as noted. A different PC/SC ratio will change these values. 24. Measurements taken with SAW filter G1984 (Siemens) for vision and sound IF (sound shelf: 14 dB). Picture-to-sound carrier ratio of transmitter PC/SC = 13 dB. Input level on pins VIF1 and VIF2 of Vi(SIF) = 10 mV (RMS) sync level, 27 kHz FM deviation for sound carrier, fAF = 400 Hz. Measurements in accordance with “CCIR 468”. De-emphasis is 50 µs. 25. The QSS signal output on pin SIOMAD is analysed by a test demodulator TDA9820. The S/N ratio of this device is more than 60 dB, related to a deviation of ±27 kHz, in accordance with “CCIR 468”. 26. Measurements taken with SAW filter K3953 for vision IF (suppressed sound carrier) and K9453 for sound IF (suppressed picture carrier). Input level Vi(SIF) = 10 mV (RMS), 27 kHz (54 % FM deviation). 27. Measurements taken with SAW filter K9453 (Siemens) for AM sound IF (suppressed picture carrier). 28. The value of Cx determines the accuracy of the resonance frequency of the crystal. It depends on the type of crystal used. 29. Pin REF is able to operate as a 1-pin crystal oscillator input as well as an external reference signal input, e.g. from the tuning system. 30. The SDA and SCL lines will not be pulled down if VCC is switched off. 31. The AC characteristics are in accordance with the I2C-bus specification for fast mode (maximum clock frequency is 400 kHz). Information about the I2C-bus can be found in the brochure “The I2C-bus and how to use it” (order number 9398 393 40011). 32. Port P1 and port P2 are open-collector outputs. 2003 Oct 02 36 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 Table 19 Examples to note 22 (FM-PLL filter) BL−3dB (kHz) CS (nF) CP (pF) R (kΩ) ϑ 100 10 390 5.6 0.5 160 10 150 9.1 0.5 Table 20 Input frequencies and carrier ratios DESCRIPTION VIF carrier SIF carrier Picture-to-sound carrier ratio 2003 Oct 02 SYMBOL B/G STANDARD M/N STANDARD L STANDARD L ACCENT STANDARD UNIT fPC 38.9 45.75 or 58.75 38.9 33.9 MHz fSC1 33.4 41.25 or 54.25 32.4 40.4 MHz fSC2 33.158 − − − MHz SC1 13 7 10 10 dB SC2 20 − − − dB 37 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 trap bypass mode handbook, full pagewidth normal mode 2.72 V 2.6 V 3.41 V 3.20 V zero carrier level white level 1.83 V 1.80 V black level 1.5 V 1.20 V sync level MHC115 Fig.5 Typical video signal levels on output pin CVBS (sound carrier off). handbook, full pagewidth VP (V) VP = 5 V 5 100 mV TDA9885 TDA9886 fripple = 70 Hz MHC114 t (s) Fig.6 Ripple rejection condition. 2003 Oct 02 38 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 MHC116 handbook, full pagewidth I TAGC VVAGC (µA) (V) 4 600 500 400 3 300 200 (1) 2 (2) (3) (4) 100 0 1 30 40 50 60 70 80 90 100 110 120 Vi(VIF) (dBµV) (1) VVAGC is VIF-AGC voltage and can only be measured at pin OP2 controlled by the I2C-bus (see Table 15). (2) ITAGC is tuner current in TV mode with RTOP = 22 kΩ or setting via I2C-bus at −15 dB. (3) ITAGC is tuner current in TV mode with RTOP = 10 kΩ or setting via I2C-bus at 0 dB. (4) ITAGC is tuner current in TV mode with RTOP = 0 kΩ or setting via I2C-bus at +15 dB. Fig.7 Typical VIF and tuner AGC characteristic. MHC117 MHB159 110 5 handbook, halfpage handbook, halfpage Vi(VIF) (dBµV) VSAGC (V) 100 4 90 3 (1) 80 (2) 2 70 60 0 4 8 12 16 1 20 24 RTOP (kΩ) 30 50 70 90 110 130 Vi(SIF) (dBµV) (1) FM mode. (2) AM mode. Fig.8 Typical tuner takeover point as a function of resistor RTOP. 2003 Oct 02 Fig.9 Typical SIF-AGC characteristic. 39 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 lock range without SAW filter handbook, full pagewidth AFC window IAFC 5 (µA) VAFC VP (V) −200 4 −100 TDA9885 21 TDA9886 (23) IAFC R1 22 kΩ VAFC 3 0 2 R2 22 kΩ +100 1 +200 0 36 37 38 40 38.9 38.71 39.09 41 f (MHz) MHC113 Pin numbers for TDA9885HN and TDA9886HN in parenthesis. Fig.10 Typical analog AFC characteristic. MHC112 3.2 dB handbook, halfpage 80 handbook, halfpage 10 dB S/N (dB) 13.2 dB 60 13.2 dB 21 dB 21 dB 40 SC CC BLUE PC SC CC PC YELLOW 20 0 30 MHA739 50 70 90 Vi(VIF) (dBµV) 110 SC is sound carrier, with respect to sync level. CC is chrominance carrier, with respect to sync level. PC is picture carrier, with respect to sync level. The sound carrier levels are take into account a sound shelf attenuation of 14 dB (SAW filter G1984M). Fig.11 Typical signal-to-noise ratio as a function of VIF input voltage. 2003 Oct 02 Fig.12 Input signal conditions. 40 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 MHC122 10 handbook, full pagewidth H (s) (dB) 0 −10 −20 −30 −40 minimum requirements 2 2.5 3 3.5 4 4.5 f (MHz) 5 Fig.13 Typical amplitude response for sound trap at M/N standard (including Korea). handbook, full pagewidth MHB167 400 group delay (ns) 300 200 ideal characteristic due to pre-correction in the transmitter 100 0 −100 minimum requirements 0 0.5 1 1.5 2 2.5 3 3.5 Overall delay is not shown, here the maximum ripple is specified. Fig.14 Typical group delay for sound trap at M/N standard. 2003 Oct 02 41 f (MHz) 4 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 MHB168 10 handbook, full pagewidth H (s) (dB) 0 −10 −20 −30 −40 minimum requirements 4 4.5 5 5.5 6 6.5 f (MHz) 7 Fig.15 Typical amplitude response for sound trap at B/G standard. MHB169 400 group delay (ns) handbook, full pagewidth 300 200 ideal characteristic due to pre-correction in the transmitter 100 0 −100 minimum requirements 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 f (MHz) 5 Overall delay is not shown, here the maximum ripple is specified. Fig.16 Typical group delay for sound trap at B/G standard. 2003 Oct 02 42 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 MHC123 handbook, full pagewidth 10 H (s) (dB) 0 −10 −20 −30 −40 minimum requirements 4 4.5 5 5.5 6 6.5 f (MHz) 7 Fig.17 Typical amplitude response for sound trap at I standard. MHB171 handbook, full pagewidth 10 H (s) (dB) 0 −10 −20 −30 −40 minimum requirements 4 4.5 5 5.5 6 6.5 f (MHz) 7 Fig.18 Typical amplitude response for sound trap at D/K standard. 2003 Oct 02 43 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 MHC118 10 handbook, full pagewidth S/NW (1) 0 (dB) −10 −20 −30 −40 (2) −50 (3) −60 −70 52 49 46 43 40 37 34 31 28 25 22 19 16 13 10 7 4 PC/SC ratio gain controlled operation of FM-PLL (1) Signal. (2) Noise at H-picture (CCIR weighted quasi peak). (3) Noise at black picture (CCIR weighted quasi peak). Conditions: PC/SC ratio measured at pins VIF1 and VIF2; via transformer; 27 kHz FM deviation; 50 µs de-emphasis. Fig.19 Audio signal-to-noise ratio as a function of picture-to-sound carrier ratio in intercarrier mode. 2003 Oct 02 44 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 MHC119 10 handbook, full pagewidth S/NW (1) 0 (dB) −10 −20 −30 −40 (2) −50 −60 −70 30 45 (1) Signal. (2) Noise. 60 75 90 Vi (dBµV) 105 Condition: m = 54 %. Fig.20 Typical audio signal-to-noise ratio as a function of input signal at AM standard. MHC120 1.5 handbook, full pagewidth THD (%) 1.0 0.5 0 10 −2 10 −1 1 10 fAF (kHz) CAGC = 2.2 µF; m = 54 %. Fig.21 Typical total harmonic distortion as a function of audio frequency at AM standard. 2003 Oct 02 45 102 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators handbook, full pagewidth TDA9885; TDA9886 MHC121 140 10 IF signals RMS value (V) antenna input (dBµV) video 2 V (p-p) 120 1 (1) 10−1 100 SAW insertion loss 20 dB IF slip 6 dB 10−2 (TOP) 80 tuning gain control range 70 dB VIF AGC 10−3 0.66 × 10−3 60 SAW insertion loss 20 dB 10−4 40 40 dB RF gain 10−5 0.66 × 10−5 20 10 VHF/UHF tuner VIF VIF amplifier, demodulator and video tuner SAW filter TDA9885, TDA9886 (1) Depends on TOP. Fig.22 Front-end level diagram. 2003 Oct 02 46 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 51 Ω 150 kΩ SIF2 24 (27) 1.5 nF 100 nF 150 Ω tuner AGC output 100 pF 4 MHz (1) R2 Cx 150 kΩ SIF1 23 (26) 22 kΩ OP2 220 nF VP AFC 22 (24) 21 (23) 20 (22) 470 nF VPLL 19 (21) AGND 18 (20) CVBS VAGC (3) REF TAGC 16 15 (16) 14 (15) 13 (6, 12, 13, 14, 17, 19, 25, 28, 29, 32) (7) 8 (8) 9 (9) 10 (10) 11 (11) 12 TDA9885 TDA9886 (30) 1 (31) 2 VIF1 47 VIF input VIF2 (1) 3 (2) 4 OP1 (3) 5 FMPLL (4) 6 DEEM (5) 7 AFD DGND n.c. 17 (18) AUD TOP SDA SIOMAD SCL 1:1 10 nF 5.6 kΩ 51 Ω 10 nF 470 nF 390 pF 22 kΩ MAD select R1 2.2 kΩ Philips Semiconductors 22 kΩ external reference CVBS output I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 1:1 R3 VIF-PLL filter (2) VP 13 TEST AND APPLICATION INFORMATION dth 2003 Oct 02 AFC output SIF input (1) FM-PLL filter audio output intercarrier output MHC124 Option R1 = 2.2 kΩ 1000 011 (R/W) 1000 010 (R/W) R2 = R3 = 150 kΩ 1001 011 (R/W) 1001 010 (R/W) (2) Different VIF loop filter in comparison with the application circuit due to different input characteristics (SAW filter or transformer). (3) Not connected for TDA9885. Fig.23 Test circuit. Product specification R1 not used R2 and R3 not used TDA9885; TDA9886 Pin numbers for TDA9885HN and TDA9886HN in parenthesis. (1) Optional for I2C-bus address selection. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1 2 BA277 4 5V BC847 100 kΩ 220 nF 10 nF 6.8 kΩ 12 kΩ 220 Ω 330 Ω 10 nF 3 6.8 kΩ SIF2 24 (27) 10 nF 1.5 nF 22 kΩ 5 SAW FILTER K9456 (3) 75 Ω BA277 10 µF BA277 tuner AGC SIF1 23 (26) OP2 (1) 22 (24) AFC 21 (23) VP 20 (22) 470 nF VPLL 19 (21) AGND 18 (20) CVBS 47 µF 100 pF VAGC (2) REF TAGC 48 16 15 (16) 14 (15) 13 (6, 12, 13, 14, 17, 19, 25, 28, 29, 32) (7) 8 (8) 9 (9) 10 (10) 11 (11) 12 5V TDA9885 TDA9886 22 kΩ (30) 1 VIF1 (31) 2 VIF2 (1) 3 (2) 4 OP1 (3) 5 (4) 6 FMPLL DEEM 10 nF 10 nF (5) 7 AFD DGND AUD TOP SDA 100 Ω IF input 1 51 Ω 2 5 SAW FILTER K3953 4 390 pF n.c. 17 (18) SCL SIOMAD Philips Semiconductors BC847C fref CVBS output 5V 220 kΩ I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators book, full pagewidth 2003 Oct 02 680 kΩ 100 Ω 470 nF 5.6 kΩ 3 (3) I 2C-bus AF output Fig.24 Application circuit. MHC125 Product specification Pin numbers for TDA9885HN and TDA9886HN in parenthesis. (1) If pin OP2 outputs VIF-AGC voltage, then pin OP1 can be used for SAW switching. (2) Not connected for TDA9885. (3) Optional measures to improve ESD performance within a TV-set application. intercarrier output TDA9885; TDA9886 positive supply I 2C-bus controller Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 14 PACKAGE OUTLINES SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 13 24 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 2003 Oct 02 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 49 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 0o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 2003 Oct 02 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 50 o Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-3 terminal 1 index area A A1 E c detail X C e1 e 1/2 e 9 y1 C v M C A B w M C b 16 y L 17 8 e e2 Eh 1/2 e 24 1 terminal 1 index area 32 25 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 5.1 4.9 3.75 3.45 5.1 4.9 3.75 3.45 0.5 3.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT617-3 --- MO-220 --- 2003 Oct 02 51 EUROPEAN PROJECTION ISSUE DATE 02-04-18 02-10-22 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators To overcome these problems the double-wave soldering method was specifically developed. 15 SOLDERING 15.1 Introduction to soldering surface mount packages If wave soldering is used the following conditions must be observed for optimal results: This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 TDA9885; TDA9886 – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. • below 220 °C (SnPb process) or below 245 °C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. – for all BGA and SSOP-T packages 15.4 – for packages with a thickness ≥ 2.5 mm Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2003 Oct 02 Manual soldering 52 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators 15.5 TDA9885; TDA9886 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA not suitable suitable(4) DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(5), SO, SOJ suitable REFLOW(2) suitable suitable suitable not recommended(5)(6) suitable SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable PMFP(8) not suitable LQFP, QFP, TQFP not suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Hot bar or manual soldering is suitable for PMFP packages. 2003 Oct 02 53 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 16 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17 DEFINITIONS 18 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Oct 02 54 Philips Semiconductors Product specification I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators TDA9885; TDA9886 19 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2003 Oct 02 55 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/02/pp56 Date of release: 2003 Oct 02 Document order number: 9397 750 11443