INTEGRATED CIRCUITS DATA SHEET TDA8354Q Full bridge current driven vertical deflection output circuit in LVDMOS Preliminary specification File under Integrated Circuits, IC02 1998 Sep 03 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS TDA8354Q FEATURES GENERAL DESCRIPTION • Few external components The TDA8354Q is a power circuit for use in 90° and 110° colour deflection systems for field frequencies of 25 to 200 Hz and 16 : 9 picture tubes. The circuit provides a DC-driven vertical deflection output circuit, operating as a highly efficient class G system. Due to the full bridge output circuit the deflection coils can be DC coupled. • Highly efficient fully DC-coupled vertical output bridge circuit • Short rise and fall times of the vertical flyback switch • Guard circuit • Temperature (thermal) protection The IC is constructed in a low-voltage DMOS process that combines bipolar, CMOS and DMOS devices, to provide ruggedness. • High ElectroMagnetic Compatibility (EMC) because of common mode inputs • Guard signal in zoom mode. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC supply VP supply voltage Iq(av) average quiescent supply current Vflb flyback supply voltage IVflb(av) average flyback supply current during scan during scan 7.5 12 − 18 V 10 15 mA 2 × VP 45 68 V − − 10 mA Vertical circuit Io(p-p) output current (peak-to-peak value) − − 3.2 A Ii(diff)(p-p) input current (peak-to-peak value) at pin 11 or 12 − 500 600 µA − − ±1.6 A Flyback switch Io(Vflb) t ≤ 1.5 ms peak output current Thermal data (in accordance with IEC 747-1) Tstg storage temperature −55 − +150 °C Tamb operating ambient temperature −25 − +75 °C Tj junction temperature − − 150 °C ORDERING INFORMATION TYPE NUMBER TDA8354Q 1998 Sep 03 PACKAGE NAME DBS13P DESCRIPTION plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) 2 VERSION SOT141-6 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS TDA8354Q BLOCK DIAGRAM Vo(guard) VP(B) handbook, full pagewidth 1 VP(A) 4 Vflb 10 7 GUARD CIRCUIT Ii(diff) Ii(pos) 12 9 Ii(bias) Ii(diff) COMPENSATION 13 CIRCUIT 2 INPUT/ FEEDBACK 3 Ii(diff) Ii(bias) Ii(diff) Ii(neg) 5 11 Ii(comp) Vi(M) Vi(con) Vo(B) TDA8354Q 6 GNDB 8 GNDA Fig.1 Block diagram. 1998 Sep 03 Vo(A) 3 MGL461 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS PINNING TDA8354Q FUNCTIONAL DESCRIPTION SYMBOL PIN The vertical driver circuit is a bridge configuration. The deflection coil is connected between the output amplifiers, which are driven in phase opposition. The differential input circuit is current driven. The input circuit is special intended for direct connection to driver circuits which deliver symmetrical current signals, but is also suitable for asymmetrical currents. The current to voltage conversion is done by the external resistor (Rcon) connected between the output of the input conversion stage and output stage B. This voltage is compared with the output current through the deflection coil measured as voltage across RM, which provides internal feedback information. The relationship between the differential input current and the output current is defined by: 2 × Ii(diff) × Rcon = Icoil × RM The output current is adjustable from 0.5 A (p-p) to 3.2 A (p-p) by varying Rcon. The maximum input current is 800 µA peak for each pin. The minimum input current should be 50 µA. DESCRIPTION Vo(guard) 1 guard output voltage Vi(M) 2 measuring resistor input Vi(con) 3 conversion resistor input VP(B) 4 supply voltage B Vo(B) 5 output voltage B GNDB 6 ground B Vflb 7 flyback supply voltage GNDA 8 ground A Vo(A) 9 output voltage A VP(A) 10 supply voltage A Ii(neg) 11 input power-stage (negative); includes Ii(bias) signal bias Ii(pos) 12 input power-stage (positive); includes Ii(bias) signal bias Ii(comp) 13 damping resistor compensation current input Flyback supply The flyback voltage is determined by an additional supply voltage Vflb. The principle of operating with two supply voltages (class G) makes it possible to fix the supply voltage VP optimum for the scan voltage and the second supply voltage Vflb optimum for the flyback voltage. Using this method, very high efficiency is achieved. The supply voltage Vflb is almost totally available as flyback voltage across the coil, this being possible due to the absence of a coupling capacitor (not necessary, due to the bridge configuration). The very short rise and fall time of the flyback switch is >400 V/µs. handbook, halfpage Vo(guard) 1 Vi(M) 2 Vi(con) 3 VP(B) 4 Vo(B) 5 GNDB 6 Vflb 7 GNDA 8 • Die temperature control Vo(A) 9 • Overvoltage of output stage A. Protection TDA8354Q The output circuit has protection circuits for: VP(A) 10 Ii(neg) 11 Ii(pos) 12 Ii(comp) 13 MGL462 The die has been glued to the metal block of the package. If the metal block is not insulated from the heat sink, the heat sink may only be connected directly to pins 6 and 8. Fig.2 Pin configuration. 1998 Sep 03 4 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS TDA8354Q Guard circuit Damping resistor compensation A guard circuit with output signal Vo(guard) is provided. For HF-loop stability a damping resistor is connected across the deflection coil. There is a big difference in current in the damping resistor Rp during scan and flyback. The resistor current is summed to the current in the deflection coil via the measuring resistor RM, which results in a too low current in the deflection coil at the start of the scan. The guard circuit generates an active HIGH level during the flyback period. The guard circuit is also activated for one or more of the following conditions: • When the thermal protection is activated (Tj ≈ 170 °C) • During short-circuit of the output pins (pins 5 and 9) to VP or ground To reach a short settling time the difference in the current during scan and flyback in the damping resistor can be compensated for by external means. To do so a resistor (Rcomp) of about 1 MΩ can be connected between the output of stage A (pin 9) and the damping resistor compensation current input (pin 13). • During open coil • During open loop • During short-circuit of the input pins (pins 11 and 12) to VP or ground. An active HIGH level of the guard signal is also generated for the next conditions: For a more accurate calculation of Rcomp refer to the following formula: ( V flb – V loss – V P ) × R p × R con R comp = -------------------------------------------------------------------------------( V flb – V loss – I L × R L ) × R M • No drive signal • Short-circuit of the coil. However, for these events the signal is generated via an internal timer circuit. The guard signal set via this timer has a delay of ≈120 ms. The delay time is given by the lowest applicable field frequency. The guard signal can be used for blanking the picture tube screen and signalling a fault condition. 1998 Sep 03 5 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS TDA8354Q LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT DC supply VP supply voltage − 18 V Vflb flyback supply voltage − 68 V − 3.2 A − 68 V Vertical circuit Io(p-p) output current (peak-to-peak value) Vo(A) output voltage (pin 9) Vo(B) output voltage (pin 5) − VP V I1,2,3,11,12,13 current into or out of pins 1 to 3 and 11 to 13 −20 +20 mA V1,2,3,11,12,13 peak voltage on pins 1 to 3 and 11 to 13 −0.5 VP V − ±1.6 A note 1 Flyback switch Io(Vflb) peak output current Thermal data (in accordance with IEC 747-1) Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −25 +75 °C Tj junction temperature note 2 − 150 °C Miscellaneous tsc short-circuiting time note 3 − 1 h Ii/o current into any pin +1.5 × VP(max); note 4 − +200 mA current out of any pin −1.5 × VP(max); note 4 −200 − mA VESD electrostatic handling note 5 − ±300 V note 6 − ±2000 V Notes 1. When the pin voltage exceeds 70 V the device behaves like a power zener diode thus limiting the voltage. 2. Internally limited by thermal protection; switching point ≈170 °C. 3. Up to VP = 18 V. 4. At Tj(max). 5. Machine model: equivalent to discharge a 200 pF capacitor through a 0 Ω series resistor. Except pin 7: ±250 V. 6. Human body model: equivalent to discharge a 100 pF capacitor through a 1.5 kΩ series resistor. Except pin 7: ±1500 V. 1998 Sep 03 6 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS TDA8354Q THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS Rth(j-c) thermal resistance from junction to case Rth(j-a) thermal resistance from junction to ambient VALUE UNIT 4 K/W 40 K/W in free air CHARACTERISTICS VP = 12 V; Vflb = 45 V; fi = 50 Hz; Ii(bias) = 330 µA; Tamb = 25 °C; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC supply VP operating supply voltage Vflb flyback supply voltage 2 × VP 45 68 V Iq(av) average quiescent supply current during scan − 10 15 mA Iq quiescent supply current no signal; no load − 60 80 mA IVflb(av) average flyback supply current during scan − − 10 mA Io = 3.2 A (p-p); note 1 − − 6.0 V − − 4.8 V − − 4.2 V − − 3.4 V 7.5 12 18 V Output stage A and B Vloss voltage loss from pin 10 to 9 and from pin 5 to 6 voltage loss from pin 4 to 5 and from pin 9 to 8 voltage loss from pin 10 to 9 and from pin 5 to 6 Io = 2.2 A (p-p); note 1 voltage loss from pin 4 to 5 and from pin 9 to 8 LE linearity error adjacent blocks Io = 3.2 A (p-p); note 2 − 0.5 2 % not adjacent blocks Io = 3.2 A (p-p); note 2 − 0.5 3 % − 46 − V Ii(bias) = 500 µA − − 15 mV Ii(bias) = 100 µA Vo output voltage swing (flyback) Vo(A) − Vo(B) Ii(diff) = 0.3 mA; Io = 1.6 A Voffset offset voltage across RM Ii(diff) = 0 − − 13 mV ∆Voffset(T) offset voltage as function of temperature Ii(diff) = 0 − − 40 µV/K Vo(A), Vo(B) DC output voltage Ii(diff) = 0; note 3 − − V Gv(ol) open-loop voltage gain V9 to 5/V3 to 5 notes 4 and 5 − − dB V3 to 5/V2 to 5 voltage ratio V3 to 5/V2 to 5 fres frequency response (−3 dB) Gi current gain (Io/Ii(diff)) 1998 Sep 03 VP ------2 60 note 4 − 0 − dB open loop − 1 − kHz − 8000 − 7 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS SYMBOL PARAMETER ∆Gi(T) current gain drift as function of temperature PSRR power supply rejection ratio TDA8354Q CONDITIONS note 6 MIN. TYP. MAX. UNIT − − 10−4 80 90 − dB − 330 500 µA /K Input stage Ii(bias) signal bias current Ii(diff)(p-p) differential mode input current (peak-to-peak value) pin 11 or 12 note 7 − 500 600 µA Vi(diff) differential mode input voltage Ii(diff) = 500 µA − 0.75 − V Vi(cm) common mode input voltage Ii(bias) = 330 µA 0.95 1.15 1.35 V Flyback switch Io(Vflb) output peak current t < 1.5 ms − − ±1.6 A Vloss voltage loss (Vflb − Vo(A)) Io = +1.6 A − 8 9 V not active; Vo(guard) = 0 V − − 10 µA active; Vo(guard) = 4.5 V 1 − 2.5 mA Guard circuit Io(guard) Vo(guard) output current output voltage on pin 1 Io(guard) = 100 µA 5 6 7 V allowable voltage on pin 1 maximum leakage current = 10 µA − − 18 V Notes 1. At Tj = 125 °C. The temperature coefficient of Vloss has a positive sign. 2. The linearity error is measured without S correction and based on the same measurement principle as performed on the screen. The measuring method is as follows: Divide the output signal into 22 equal time parts ranging from 1 to 22 inclusive. Measure the value of the voltage across RM of two succeeding parts called one block (a) starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). Thus parts 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and not adjacent blocks (LENAB) are given below: ak – a ( k + 1) LEAB = ----------------------------a av a max – a min LENAB = ----------------------------a av 3. Vo(A) + Vo(B) = VP. At the start of the scan this equation is one diode voltage less. 4. The V value within formulae relates to voltages at or between relative pin numbers, i.e. V9 to 5/V3 to 5 = voltage value across pins 9 and 5 divided by voltage value across pins 3 and 5. 5. V2 to 5 AC short-circuited. 6. At V(ripple) = 500 mV (eff) at VP; measured across RM; f(ripple) = 50 Hz − 1 kHz. 7. Ii(bias) + Ii(diff) ≤ 800 µA and Ii(bias) − Ii(diff) ≥ 50 µA per pin. 1998 Sep 03 8 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS TDA8354Q INTERNAL CIRCUITRY Table 1 Equivalent pin circuits PIN 1 SYMBOL EQUIVALENT CIRCUIT Vo(guard) 300 Ω 1 MGL472 2 Vi(M) 300 Ω 2 MGL465 3 Vi(con) 300 Ω 3 MGL466 4 VP(B) 5 Vo(B) 6 GNDB 4 5 6 MGL467 1998 Sep 03 9 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS PIN SYMBOL 7 Vflb 8 GNDA 9 Vo(A) 10 VP(A) TDA8354Q EQUIVALENT CIRCUIT 10 9 8 7 MGL471 11 Ii(neg) 300 Ω 11 MGL470 12 Ii(pos) 300 Ω 12 MGL469 13 Ii(comp) 300 Ω 13 MGL468 1998 Sep 03 10 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS TDA8354Q TEST AND APPLICATION INFORMATION VP handbook, full pagewidth R(guard) Vflb Vo(guard) VP(B) 1 4 VP(A) Vflb 10 C4 C3 7 GUARD CIRCUIT Ii(diff) Ii(bias) Ii(diff) Ii(bias) Ii(pos) 12 9 RL Vo(A) Rcomp COMPENSATION 13 Ii(comp) CIRCUIT V 2 i(M) Ii(diff) INPUT/ FEEDBACK Ii(diff) 3 Vi(con) 11 Ii(neg) Ii(bias) 5 Vo(B) Ii(diff) Ii(bias) Ii(diff) TDA8354Q 6 GNDB 8 GNDA Fig.3 Test diagram. 1998 Sep 03 11 MGL463 Rp coil Rs Rcon RM Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS TDA8354Q VP handbook, full pagewidth R(guard) Vflb Vo(guard) VP(B) 1 4 VP(A) Vflb 10 C3 C4 C1 7 C2 C5 GUARD CIRCUIT Ii(diff) Ii(bias) Ii(diff) Ii(pos) 12 9 Vo(A) C6 Rcomp DEFLECTION PROCESSOR COMPENSATION 13 Ii(comp) CIRCUIT V 2 i(M) INPUT/ FEEDBACK Ii(neg) 3 coil Rs Rcon RM 11 C7 5 Vo(B) Ii(diff) Ii(bias) Ii(diff) TDA8354Q 8 6 GNDB MGL464 GNDA Coil: AT6216/42; VP = 12.1 V at fv = 50 Hz (vertical frame frequency); inclusive spread (absolute) and temperature rise in the coil; VP = 12.8 V at fv = 100 Hz (vertical frame frequency); inclusive spread (absolute) and temperature rise in the coil; Io(p-p) = 2.33 A (peak-to-peak); Ii(bias) = 330 µA; Ii(diff)(12-11) = 485 µA (peak value); Vflb = 45 V; tflb = 0.6 ms. RM = 0.5 Ω; Rcon = Rs = 1.2 kΩ; Rp = 300 Ω; Rcomp = 650 kΩ; R(guard) = 5 kΩ. Fig.4 Application diagram. 1998 Sep 03 Vi(con) Rp 12 C1 = 47 µF; 100 V; C2 = 220 µF; 25 V; C3 = C4 = 100 nF; C5 = 10 nF; C6 = C7 = 10 nF. Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS TDA8354Q PACKAGE OUTLINE DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6 non-concave Dh x D Eh view B: mounting base side d A2 B j E A L3 L Q c 1 v M 13 e1 Z e bp e2 m w M 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A2 bp c D (1) d Dh E (1) e e1 e2 Eh j L L3 m Q v w x Z (1) mm 17.0 15.5 4.6 4.2 0.75 0.60 0.48 0.38 24.0 23.6 20.0 19.6 10 12.2 11.8 3.4 1.7 5.08 6 3.4 3.1 12.4 11.0 2.4 1.6 4.3 2.1 1.8 0.8 0.25 0.03 2.00 1.45 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-03-11 97-12-16 SOT141-6 1998 Sep 03 EUROPEAN PROJECTION 13 Philips Semiconductors Preliminary specification Full bridge current driven vertical deflection output circuit in LVDMOS TDA8354Q The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/00/01/pp16 Date of release: 1998 Sep 03 Document order number: 9397 750 04083