STMICROELECTRONICS LY530ALTR

LY530AL
MEMS inertial sensor
single-axis analog and digital output yaw rate gyroscope
Preliminary Data
Features
■
2.7 V to 3.6 V single supply operation
■
Low power consumption
■
Embedded power-down
■
±300°/sec full scale
■
Absolute analog rate output
■
I2C/SPI digital output interface
■
Integrated low-pass filters
■
Additional high pass filter for digital output
■
Embedded self-test
■
High shock survivability
■
ECOPACK® RoHS and “Green” compliant
(see Section 7)
LGA-16 (5x5x1.5mm)
The output of LY530AL has a full scale of ±300 °/s
and is capable of measuring rates with a -3 dB
bandwidth up to 88 Hz.
Description
The LY530AL is a low-power single-axis yaw rate
sensor. It includes a sensing element and an IC
interface able to provide the measured angular
rate to the external world through an analog
output voltage and I2C/SPI digital interfaces.
The LY530AL is available in a plastic land grid
array (LGA) package and can operate within a
temperature range from -40 °C to +85 °C.
The LY530AL belongs to a family of products
suitable for a variety of applications, including:
– Gaming and virtual reality input devices
– Motion control with MMI (man-machine
interface)
– Image stabilization for digital video and
digital still cameras
– GPS navigation systems
– Appliances and robotics
The sensing element, capable of detecting the
yaw rate, is manufactured using a dedicated
micromachining process developed by ST to
produce inertial sensors and actuators on silicon
wafers.
The IC interface is manufactured using a CMOS
process that allows a high level of integration to
design a dedicated circuit which is trimmed to
better match the sensing element characteristics.
Table 1.
Device summary
Order code
Temperature range (°C)
Package
Packing
LY530AL
-40 to +85
LGA-16 (5x5x1.5)
Tray
LY530ALTR
-40 to +85
LGA-16 (5x5x1.5)
Tape and reel
September 2008
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/30
www.st.com
30
Contents
LY530AL
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
2
3
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Mechanical characteristics (analog output) . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Mechanical characteristics (digital output) . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.2
I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.2
Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.3
Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1
4.2
I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.2
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.3
SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/30
6.1
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2
CTRL_REG (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3
FILTER_CFG_REG (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LY530AL
Contents
6.4
OUTPUT_SEL_REG (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5
STATUS_REG(27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6
OUT_CONV_H(28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.7
OUT_CONV_L(29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/30
List of tables
LY530AL
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
4/30
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Mechanical characteristics @ Vdd = 3.3 V, T = 25 °C unless otherwise noted . . . . . . . . . . 8
Mechanical characteristics @ Vdd = 3.3 V, T = 25 °C unless otherwise noted . . . . . . . . . . 8
Electrical characteristics @ Vdd =3.3 V, T=25 °C unless otherwise noted. . . . . . . . . . . . . 10
SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PLL low-pass filter components’ values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transfer when Master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 19
Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 19
Registers addresses map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CTRL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CTRL_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FILTER_CFG_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FILTER_CFG_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
High pass filter pole -3dB frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Low pass filter pole -3dB frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
OUTPUT_SEL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
OUTPUT_SEL_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Filtering selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Forbidden combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STATUS_REG(27h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STATUS_REG(27h) description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
OUT_CONV_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
OUT_CONV_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LY530AL
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I2C slave timing diagram (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LY530AL electrical connections and external components values . . . . . . . . . . . . . . . . . . . 15
Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5/30
Block diagram and pin description
1
LY530AL
Block diagram and pin description
Figure 1.
Block diagram
ANALOG OUTPUT
+Ω
CHARGE
AMPLIFIER
Sens+
ACTIVE
LOW-PASS
FILTER
DEMODULATOR
SWITCHED
CAPACITOR
LOW-PASS
FILTER
z
Sens-
CS
CONTROL
A/D
CONVERTER
LOGIC
I2C
SCL/SPC
SDA/SDO/SDI
SPI
SDO
ANALOG
CONDITIONING
Feedback+
TRANSIMPEDANCE
AMPLIFIER
FeedbackDrive-
VOLTAGE
GAIN
AMPLIFIER
PID
control
AUTOMATIC
GAIN
CONTROL
PLL
Drive+
SELF TEST
TRIMMING
CIRCUITS
PHASE
CLOCK
GENERATOR
Pin description
+Ω
z
14
SDA_SDI_SDO
VDDA
Pin connection
Res
Figure 2.
VDDD
1.1
REFERENCE
16
13
1
SDO
VCONT
DR
CACT
CS
ANALOG OUTPUT
9
5
6
6/30
ST
PD
8
GND
SCL / SPC
(TOP VIEW)
DIRECTION OF THE
DETECTABLE
ANGULAR RATE
FILTVDD
(BOTTOM VIEW)
IF_DIS
LY530AL
Table 2.
Block diagram and pin description
Pin description
Pin #
Pin Name
1
FILTVDD
PLL filter connection pin #2
PLL filter connection pin #2
2
VCONT
PLL filter connection pin #1
PLL filter connection pin #1
3
CACT
Active filter capacitor
Active filter capacitor
4
ANALOG
OUTPUT
Rate signal output voltage
Leave unconnected
5
IF_DIS
Leave unconnected
Digital Interface Selection (See Table 19)
6
GND
0V supply voltage
0V supply voltage
7
ST
Self-test (logic 0: normal mode;
logic 1: self-test)
Leave unconnected
8
PD
Power-down (logic 0: normal
mode; logic 1: power-down mode)
Connect to Vdd
9
SCL
SPC
Leave unconnected
I2C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
10
CS
Leave unconnected
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI mode)
11
DR
Leave unconnected
DataReady
12
SDO
Leave unconnected or connect to
Vdd
SPI Serial data output (4-wire mode only)
I2C less significant bit of the device address
13
Analog function
Leave unconnected or connect to
SDA_SDI_SDO
Vdd
14
Res
15
16
Digital function
I2C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output
Connect to Vdd
Connect to Vdd
VDDD
Digital side Vdd supply
Digital side Vdd supply
VDDA
Analog side Vdd supply
Analog side Vdd supply
7/30
Mechanical and electrical specifications
LY530AL
2
Mechanical and electrical specifications
2.1
Mechanical characteristics (analog output)
Table 3.
Mechanical characteristics @ Vdd = 3.3 V, T = 25 °C unless otherwise noted(1)
Symbol
Parameter
FS
Measurement range
So
Sensitivity
SoDr
Sensitivity change vs.
temperature
Voff
Zero-rate level(3)
OffDr
NL
Test condition
Min.
From -40 °C to +85 °C
Zero-rate level change
From -40 °C to +85 °C
vs. temperature
Non linearity(4)
Best fit straight line
(5)(6)
CACT = 10 nF
Typ.(2)
Max.
Unit
±300
°/s
3.3
mV/ °/s
4
%
1.65
V
5
°/s
±0.8
% FS
88
Hz
BW
-3dB bandwidth
Rn
Rate noise density
0.1
°/s /
Hz
Vt
Self-test output
voltage change(7)
+300
mV
300
ms
4.5
kHz
Sup
Start-up time
Settling to ±5 °/s
Fres
Sensing element
resonant frequency
Top
Operating
temperature range
Wh
Product weight
-40
+85
160
°C
mg
1. The product is factory calibrated at 3.3 V. The operational power supply range is specified in Table 5.
2. Typical specifications are not guaranteed
3. Zero rate level is absolute with respect to power supply
4. Specified by design
5. The product is capable of sensing angular rates extending from DC to the selected bandwidth
6. User selectable by external capacitor CACT
7. “Self-test output voltage change” is defined as Vout(Vst = logic 1) - Vout(Vst = logic 0)
2.2
Mechanical characteristics (digital output)
Table 4.
Mechanical characteristics @ Vdd = 3.3 V, T = 25 °C unless otherwise noted(1)
Symbol
So
Parameter
Min.
Typ.(2)
Max.
Unit
1.55
LSb/ °/s
Voff
(3)
Zero-rate level
0
LSb
ODR
Output data rate
1
kHz
8/30
Sensitivity
Test condition
LY530AL
Table 4.
Symbol
Mechanical and electrical specifications
Mechanical characteristics @ Vdd = 3.3 V, T = 25 °C unless otherwise noted(1)
Parameter
Test condition
Min.
Typ.(2)
Max.
Unit
Self-test output
change(4)
230
LSb
Fres
Sensing element
resonant frequency
4.5
kHz
Top
Operating
temperature range
Wh
Product weight
Vt
-40
+85
160
°C
mg
1. The product is factory calibrated at 3.3 V. The operational power supply range is specified in Table 5.
2. Typical specifications are not guaranteed
3. The product is capable of sensing angular rates extending from DC to the selected bandwidth
4. “Self test output change” is defined as OUTPUT[LSb](Self-test bit on OUTPUT_SEL_REG=1) OUTPUT[LSb](Self-test bit on
OUTPUT_SEL_REG=0).
9/30
Mechanical and electrical specifications
LY530AL
2.3
Electrical characteristics
Table 5.
Electrical characteristics @ Vdd =3.3 V, T=25 °C unless otherwise noted(1)
Symbol
Vdd
Parameter
Supply voltage
Idd_A
Supply current (analog)
Idd_D
Supply current (digital)
IddPdn
Supply current in
power-down mode
VST
VPD
Max.
Unit
2.7
3.3
3.6
V
PD pin connected to GND
PD pin connected to Vdd
4.8
mA
5.5
mA
1
µA
0
0.2*Vdd
Logic 1 level
0.8*Vdd
Vdd
Power-down input
(Analog use)
Logic 0 level
0
0.2*Vdd
Logic 1 level
0.8*Vdd
Vdd
V
OVS
Output voltage swing(3)
V
10
0.4
Vdd-0.4
V
0.4
10
nF
Operating temperature
range
-40
+85
°C
Capacitive load
2. Typical specifications are not guaranteed
3. Referred to ANALOG OUTPUT pin #6
Iout = ±100µA
nF
drive(3)
1. The product is factory calibrated at 3.3 V
10/30
Typ.(2)
Logic 0 level
Active low-pass filter
capacitor
Top
Min.
Self-test input
(Analog use)
CACT
CLOAD
Test condition
LY530AL
Mechanical and electrical specifications
2.4
Communication interface characteristics
2.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6.
SPI slave timing values
Value(1)
Symbol
Parameter
Unit
Min
tc(SPC)
SPI clock cycle
fc(SPC)
SPI clock frequency
tsu(CS)
CS setup time
5
th(CS)
CS hold time
8
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
th(SO)
SDO output hold time
tdis(SO)
Max
100
ns
10
MHz
ns
50
6
SDO output disable time
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production
Figure 3.
CS
SPI slave timing diagram (2)
(3)
(3)
tc(SPC)
tsu(CS)
SPC
(3)
(3)
tsu(SI)
SDI
(3)
th(SI)
LSB IN
MSB IN
tv(SO)
SDO
th(CS)
(3)
MSB OUT
(3)
tdis(SO)
th(SO)
LSB OUT
(3)
2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and Output port
3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up
resistors
11/30
Mechanical and electrical specifications
LY530AL
I2C - Inter IC control interface
2.4.2
Subject to general operating conditions for Vdd and Top.
Table 7.
I2C slave timing values
I2C Standard mode(1)
Symbol
I2C Fast mode (1)
Parameter
f(SCL)
Unit
SCL clock frequency
Min
Max
Min
Max
0
100
0
400
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0(2)
KHz
µs
ns
3.45
0(2)
0.9
tr(SDA) tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb (3)
300
tf(SDA) tf(SCL)
SDA and SCL fall time
300
20 + 0.1Cb (3)
300
th(ST)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
4.7
1.3
µs
ns
µs
tw(SP:SR)
Bus free time between STOP
and START condition
1. Data based on standard I2C protocol requirement, not tested in production
2. A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL
3. Cb = total capacitance of one bus line, in pF
Figure 4.
I2C slave timing diagram (4)
REPEATED
START
START
tsu(SR)
tw(SP:SR)
SDA
tf(SDA)
tsu(SDA)
tr(SDA)
th(SDA)
tsu(SP)
SCL
th(ST)
tw(SCLL)
tw(SCLH)
tr(SCL)
tf(SCL)
4. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports
12/30
START
STOP
LY530AL
2.5
Mechanical and electrical specifications
Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 8.
Absolute maximum ratings
Symbol
Ratings
Vdd
Supply voltage
Vin
Input voltage on any control pin (PD, ST)
Maximum value
Unit
-0.3 to 6
V
-0.3 to Vdd +0.3
V
3000 g for 0.5 ms
AUNP
Acceleration (not powered)
TSTG
Storage temperature range
ESD
Electrostatic discharge protection
10000 g for 0.1 ms
-40 to +125
°C
2 (HBM)
kV
This is a mechanical shock sensitive device, improper handling can cause permanent
damage to the part
This is an ESD sensitive device, improper handling can cause permanent damage to
the part
13/30
Mechanical and electrical specifications
2.6
Terminology
2.6.1
Sensitivity
LY530AL
A yaw rate gyroscope is a Z-axis rate device that produces a positive-going output value for
counterclockwise rotation around the axis normal to the package top. Sensitivity describes
the gain of the sensor and can be determined by applying a defined angular velocity to it.
This value changes very little over temperature and also very little over time.
2.6.2
Zero-rate level
Zero-rate level describes the actual output value if there is no angular rate present.Zero-rate
level of precise MEMS sensors is, to some extent, a result of stress to the sensor and
therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit
board or after exposing it to extensive mechanical stress. This value changes very little over
temperature and also very little over time.
2.6.3
Self-test
Self-test allows to test the mechanical and electric part of the sensor, allowing the seismic
mass to be moved by means of an electrostatic test-force. If the device is used as analog
component the Self-test function is off when the ST pin is connected to GND. When the ST
pin is tied to Vdd, an actuation force is applied to the sensor, emulating a definite Coriolis
force. In this case the sensor output will exhibit a voltage change in its DC level which is also
depending on the supply voltage.
For the digital use of the device, the self test function is enabled acting on ST_bit inside
OUTPUT_SEL_REG(23h).
When ST is active, the device output level is given by the algebraic sum of the signals
produced by the velocity acting on the sensor and by the electrostatic test-force. If the output
signals change within the amplitude specified in Table 3, then the mechanical element is
working properly and the parameters of the interface chip are within the defined
specification.
14/30
LY530AL
Application hints
+Ω
LY530AL electrical9nF
connections and external components values
z
C2
9nF
9.5kOhm
450nF
GND
R1
GND VDDA VDDD
GND
GND
C1
1
Optional
Low-pass filter
100 nF
100 nF
10 µF
16
10 µF
14
SDA_SDI_SDO
13
SDO
LY530AL
(Top View)
CACT
ROPT
DR
CS
VoutYAW
0.4nF
COPT
GND
CLOAD
5
6
8
9
SCL/SPC
GND
GND
IF_DIS
PD
Figure 5.
ST
3
Application hints
Digital signals
Power supply decoupling capacitors (100 nF ceramic or polyester + 10 µF Aluminum)
should be placed as near as possible to the device (common design practice).
VDDA(pin 16) and VDDD(pin 15) lines have been kept separated to avoid switching noise
coupling on the analog side.
The LY530AL allows to band limit the output rate response through the use of two first-order
on-chip filters: a switched capacitor low-pass filter, with 400Hz -3dB bandwidth, in
combination with an active low-pass filter. The active filter -3 dB nominal frequency (ftA) is
set through an internal resistor RACT and the external capacitor CACT (added between
CACT pin #3 and ANALOG OUTPUT pin #4), by the formula:
1
f tA = -------------------------------------------------2π ⋅ R ACT ⋅ C ACT
The value of the internal resistor RACT is 180 kΩ, while the external capacitor CACT is used to
select the signal bandwidth. The sensed frequency range spans from DC up to the selected
bandwidth.
In order to further reduce high-frequency noise, the LY530AL supports an additional optional
low-pass filter on ANALOG OUTPUT pin #4 (Figure 5). The cutoff frequency (ftP) is given by
the formula:
15/30
Application hints
LY530AL
1
f t P = --------------------------------------------------2π ⋅ R OPT ⋅ C OPT
The LY530AL IC includes a PLL (phase locked loop) circuit to synchronize driving and
sensing interfaces. Capacitors and resistors must be added at the FILTVDD and VCONT
pins (as shown in Figure 5) to implement a second-order low-pass filter. Table 9
summarizes the PLL low-pass filter components’ values.
Table 9.
3.1
PLL low-pass filter components’ values
Component
Value
C1
450 nF ± 10%
C2
9 nF ± 10%
R1
9.5 kΩ ± 10%
Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020C.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com/mems.
16/30
LY530AL
4
Digital interfaces
Digital interfaces
The registers embedded inside the LY530AL may be accessed through both the I2C and SPI
serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, CS
line must be tied high (i.e connected to Vdd_IO).
Table 10.
Serial interface pin description
Pin name
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
CS
SCL/SPC
SDA/SDI/SDO
I2C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
I2C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
I2C less significant bit of the device address
SDO
4.1
Pin description
I2C serial interface
The LY530AL I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
Table 11.
I2C terminology
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave
The device addressed by the master
There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor
embedded inside the LY530AL. When the bus is free both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the
normal mode.
17/30
Digital interfaces
4.1.1
LY530AL
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the LY530AL is 110100xb. SDO pin can be used to
modify less significant bit of the device address. If SDO pin is connected to voltage supply
LSb is ‘1’ (address 1101001b) else if SDO pin is connected to ground LSb value is ‘0’
(address 1101000b). This solution permits to connect and address two different gyroscopes
to the same I2C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the LY530AL behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7
LSb represent the actual register address while the MSB enables address auto increment. If
the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented
to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’
(Write) the Master will transmit to the slave with direction unchanged. Table explains how
the SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 12.
Command
SAD[6:1]
SAD[0] = SDO
R/W
Read
110100
0
1
11010001 (39h)
Write
110100
0
0
11010000 (38h)
Read
110100
1
1
11010011 (3Bh)
Write
110100
1
0
11010010 (3Ah)
Table 13.
Master
Slave
18/30
SAD+Read/Write patterns
SAD+R/W
Transfer when Master is writing one byte to slave
ST
SAD + W
SUB
SAK
DATA
SAK
SP
SAK
LY530AL
Digital interfaces
Table 14.
Master
Transfer when Master is writing multiple bytes to slave
ST
SAD + W
Slave
SAK
Table 15.
Master
Master
Slave
DATA
DATA
SAK
SAK
SP
SAK
Transfer when Master is receiving (reading) one byte of data from slave
ST
SAD + W
Slave
Table 16.
SUB
SUB
SAK
SR
SAD + R
SAK
NMAK
SAK
SP
DATA
Transfer when Master is receiving (reading) multiple bytes of data from slave
ST SAD+W
SUB
SAK
SR SAD+R
SAK
MAK
SAK
DATA
MAK
DATA
NMAK
SP
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is Master Acknowledge and NMAK is No
Master Acknowledge.
4.2
SPI bus interface
The LY530AL SPI is a bus slave. The SPI allows to write and read the registers of the
device.
The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
19/30
Digital interfaces
LY530AL
Figure 6.
Read & write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the Serial Port Clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the Read Register and Write Register commands are completed in 16 clock pulses or
in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling
edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just
before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.
When 1, the address will be auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb
first).
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
In multiple read/write commands further blocks of 8 clock periods will be added. When MS
bit is 0 the address used to read/write data remains the same for every block. When MS bit
is 1 the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
20/30
LY530AL
4.2.1
Digital interfaces
SPI read
Figure 7.
SPI read protocol
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
bit 16-... : data DO(...-8). Further data in multiple byte reading.
Figure 8.
Multiple bytes SPI read protocol (2 bytes example)
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8
4.2.2
SPI write
Figure 9.
SPI write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
21/30
Digital interfaces
LY530AL
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: WRITE bit. The value is 0.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
writing.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device
(MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writing.
Figure 10. Multiple bytes SPI write protocol (2 bytes example)
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
4.2.3
SPI read in 3-wires mode
3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in
CTRL_REG2.
Figure 11. SPI read protocol in 3-wires mode
CS
SPC
SDI/O
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI Read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
Multiple read command is also available in 3-wires mode.
22/30
LY530AL
5
Register mapping
Register mapping
The table given below provides a listing of the 8 bit registers embedded in the device and
the related addresses:
Table 17.
Registers addresses map
Register address
Name
Type
Default
Hex
Reserved (do not modify)
WHO_AM_I
00-0E
r
Reserved (do not modify)
CTRL_REG
0F
Reserved
000 1111 11010001
10-1F
rw
Reserved (do not modify)
Comment
Binary
Dummy register
Reserved
20
010 0000 00000000
21
010 0001
Reserved
Loaded at boot
FILTER_CFG_REG
rw
22
010 0010
OUTPUT_SEL_REG
rw
23
010 0011 00000000
Reserved (do not modify)
24
001 1000
Reserved
Reserved (do not modify)
25
001 1001
Reserved
Reserved (do not modify)
26
001 1010
Reserved
STATUS_REG
r
27
010 0111 00000000
OUT_CONV_H
r
28
010 1000
OUT_CONV_L
r
29
010 1001
Registers marked as “Reserved” or not listed must not be changed. The writing to those
registers may cause permanent damages to the device.
23/30
Register description
6
LY530AL
Register description
The device contains a set of registers which are used to control its behavior and to retrieve
angular rate data. The registers address, made of 7 bits, is used to identify them and to write
the data through serial interface.
6.1
WHO_AM_I (0Fh)
Table 18.
1
WHO_AM_I register
1
0
1
0
0
0
1
BOOT
SIM
Device identification register.
This register contains the device identifier that for LY530AL is set to D1h
6.2
CTRL_REG (20h)
Table 19.
TUD_SDO
CTRL_REG register
DIG_en
0(1)
IF_SEL
BDU
alg
1. ‘0’ is the default value. This value must not be changed
Table 20.
CTRL_REG description
TUD_SDO
Pull Up disable for SDO pin. Default value: 0
(0: Pull Up connected; 1: Pull Up disabled)
DIG_en
Power Down bit. Default value: 0
(0: Device is in power down mode; 1: Divice is in normal mode)
IF_SEL
Interface selection. Default value: 0
(0: both interfaces available; 1: IF_DIS pin value selects the interface)
BDU
Block data update. Default value: 0
(0: continuos update; 1: update inhibited)
alg
Data alignment selection bit. Default value: 0
(0: 16 bit left justified; 1: 10 bit right justified)
BOOT
Reboot of memory content. Default value: 0
(0: normal mode; 1: memory reboot)
SIM
SPI serial interface mode selection bit. Default value: 0
(0: 4-wire mode; 1:3-wire mode)
TUD_SDO: When this bit is set to ‘1’ the Pull Up on SDO pin is disabled.
DIG_en: When this bit is set to ‘1’ the device is in normal mode. When DIG_en bit is ‘0’ the
device is in power down mode.
IF_SEL: Setting this bit to ‘1’ the voltage value applied to IF_DIS pin selects one of the two
digital interfaces (‘1’ for I2C only, ‘0’ for SPI only).
24/30
LY530AL
Register description
BDU: This bit is used to inhibit output registers update until both upper and lower parts are
read. In default mode (BDU=’0’) the output registers values are updated continuosly. It is
recommended to set BDU bit to ‘1’ if the reading is not faster than the output data rate.
alg: This bit permits to decide between 16 bits left justified (default value) and 10 bits right
justified representation of data coming from the device. In this last case the most significant
bits are replaced by the bit representing the sign.
BOOT bit is used to refresh the content of internal registers stored in the flash memory
block. At the device power up the content of the flash memory block is transferred to the
internal registers related to trimming functions to permit a good behavior of the device itself.
If for any reason the content of trimming registers was changed it is sufficient to use this bit
to restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied
inside corresponding internal registers and it is used to calibrate the device. These values
are factory trimmed and they are different for every gyroscope. They permit a good behavior
of the device and normally they have not to be changed. At the end of the boot process the
BOOT bit is set again to ‘0’.
SIM bit selects the SPI Serial Interface Mode. When SIM is ‘0’ (default value) the 4-wire
interface mode is selected. The data coming from the device are sent to SDO pin. In 3-wire
interface mode output data are sent to SDA/SDI/SDO pin.
6.3
FILTER_CFG_REG (22h)
Table 21.
FILTER_CFG_REG register
HP_BW1
HP_BW0
LP_BW2
LP_BW1
LP_BW0
0 (1)
0
0
1. 0 is the default value loaded at boot. This value must not be changed.
Table 22.
FILTER_CFG_REG description
HP_BW(1-0)
High pass filter pole frequency selection
LP_BW(2-0)
Low pass filter pole frequency selection
Table 23.
Table 24.
High pass filter pole -3dB frequency selection
HP_BW[1:0]
Pole frequency [Hz]
00
1.25
01
0.31
10
0.15
11
0.08
Low pass filter pole -3dB frequency selection
LP_BW[2:0]
Pole frequency [Hz]
000
115
001
46.1
010
21.3
25/30
Register description
LY530AL
Table 24.
6.4
LP_BW[2:0]
Pole frequency [Hz]
011
10.3
100
5.1
101
2.5
110
1.2
111
0.6
OUTPUT_SEL_REG (23h)
Table 25.
X
OUTPUT_SEL_REG register
X
Table 26.
ST_bit
X
X
OUT2
OUT1
OUT0
OUTPUT_SEL_REG description
ST_bit
When Dig_en is set to ‘1’, ST_bit enables Selft Test function. Default value: 0
(0: no selft test activated; 1: self test enabled
OUT2-0
Output data filtering selection
Table 27.
Filtering selection
OUTPUT_SEL_REG[2:0]
Filter type
000
no filtering
001
high pass
011
2 x high pass
100
low pass
101
high pass + low pass
111
2 x high pass + low pass
Table 28.
26/30
Low pass filter pole -3dB frequency selection (continued)
Forbidden combinations
FILTER_CFG_REG[2:0]
OUTPUT_SEL_REG[2:0]
101
111
101
100
100
111
100
101
111
101
111
100
LY530AL
6.5
Register description
STATUS_REG(27h)
Table 29.
STATUS_REG(27h) register
X(1)
X
X
X
X
ow
davbH
davbL
1. Undefined value
Table 30.
6.6
STATUS_REG(27h) description
ow
Digital data overrun. When ‘1’, output registers have been updated before being read.
davbH
When this bit is ‘1’, new data is available on OUT_CONV_H (high part)
davbL
When this bit is ‘1’, new data is available on OUT_CONV_L (low part)
OUT_CONV_H(28h)
Table 31.
DOH7
OUT_CONV_H register
DOH6
DOH5
DOH4
DOH3
DOH2
DOH1
DOH0
These bits are the high part of digital output expressed as 2’s complement number. For data
alignment see alg bit in CTRL_REG(20h) (Table 20).
6.7
OUT_CONV_L(29h)
Table 32.
DOL7
OUT_CONV_L register
DOL6
DOL5
DOL4
DOL3
DOL2
DOL1
DOL0
These bits are the lowpart of digital output expressed as 2’s complement number. For data
alignment see alg bit in CTRL_REG(20h) (Table 20).
27/30
Package information
7
LY530AL
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK® is an ST trademark.
ECOPACK® specifications are available at: www.st.com.
Figure 12. LGA-16: mechanical data and package dimensions
A1
1.46
1.5
A2
A3
1.6
0.057
0.059
1.33
0.16
C
0.2
0.24
0.063
0.052
0.006
0.3
0.008
0.009
0.012
D1
4.85
5
5.15
0.191
0.197
0.203
E1
4.85
5
5.15
0.191
0.197
0.203
L
0.8
0.031
L1
3.2
0.126
M
1.6
M1
2.15
2.175
0.062
2.20
0.085
0.086
M2
1.625
0.064
N
2.175
0.086
N1
2.4
0.094
T1
0.8
T2
0.475
R
1.2
S
0.5
0.087
LGA-16 (5x5x1.6mm)
Land Grid Array Package
0.031
0.525
0.019
1.6
0.047
0.020
0.021
0.063
0.1
0.004
h
0.15
0.006
k
0.05
0.002
j
0.1
0.004
7887555A
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8
Revision history
Revision history
Table 33.
Document revision history
Date
Revision
03-Sep-2008
1
Changes
Initial release
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