PHILIPS SAA4992H

INTEGRATED CIRCUITS
DATA SHEET
SAA4992H
Field and line rate converter with
noise reduction
Product specification
File under Integrated Circuits, IC02
2000 Feb 04
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
5
BLOCK DIAGRAMS
6
PINNING
7
FUNCTIONAL DESCRIPTION
8
CONTROL REGISTER DESCRIPTION
9
LIMITING VALUES
10
THERMAL CHARACTERISTICS
11
CHARACTERISTICS
12
PACKAGE OUTLINE
13
SOLDERING
13.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
13.2
13.3
13.4
13.5
14
DEFINITIONS
15
LIFE SUPPORT APPLICATIONS
2000 Feb 04
2
SAA4992H
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
1
SAA4992H
2
FEATURES
• Upconversion of all 1fH film and video standards up to
292 active input lines per field
GENERAL DESCRIPTION
The SAA4992H is a completely digital monolithic
integrated circuit which can be used for field and line rate
conversion of all global TV standards.
• 100/120 Hz 2 : 1, 50/60 Hz 1 : 1 and 100/120 Hz 1 : 1
output formats
It features improved ‘Natural Motion’ performance and full
film upconversion for all 50 and 60 Hz film material.
• 4 : 1 : 1, 4 : 2 : 2 and 4 : 2 : 2 Differential Pulse Code
Modulation (DPCM) input colour formats; 4 : 1 : 1 and
4 : 2 : 2 output colour formats
It can be configured to emulate the SAA4990H as well as
the SAA4991WP. For demonstration purposes a split
screen mode to show the Dynamic Noise Reduction
(DNR) function and a colour vector overlay is available.
• Full 8-bit accuracy
• Scalable performance by applying 1, 2 or 3 external
field memories
The SAA4992H supports a Boundary Scan Test (BST)
circuit in accordance with IEEE 1149.
• Improved recursive de-interlacing
• Film (25 Hz, 30 Hz) upconversion to 100/120
movement phases per second
• Variable vertical sharpness enhancement
• Motion compensated 3D dynamic noise reduction
• High quality vertical zoom
• 2 Mbaud serial interface (SNERT).
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
VDD
supply voltage
3.0
3.3
IDD
supply current
−
fCLK
operating clock frequency
−
Tamb
ambient temperature
0
4
MAX.
UNIT
3.6
V
400
550
mA
32
33.3
MHz
−
70
°C
ORDERING INFORMATION
TYPE
NUMBER
SAA4992H
2000 Feb 04
PACKAGE
NAME
QFP160
DESCRIPTION
plastic quad flat package; 160 leads (lead length 1.6 mm);
body 28 × 28 × 3.4 mm; high stand-off height
3
VERSION
SOT322-2
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SNRST
27
26
25
YC0 to YC7
YD7 to YD0
YE0 to YE7
151, 152,
154 to 159
2 to 9
111, 112,
114 to 119
122 to 129
COMPRESS
DECOMPRESS
SEQUENCER
MUX
MUX
SNERT
INTERFACE
SAA4992H
DE-INTERLACER
4
vectors
CONTROL
TCK
TDO
TDI
TMS
TRST
TEST
CLK32
MPR
LEFT
35
34
TPM
ESM
VERTICAL
PEAKING
VERTICAL
ZOOM
82 to 89
YF7 to YF0
YG7 to YG0
MOTION ESTIMATOR
33
32
SPM
61 to 68
MPR
RIGHT
Philips Semiconductors
SNDA
DYNAMIC
NOISE
REDUCTION
YB7 to YB0
Field and line rate converter with noise
reduction
SNCL
45 to 52
BLOCK DIAGRAMS
YA0 to YA7
5
ndbook, full pagewidth
2000 Feb 04
FIELD MEMORY 3
FIELD MEMORY 2
vectors
BST/TEST
31
UPCONVERSION
30
79
MHB645
Product specification
Fig.1 Block diagram of the luminance part.
SAA4992H
The solid lines represent pixel data; the broken lines represent controls.
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UVB3 to UVB0
UVC0 to UVC3
UVD3 to UVD0
UVE0 to UVE3
10 to 13
107 to 110
130 to 133
37 to 44
DECOMPRESS/
REFORMAT
DECOMPRESS/
REFORMAT
DNR
5
SAA4992H
Philips Semiconductors
UVA0 to UVA7
FIELD MEMORY 3
147 to 150
COMPRESS/
FORMAT
Field and line rate converter with noise
reduction
dbook, full pagewidth
2000 Feb 04
FIELD MEMORY 2
vectors
MPR
LEFT
MPR
RIGHT
UPCONVERSION
FORMAT
VERTICAL
ZOOM
70 to 77
91 to 98
UVF7 to YVF0
UVG7 to YVG0
MHB646
Product specification
Fig.2 Block diagram of the chrominance part.
SAA4992H
The solid lines represent pixel data; the broken lines represent controls.
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
6
SAA4992H
PINNING
SYMBOL
PIN
DESCRIPTION(1)(2)
TYPE
VSSE
1
ground ground of output pads
YC0
2
input
bus C luminance input from field memory 2 bit 0 (LSB)
YC1
3
input
bus C luminance input from field memory 2 bit 1
YC2
4
input
bus C luminance input from field memory 2 bit 2
YC3
5
input
bus C luminance input from field memory 2 bit 3
YC4
6
input
bus C luminance input from field memory 2 bit 4
YC5
7
input
bus C luminance input from field memory 2 bit 5
YC6
8
input
bus C luminance input from field memory 2 bit 6
YC7
9
input
bus C luminance input from field memory 2 bit 7 (MSB)
UVC0
10
input
bus C chrominance input from field memory 2 bit 0 (LSB)
UVC1
11
input
bus C chrominance input from field memory 2 bit 1
UVC2
12
input
bus C chrominance input from field memory 2 bit 2
UVC3
13
input
bus C chrominance input from field memory 2 bit 3 (MSB)
REC
14
output
read enable output for bus C
VSSE
15
ground ground of output pads
VDDE
16
supply supply voltage of output pads
VSSI
17
ground core ground
VDDI
18
supply core supply voltage
JUMP0
19
input
configuration pin 0; will be stored in register 0B3 e.g. to indicate presence of 3rd field
memory; should be connected to ground or to VDDI via pull-up resistor; note 3
JUMP1
20
input
configuration pin 1; will be stored in register 0B5 e.g. to indicate presence of 16-bit
1st field memory for full 4 : 2 : 2; should be connected to ground or to VDDI via
pull-up resistor; note 3
VDDE
21
supply supply voltage of output pads
VDDI
22
supply core supply voltage
VSSI
23
ground core ground
RAMTST1
24
input
test pin 1 for internal RAM testing; connect to ground for normal operation
SNRST
25
input
SNERT bus reset
SNDA
26
I/O
SNERT bus data
SNCL
27
input
SNERT bus clock
VSSE
28
ground ground of output pads
RAMTST2
29
input
test pin 2 for internal RAM testing; connect to ground for normal operation
TEST
30
input
test mode input; if not used it has to be connected to ground
TRST
31
input
boundary scan test: reset input signal; if not used it has to be connected to ground via
pull-down resistor; note 3
TMS
32
input
boundary scan test: test mode select; if not used it has to be connected to VDDI via
pull-up resistor; note 3
TDI
33
input
boundary scan test: data input signal; if not used it has to be connected to VDDI via
pull-up resistor; note 3
TDO
34
output
boundary scan test: data output signal
2000 Feb 04
6
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
DESCRIPTION(1)(2)
SYMBOL
PIN
TYPE
TCK
35
input
VSSE
36
ground ground of output pads
UVA0
37
input
bus A chrominance input from field memory 1 bit 0 (LSB)
UVA1
38
input
bus A chrominance input from field memory 1 bit 1
UVA2
39
input
bus A chrominance input from field memory 1 bit 2
UVA3
40
input
bus A chrominance input from field memory 1 bit 3
UVA4
41
input
bus A chrominance input from field memory 1 bit 4
UVA5
42
input
bus A chrominance input from field memory 1 bit 5
UVA6
43
input
bus A chrominance input from field memory 1 bit 6
UVA7
44
input
bus A chrominance input from field memory 1 bit 7 (MSB)
YA0
45
input
bus A luminance input from field memory 1 bit 0 (LSB)
YA1
46
input
bus A luminance input from field memory 1 bit 1
YA2
47
input
bus A luminance input from field memory 1 bit 2
YA3
48
input
bus A luminance input from field memory 1 bit 3
YA4
49
input
bus A luminance input from field memory 1 bit 4
YA5
50
input
bus A luminance input from field memory 1 bit 5
YA6
51
input
bus A luminance input from field memory 1 bit 6
YA7
52
input
bus A luminance input from field memory 1 bit 7 (MSB)
REA
53
output
read enable output for bus A
VSSE
54
ground ground of output pads
VSSI
55
ground core ground
VDDI
56
supply core supply voltage
VDDI
57
supply core supply voltage
VSSI
58
ground core ground
VSSE
59
ground ground of output pads
REF
60
input
read enable input for bus F and G
YF7
61
output
bus F luminance output bit 7 (MSB)
YF6
62
output
bus F luminance output bit 6
YF5
63
output
bus F luminance output bit 5
YF4
64
output
bus F luminance output bit 4
YF3
65
output
bus F luminance output bit 3
YF2
66
output
bus F luminance output bit 2
YF1
67
output
bus F luminance output bit 1
YF0
68
output
bus F luminance output bit 0 (LSB)
VDDE
69
supply supply voltage of output pads
UVF7
70
output
bus F chrominance output bit 7 (MSB)
UVF6
71
output
bus F chrominance output bit 6
UVF5
72
output
bus F chrominance output bit 5
UVF4
73
output
bus F chrominance output bit 4
UVF3
74
output
bus F chrominance output bit 3
2000 Feb 04
boundary scan test: clock input signal; if not used it has to be connected to VDDI via
pull-up resistor; note 3
7
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
DESCRIPTION(1)(2)
SYMBOL
PIN
TYPE
UVF2
75
output
bus F chrominance output bit 2
UVF1
76
output
bus F chrominance output bit 1
UVF0
77
output
bus F chrominance output bit 0 (LSB)
VSSE
78
ground ground of output pads
CLK32
79
input
VSSI
80
ground core ground
VSSE
81
ground ground of output pads
YG7
82
output
bus G luminance output bit 7 (MSB)
YG6
83
output
bus G luminance output bit 6
YG5
84
output
bus G luminance output bit 5
YG4
85
output
bus G luminance output bit 4
YG3
86
output
bus G luminance output bit 3
YG2
87
output
bus G luminance output bit 2
YG1
88
output
bus G luminance output bit 1
YG0
89
output
bus G luminance output bit 0 (LSB)
VDDE
90
supply supply voltage of output pads
UVG7
91
output
bus G chrominance output bit 7 (MSB)
UVG6
92
output
bus G chrominance output bit 6
UVG5
93
output
bus G chrominance output bit 5
UVG4
94
output
bus G chrominance output bit 4
UVG3
95
output
bus G chrominance output bit 3
UVG2
96
output
bus G chrominance output bit 2
UVG1
97
output
bus G chrominance output bit 1
UVG0
98
output
bus G chrominance output bit 0 (LSB)
system clock input
VSSE
99
ground ground of output pads
VSSI
100
ground core ground
VDDI
101
supply core supply voltage
VDDE
102
supply supply voltage of output pads
VDDI
103
supply core supply voltage
VSSI
104
ground core ground
VSSE
105
ground ground of output pads
WED
106
output
write enable output for bus D
UVD3
107
output
bus D chrominance output to field memory 3 bit 3 (MSB)
UVD2
108
output
bus D chrominance output to field memory 3 bit 2
UVD1
109
output
bus D chrominance output to field memory 3 bit 1
UVD0
110
output
bus D chrominance output to field memory 3 bit 0 (LSB)
YD7
111
output
bus D luminance output to field memory 3 bit 7 (MSB)
YD6
112
output
bus D luminance output to field memory 3 bit 6
VDDE
113
supply supply voltage of output pads
YD5
114
output
bus D luminance output to field memory 3 bit 5
YD4
115
output
bus D luminance output to field memory 3 bit 4
2000 Feb 04
8
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
DESCRIPTION(1)(2)
SYMBOL
PIN
TYPE
YD3
116
output
bus D luminance output to field memory 3 bit 3
YD2
117
output
bus D luminance output to field memory 3 bit 2
YD1
118
output
bus D luminance output to field memory 3 bit 1
YD0
119
output
bus D luminance output to field memory 3 bit 0 (LSB)
VSSE
120
ground ground of output pads
VSSE
121
ground ground of output pads
YE0
122
input
bus E luminance input from field memory 3 bit 0 (LSB)
YE1
123
input
bus E luminance input from field memory 3 bit 1
YE2
124
input
bus E luminance input from field memory 3 bit 2
YE3
125
input
bus E luminance input from field memory 3 bit 3
YE4
126
input
bus E luminance input from field memory 3 bit 4
YE5
127
input
bus E luminance input from field memory 3 bit 5
YE6
128
input
bus E luminance input from field memory 3 bit 6
YE7
129
input
bus E luminance input from field memory 3 bit 7 (MSB)
UVE0
130
input
bus E chrominance input from field memory 3 bit 0 (LSB)
UVE1
131
input
bus E chrominance input from field memory 3 bit 1
UVE2
132
input
bus E chrominance input from field memory 3 bit 2
UVE3
133
input
bus E chrominance input from field memory 3 bit 3 (MSB)
REE
134
output
read enable output for bus E
VSSE
135
ground ground of output pads
n.c.
136
−
VSSI
137
ground core ground
VDDI
138
supply core supply voltage
n.c.
139
−
not connected
not connected
not connected
n.c.
140
−
VDDE
141
supply supply voltage of output pads
VDDI
142
supply core supply voltage
VSSI
143
ground core ground
n.c.
144
−
VSSE
145
ground ground of output pads
WEB
146
output
write enable output for bus B
UVB3
147
output
bus B chrominance output to field memory 2 bit 3 (MSB)
UVB2
148
output
bus B chrominance output to field memory 2 bit 2
UVB1
149
output
bus B chrominance output to field memory 2 bit 1
UVB0
150
output
bus B chrominance output to field memory 2 bit 0 (LSB)
YB7
151
output
bus B luminance output to field memory 2 bit 7 (MSB)
YB6
152
output
bus B luminance output to field memory 2 bit 6
VDDE
153
supply supply voltage of output pads
YB5
154
output
bus B luminance output to field memory 2 bit 5
YB4
155
output
bus B luminance output to field memory 2 bit 4
YB3
156
output
bus B luminance output to field memory 2 bit 3
2000 Feb 04
not connected
9
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
DESCRIPTION(1)(2)
SYMBOL
PIN
TYPE
YB2
157
output
bus B luminance output to field memory 2 bit 2
YB1
158
output
bus B luminance output to field memory 2 bit 1
YB0
159
output
bus B luminance output to field memory 2 bit 0 (LSB)
VSSE
160
ground ground of output pads
Notes
1. Not used input pins (e.g. bus E) should be connected to ground.
2. Because of the noisy characteristic of the output pad supply it is recommended not to connect the core supply and
the output pad supply directly at the device. The output pad supply should be buffered as close as possible to the
device.
3. The external pull-up resistor should be 47 kΩ.
2000 Feb 04
10
Philips Semiconductors
Product specification
122 YE0
121 VSSE
123 YE1
124 YE2
125 YE3
126 YE4
127 YE5
128 YE6
129 YE7
130 UVE0
131 UVE1
132 UVE2
133 UVE3
134 REE
137 VSSI
136 n.c.
135 VSSE
139 n.c.
138 VDDI
SAA4992H
142 VDDI
141 VDDE
140 n.c.
144 n.c.
143 VSSI
146 WEB
145 VSSE
147 UVB3
148 UVB2
149 UVB1
150 UVB0
151 YB7
152 YB6
154 YB5
153 VDDE
155 YB4
156 YB3
157 YB2
158 YB1
handbook, full pagewidth
160 VSSE
159 YB0
Field and line rate converter with noise
reduction
VSSE
1
YC0
2
120 VSSE
119 YD0
YC1
3
118 YD1
YC2
4
117 YD2
YC3
5
116 YD3
YC4
6
115 YD4
YC5
7
YC6
8
114 YD5
113 VDDE
YC7
9
112 YD6
UVC0 10
111 YD7
UVC1 11
110 UVD0
UVC2 12
109 UVD1
UVC3 13
108 UVD2
REC 14
VSSE 15
VDDE 16
107 UVD3
VSSI 17
VDDI 18
JUMP0 19
104 VSSI
103 VDDI
JUMP1
VDDE
106 WED
105 VSSE
20
102 VDDE
101 VDDI
100 VSSI
SAA4992H
21
VDDI 22
VSSI 23
98
VSSE
UVG0
99
2000 Feb 04
75
76
77
UFV2
UFV1
UFV0
VSSE
80
74
UFV3
79
73
UFV4
11
CLK32
VSSI
72
UFV5
Fig.3 Pin configuration.
78
71
UFV6
YG7
VSSE
70
81
UFV7
40
69
UVA3
VDDE
82
68
39
67
YG6
UVA2
YF0
83
66
38
YF1
YG5
UVA1
YF2
84
65
YG4
37
64
85
YF3
36
YF4
YG3
VSSE
UVA0
63
86
62
35
YF5
YG2
TCK
61
87
YF6
34
YF7
YG1
TDO
60
YG0
88
REF
89
33
VSSI 58
VSSE 59
32
TDI
VDDI 56
VDDI 57
TMS
REA 53
VSSE 54
VSSI 55
UVG7
VDDE
YA7 52
90
YA6 51
31
49
TRST
YA5 50
91
YA4
30
48
UVG6
TEST
YA3
92
47
29
YA2
UVG5
RAMTST2
46
93
YA1
UVG4
28
45
94
YA0
27
44
UVG3
SNCL
VSSE
43
95
UVA7
26
UVA6
UVG2
SNDA
42
UVG1
96
41
97
25
UVA5
24
SNRST
UVA4
RAMTST1
MHB647
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
7
Table 1
FUNCTIONAL DESCRIPTION
The FAL (fal_top) module builds the functional top level of
the SAA4992H. It connects the luminance data path (KER,
kernel), the chrominance data path (COL, colour) and the
luminance (de)compression (YDP, Y-DPCM) with
SAA4992H inputs and outputs as well as controlling logic
(LSE, line sequencer; SNE, SNERT interface). Outside of
fal_top there are only the pad cells, boundary scan test
cells, the boundary scan test controller, the clock tree, the
test enable tree and the input port registers.
Clock cycle references
SIGNAL
Figure 4 shows a simplified block diagram of fal_top. It
displays the flow of pixel data (solid lines) and controls
(broken lines) between the modules inside.
Basic functionality of the modules in fal_top is as follows:
• KER (kernel): Y (luminance) data path
• COL (colour): UV (chrominance) data path
• YDP (Y-DPCM): compression (and decompression) of
luminance output (and input) data by Differential Pulse
Code Modulation (DPCM)
LATENCY
RE_F
0
RE_C and
RE_E
63 cycles + REceShift
YC, YE, UVC
and UVE
63 cycles
RE_A
94 cycles + REaShift
YA and UVA
94 cycles
YF, YG, UVF
and UVG
148 cycles + 3 input lines
WE_B and
WE_D
160 cycles + 4 input lines + WEbdShift
YB, YD, UVB
and UVD
160 cycles + 4 input lines
There is an algorithmic delay of 3 lines between input and
output data. Therefore, the main data output on the
F and G bus begins while the fourth input line is read.
Writing to the B and D bus starts one input line later.
The read and write enable signals RE_A, WE_B, RE_C,
WE_D and RE_E can be shifted by control registers
REaShift, WEbdShift and REceShift, which are
implemented in the line sequencer.
• LSE (line sequencer): generate line frequent control
signals
• SNE: Synchronous No parity Eight bit Reception and
Transmission (SNERT) interface to a microcontroller.
The SNERT interface operates in a slave receive and
transmit mode for communication with a microprocessor,
which resides on peripheral circuits (e.g. SAA4978H)
together with a SNERT master. The SNERT interface
transforms serial data from the microprocessor (via the
SNERT bus) into parallel data to be written into the
SAA4992Hs write registers and parallel data from
SAA4992Hs read registers into serial data to be sent to the
microprocessor. The SNERT bus consists of 3 signals:
The fal_top module itself reads the following control
register bits(addresses):
• NrofFMs (017)
• MatrixOn (026)
• MemComp and MemDecom (026).
NrofFMs and MatrixOn are used to enable the D and G
output bus, respectively. MemComp and MemDecom are
connected to YDP to control luminance data compression
and decompression. These control register signals are not
displayed in Fig.4. Further information on the control
registers is given in Chapter 8.
1. SNCL: used as serial clock signal, generated by the
master
2. SNDA: used as bidirectional data line
3. SNRST: used as a reset signal, generated by the
microprocessor to indicate the start of a transmission.
The processing of a video field begins on the rising edge
of the RE_F input signal. As indicated in Fig.4, the
SAA4992H expects its inputs and generates its outputs at
the following clock cycles after RE_F (see Table 1).
2000 Feb 04
SAA4992H
12
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
external field memories
handbook, full pagewidth
fal_top
WE_B,
WE_D
RE_C,
RE_W
UVB,
UVD
UVC,
UVE
YB,
YD
YC,
YE
160
cycles
63
cycles
160
cycles
63
cycles
160
cycles
63
cycles
UVA
94 cycles
YDP
COL
UVF, UVG
148 cycles
SNDA
SNE
LSE
RE_A
94 cycles
RE_F
0 cycles
YF, YG
148 cycles
KER
YA
94 cycles
MHB648
The solid lines represent pixel data; the broken lines represent controls.
Fig.4 Block diagram of fal_top.
2000 Feb 04
13
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NAME
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
DESCRIPTION(2)
DNR/peaking/colour
Kstep10
010
write; S
X X X X set LUT value: k = 1⁄16 if difference below (0 to 15)
Kstep0
Kstep1
Kstep32
X X X X
011
write; S
X X X X set LUT value: k = 2⁄8 if difference below (0 to 30 in multiples of 2)
Kstep2
Kstep3
Kstep54
X X X X
012
X X X X set LUT value: k = 4⁄8 if difference below (0 to 60 in multiples of 4)
Kstep5
X X X X
013
X X X X set LUT value: k = 6⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,
64, 72, 80, 88, 96, 104, 112 or 120)
14
Kstep7
X X X X
014
X X X X set fixed Y value; used when FixY = 1 or in left part of split screen
(0, 1⁄16 to 14⁄16 or 16⁄16)
GainY
X X X
FixY
X
015
write; S
X X X X set fixed UV value; used when FixUV = 1 or in left part of split screen
(0, 1⁄16 to 14⁄16 or 16⁄16)
GainUV
X X X
X
select fixed UV (adaptive or fixed) (full screen)
write; S
VecComp
X X X set degree of horizontal vector compensation in Y DNR:
(0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8 or 7⁄8) of the vector
X X X X
set vertical peaking level: (0, +2, +3.5, +5, +6, x, x, x, x, x, x, x, x,
−12, −6 or −2.5) dB
SAA4992H
016
set gain in difference signal for adaptive DNR UV (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)
Product specification
FixUV
PeakCoef
set gain in difference signal for adaptive DNR Y (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)
select fixed Y (adaptive or fixed) (full screen)
FixvalUV
Peak_Vcomp
set LUT value: k = 7⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,
64, 72, 80, 88, 96, 104, 112 or 120)
write; S
FixvalY
Gain_fix_uv
set LUT value: k = 5⁄8 if difference below (0 to 60 in multiples of 4)
write; S
Kstep6
Gain_fix_y
set LUT value: k = 3⁄8 if difference below (0 to 30 in multiples of 2)
write; S
Kstep4
Kstep76
set LUT value: k = 1⁄8 if difference below (0 to 15)
Philips Semiconductors
CONTROL REGISTER DESCRIPTION
Field and line rate converter with noise
reduction
2000 Feb 04
8
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017
DESCRIPTION(2)
write; S
ColourIn
X X select colour input format: (4 : 1 : 1, 4 : 2 : 2, 4 : 2 : 2 DPCM or
4 : 2 : 2)
ColourOut
X
NrofFMs
X
ColOvl
X
SlaveUVtoY
X
DnrSplit
X
DnrHpon
select colour output format: (4 : 1 : 1 or 4 : 2 : 2)
set number of field memories connected: (1 or 2/3)
select vector overlay on colour output: (vector overlay or colour
from video path)
slave UV noise reduction to K factor of Y: (separate or slaved)
select split screen mode for DNR: (normal or split screen)
X
switch DNR high-pass on (DNR only active on low frequent spectrum:
(all through DNR or high bypassed)
Vertical zoom
Zoom1
018
write; F
ZoomSt98
15
X X zoom line step bits 9 and 8; line step = vertical distance between
successive output lines; usable range = 0 to 2 frame lines;
resolution 1⁄256 frame line
ZoomPo98
Zoom2
X X
019
X X X X X X X X zoom line step bits 7 to 0 (see above)
01A
write; F
ZoomPo70
Zoom4
X X X X X X X X zoom start position bits 7 to 0 (see above)
01B
write; F
ZoomEnVal
X X X X zoom run in value = number of lines without zoom active
(0 to 15 lines)
zoom run out value = number of lines without zoom active
(−8 to +7 lines)
Product specification
X X X X
SAA4992H
ZoomDiVal
zoom start position bits 9 and 8; start position = vertical position of the
top display line; usable range = 1 to 3 frame lines; resolution 1⁄256
frame line
write; F
ZoomSt70
Zoom3
Philips Semiconductors
DNR_Colour_mode
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
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DESCRIPTION(2)
De-interlacer
Proscan1
01C
write; S
KlfLim
X X X X limitation of recursion factor in calculation of original line positions:
(1 to 16); 1 limits to almost full recursion, 16 limits to no recursion
KlfOfs
Proscan2
X X X X
01D
write; S
PlfLim
X X X X limitation of recursion factor in calculation of interpolated line
positions: (1 to 16); 1 limits to almost full recursion, 16 limits to no
recursion
16
PlfOfs
Proscan3
X X X X
01E
see KlfOfs; this offset applies to interpolated lines
write; S
PeakLim
PenInd
The transfer curve of the de-interlacing filter coefficient is determined
by the difference (Diff) between a line in the input field and the
counterpart in the previous field shifted over the estimated motion
vector. KlfOfs determines the bias of the transfer curve for the original
input line, such that coefficient = KlfOfs + F(Diff), where the function F
is calculated in the SAA4992H. The bias can take a value in the range
(0 to 15), representing decreasing filter strength.
Philips Semiconductors
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
X X X X Maximum that the peaked pixel is allowed to deviate from original pixel
value: deviation (0 to 30 in steps of 2). Above this deviation, the
peaked pixel is clipped to (original pixel + or − PeakLim).
X X X X
index to PenMed table (−256, −128, −64, −32, −16, −8, −4, 0, 4, 8, 16,
24, 32, 64, 128 or 255); penalty for applying (vertical/temporal)
median, in favour of applying vertical average within new field
Product specification
SAA4992H
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01F
DESCRIPTION(2)
write; F
PlfThr
X X X Multiplier threshold at which to switch the lower limit of the filter
coefficient for interpolated lines. Above this threshold, the differences
corresponding to the two neighbouring lines are used as clipping
parameters, below this threshold, the interpolated line difference is
used as clipping level. This parameter can be used to optimize the
de-interlacing quality in slowly moving edges; it is not likely to have
effect if PlfLim is high.
ProDiv
X X
UseVec
X
17
KplOff
X
Scaling factor to control the strength of the filtering for the interpolated
lines. A value 0 means no scaling (normal filtering), while 3 means
scaling by factor 8 (very strong filtering). This parameter can be used
to adjust the de-interlacing to varying level of noise in the input picture;
use higher scaling for higher noise.
Enables use of estimated vectors to shift pixels from previous frame to
the current time (null vector or estimated vectors). It is best
switched to ‘null vector’, if vectors are unreliable.
disable all recursion in calculating pixels for frame memory (recursive
or non recursive); to be true SAA4991WP and digital scan emulation
modes
Philips Semiconductors
Proscan4
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
General
NrBlks
020
write; S
NrBlks
X X X X X X number of blocks in active video (6 to 53, corresponds to
96 to 848 pixels), to be set as 1⁄16 (number of active pixels per
line + 15); take remarks on TotalPxDiv8 into consideration
TotalLnsAct98
X X
total number of output lines (bits 9 and 8)
write; S
X X X X X X X X total number of output lines (bits 7 to 0)
TotalPxDiv8
022
write; S
X X X X X X X X Total number of pixels per line divided-by-8 (80 to 128, corresponds to
640 to 1024 pixels). The horizontal blanking interval is calculated as
TotalPxDiv8 − 2 × NrBlks and has to be in the range from 12 to 124
(corresponds to 96 to 992 pixels). Conclusion: TotalPxDiv8 has to be
set to 12 + 2 × NrBlks < TotalPxDiv8 < 124 + 2 × NrBlks and NrBlks
TotalPxDiv8 – 124
TotalPxDiv8 – 12
has to be set to ------------------------------------------------ < NrBlks < --------------------------------------------2
2
REaShift
023
write; S
X X X shift of REa signal in number of pixels (0, +1, +2, +3, −4, −3, −2 or −1)
Product specification
021
SAA4992H
TotalLnsAct70
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024
write; S
WEbdShift
X X X shift of WEb and WEd signal in number of pixels
(0, +1, +2, +3, −4, −3, −2 or −1)
REceShift
POR
DESCRIPTION(2)
X X X
025
write; S
026
write; F
shift of REc and REe signal in number of pixels
(0, +1, +2, +3, −4, −3, −2 or −1)
X power-on reset command, to be set high temporarily during start-up
(normal or reset); note 3
Mode control
Control1
EstMode
X Set estimator mode; 0 = line alternating use of left and right estimator:
use in progressive scan except with vertical compress. 1 = field
alternating use of left and right estimator: use in field doubling and
progressive scan with vertical compress.
FilmMode
X
18
UpcMode
X X
MatrixOn
X
EmbraceOn
X
MemComp
MemDecom
X
X
set film mode; 0 = video camera mode; 1 = film mode
select upconversion quality; 00 = full, 01 = economy (DPCM),
10 = SAA4991WP, 11 = SAA4990H
Philips Semiconductors
WEbdREceShift
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
set matrix output mode; 1 = double output, disabling vertical peaking;
0 = normal single output mode
Master enable for embrace mode (off or on); SwapMpr in control2
should be at ‘swap’ position to really cross-switch FM1 and FM3 field
outputs. Should be set to logic 0 except in film mode and FM3 is
present, or in SAA4991WP film mode and MemComp bit is active.
set memory compression (luminance DPCM) (off or on)
set memory decompression (luminance DPCM) (off or on)
Product specification
SAA4992H
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027
write; F
QQcurr
X Quincunx phase of current field (in TPM) (phase0 or phase1); this
needs to toggle each time a new field comes from FM1. In phase0 the
estimator operates on a checker-board pattern that starts with the left
upper block; in phase1 the other blocks are estimated.
QQprev
X
FldStat
X
FieldWeYUV
X
19
OddFM1
X
SwapMpr
VecOffs
DESCRIPTION(2)
X
X X
quincunx phase of previous field (in TPM) (phase0 or phase1); this is
the value of QQcur during the last estimate written into the temporal
prediction memory
Field status (same input field or new input field); reflects whether
the output of FM1 is a new or a repeated field. This bit will toggle field
by field in field doubling mode and is continuously HIGH in progressive
output mode.
enable writing FM2 and FM3 for both luminance and chrominance
(recirculation of data for luminance alone can be controlled with
OrigFmEnY and IntpFmEnY in Control3) (off or on)
odd input field (even or odd), this is to be set equal to the detected
field interlace for the field that comes out of FM1
Philips Semiconductors
Control2
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
Swap multi port RAMs (normal or swap); this bit needs to be set to
get real frame data at the temporal position from FM1. If swapped, the
current field (FM1) will be stored in the right line memory tree, while
the original lines from the stored frame (FM2/3) are stored in the left
memory tree. Should be set only in film mode if FM3 is present;
EmbraceOn must be set as well.
Product specification
SAA4992H
Set vertical vector offset (0, +1, − or −1) frame lines; vertical offset of
the right line memory tree with respect to the left line memory tree.
A higher offset value means: on the right memory tree access to less
delayed video lines is taken; in interlaced video operation, the vertical
offset will be −1 with an odd field on the left side and +1 with an even
field on the left. With non-interlaced input, vertical offset should be
constantly 0. In film mode, vertical offset is dynamically switched
between +1, 0 and −1.
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028
DESCRIPTION(2)
write; F
OddLeft
X interlace (even or odd) phase of the field which is written to the left
line memory tree (left MPRAM)
OrigFmEnY
X
IntpFmEnY
X
FillTPM
X
VertOffsDNR
X X
enables writing luminance from de-interlacer in original field memory
(FM2), otherwise recirculation of luminance that is just read from FM2
(recirculate or update)
enables writing luminance from de-interlacer in interpolated field
memory (FM3), otherwise recirculation of luminance that is just read
from FM3 (recirculate or update)
Enables writing in temporal prediction memory (keep or update);
FillTPM should be set to ‘keep’ in SAA4991WP/film mode, in those
output fields where FM1 and FM2 contain the same motion phase.
FillTPM should be set to ‘update’ in all other situations.
20
Set vertical vector offset of DNR (0, +1, − or −1) frame lines; vertical
offset of the right line memory tree with respect to the left line memory
tree, before the swap action. A higher offset value means: on the right
memory tree access to less delayed video lines is taken; in interlaced
video operation, the vertical offset will be −1 with an odd field on the
left side and +1 with an even field on the left. With non-interlaced
input, vertical offset should be constantly logic 0; in film mode, vertical
offset is dynamically switched between +1, 0 and −1. It should be
noted that the signal OddFM1 is used to determine this offset.
Philips Semiconductors
Control3
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
Upconversion
Upconv1
029
write; F
UpcShFac
Upconv2
X X X X X X temporal interpolation factor used in luminance upconverter; value
ranges from 0 (for current field position) to 32 (for previous field
position)
02A
write
RollBack
F
X X X value used for coring the vertical vector component before application
in the upconverter; range: 0 to 3.5 in steps of 0.5 line; should remain
at logic 0 in normal operation
X X X X X
roll back factor ranging from 0 (use 0% of estimated vectors) to 16
(use 100% of estimated vectors)
Product specification
S
SAA4992H
YVecClip
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02B
write; S
MelzLfbm
X SAA4991WP type local fallback method instead of more robust local
fallback (complex or SAA4991WP type fallback)
Melzmemc
X
MelDeint
X
MixCtrl
X X X
21
UpcColShiFac
DESCRIPTION(2)
0C4
write; F
02C
write; S
SAA4991WP film mode memory control (normal or SAA4991WP
type); should be set in SAA4991WP film mode to ensure that only
original lines are selected as output when UpcShFac is 0 or 32
use (as in SAA4991WP) horizontal motion compensated median for
upconverter de-interlacing (normal or SAA4991WP type
de-interlacing)
Upconverter sensitivity:
0 to 3: smoothness dependent weighting between vector shifted
pixels and static pixels. 0 = sensitive to unsmoothness for taking more
of the static pixels ‘conservative’, up to 3 = hardly sensitive to
unsmoothness for taking more of static pixels ‘confident in vector
shifting’.
4 to 7: static weighting between vector shifted pixels and static pixels.
4 = take most of vector shifted pixels ‘confident in vector shifting’, up to
7 = take most of the static pixels ‘conservative’.
Philips Semiconductors
Upconv3
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
X X X X X X temporal interpolation factor used in chrominance upconverter; value
ranges from 0 (for current field position) to 32 (for previous field
position)
Motion estimator
Motest1
PenOdd
X X X additional penalty on vector candidates with odd vertical component
(0, 8, 16, 32, 64, 128, 256 or 511)
SpcThr
Active when EstMode = 0; select as estimated vector the output of the
right estimator unless its match error exceeds that of the left estimator
by more than (0, 8, 16 or 32). This parameter should normally be set
to logic 0.
Product specification
X X
Active when EstMode = 0; replace the spatial prediction of one
estimator (left or right) by that of the other if the match error of the
former exceeds that of the latter by more than (0, 8, 16, 32, 64, 128,
256 or 511). A higher threshold means the two estimators are very
independent.
SAA4992H
BmsThr
X X X
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02D
write; S
TavLow
X If the difference between the current vector and the previous one in
the same spatial location is within a small window, then the two
vectors are averaged to improve temporal consistency. TavLow is the
lower threshold of this window (1 or 2).
TavUpp
X X
MedEns
X X
LarEns
Motest3
MotShiFac
DESCRIPTION(2)
X X
02E
see above; TavUpp is the upper threshold (0, 4, 8 or 16)
scaling factor to reduce all sizes of update vectors in the ensemble
with medium sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)
scaling factor to reduce all sizes of update vectors in the ensemble
with large sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)
write; F
22
X X X X X X Motion estimator shift factor, being the temporal position used in the
estimator at which the matching is done; value 32 for matching at
previous field position down to 0 for matching at current field position.
Keeping MotShiFac equal to UpShiFac in the next upconverted output
field estimates for minimum matching errors (minimum Halo’s).
MotShiFac at value 16 gives the largest natural vector range (twice as
large as with value 0 or 32). Going above the range with
MotShiFac ≠ 16 is dealt with in SAA4992H by shifting towards 16, but
for the horizontal and vertical component separately (consequence is
that vector candidates tend to rotate towards the diagonal directions).
Philips Semiconductors
Motest2
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
Product specification
SAA4992H
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02F
write; S
PenRng
X Penalty for vectors estimated on the first row and the first column (if
left estimator is used) or the right column (if right estimator is used),
whenever the spatial prediction candidate is selected (16 or 64).
For noisy pictures, this register could be set to logic 1 to improve
border processing in the estimator.
CndSet
X
ErrThr
X X X
ErrHbl
X X
TstMod
23
Candidate1
X
090
to be kept to logic 1 for normal operation
X X X selection Candidate1 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
X X
Penalty1
X X X
091
update for Candidate1 (zero update, medium update, large update
or zero update)
penalty for Candidate1 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
Candidat2
X X X selection Candidate2 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update2
X X
Penalty2
X X X
write; S
Update3
X X
X X X
update for Candidate3 (zero update, medium update, large update
or zero update)
penalty for Candidate3 (0, 8, 16, 32, 64, 128, 256 or 511)
SAA4992H
X X X selection Candidate3 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Product specification
092
update for Candidate2 (zero update, medium update, large update
or zero update)
penalty for Candidate2 (0, 8, 16, 32, 64, 128, 256 or 511)
Candidat3
Penalty3
threshold on block match error for considering a block to be bad
(16, 32, 64, 128, 256, 512, 1024 or 2032)
write; S
Update1
Candidate3
choice of candidate set (left or right) for which data (Candidate1 to
Candidate8) is written in this field (becomes active in next field); see
note 3
number of horizontally adjacent blocks that have to be all bad before
considering an occurrence of a burst error (1, 2, 4 or 8) (counting of
burst errors is read out with BlockErrCnt, address 0A8)
Candidat1
Candidate2
DESCRIPTION(2)
Philips Semiconductors
Motest4
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
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093
write; S
Candidat4
X X X selection Candidate4 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update4
X X
Penalty4
Candidate5
X X X
094
write; S
X X X selection Candidate5 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update5
X X
Penalty5
X X X
095
penalty for Candidate5 (0, 8, 16, 32, 64, 128, 256 or 511)
24
X X X selection Candidate6 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update6
X X
Penalty6
X X X
096
write; S
X X X selection Candidate7 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update7
X X
Penalty7
X X X
097
update for Candidate7 (zero update, medium update, large update
or zero update)
penalty for Candidate7 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
Candidat8
Penalty8
X X X
098
write; S
update for Candidate8 (zero update, medium update, large update
or zero update)
penalty for Candidate8 (0, 8, 16, 32, 64, 128, 256 or 511)
X X X X X X X position of LeftUpp measurement point for pan-zoom calculations
(resolution: 16 pixels)
SAA4992H
X X
Product specification
X X X selection Candidate8 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update8
PZpositionLeftUppX
update for Candidate6 (zero update, medium update, large update
or zero update)
penalty for Candidate6 (0, 8, 16, 32, 64, 128, 256 or 511)
Candidat7
Candidate8
update for Candidate5 (zero update, medium update, large update
or zero update)
write; S
Candidat6
Candidate7
update for Candidate4 (zero update, medium update, large update
or zero update)
penalty for Candidate4 (0, 8, 16, 32, 64, 128, 256 or 511)
Candidat5
Candidate6
DESCRIPTION(2)
Philips Semiconductors
Candidate4
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
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DESCRIPTION(2)
099
write; S
X X X X X X X Y position of LeftUpp measurement point for pan-zoom calculations
(resolution: 4 lines)
PZpositionRightLowX 09A
write; S
X X X X X X X position of RightLow measurement point for pan-zoom calculations
(resolution: 16 pixels)
PZpositionRightLowY 09B
write; S
X X X X X X X Y position of RightLow measurement point for pan-zoom calculations
(resolution: 4 lines)
PZvectorStartX
09C
write; F
X X X X X X X X X start value of pan-zoom vectors
PZvectorDeltaX
09D
write; F
X X X X X X X X X delta value of pan-zoom vectors
PZvectorStartY
09E
write; F
X X X X X X X X Y start value of pan-zoom vectors
PZvectorDeltaY
09F
write; F
X X X X X X X X Y delta value of pan-zoom vectors
GlobalMSEmsb
0A0
read; F
GlobalMSElsb
0A1
read; F
X X X X X X X X Global Mean Square Error (MSE) = summation within a field period of
X X X X X X X X squared differences in comparing vector shifted video from frame
memory (FM2/3) with new field input (FM1) in those lines coinciding
with new field lines. The window for the measurement is kept at
40 pixels horizontal and 20 field lines vertical from the border of the
video. Measurements is only done in fields where the de-interlacer is
active, otherwise reading is zero. In field doubling mode, MSE is zero
at the end of every new input field.
GlobalMTImsb
0A2
read; F
GlobalMTIlsb
0A3
read; F
GlobalACTmsb
0A4
read; F
GlobalACTlsb
0A5
read; F
VectTempCons
0A6
read; F
Read data; note 3
Philips Semiconductors
PZpositionLeftUppY
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
25
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
X X X X X X X X Global Motion Trajectory Inconsistency (MTI) = summation within a
X X X X X X X X field period of squared differences comparing shifted video from frame
memory (FM2/3 output) with filtered data that is rewritten to the frame
memory (FM2/3 input) in those lines coinciding with new field lines.
The window for the measurement is kept at 40 pixels horizontal and
20 field lines vertical from the border of the video. Measurement is
done only in fields where de-interlacer is active, otherwise reading is
zero; in field doubling mode, MTI is zero at the end of every new input
field.
Product specification
X X X X X X X X Vector temporal consistency = summation over a field period of
absolute differences of horizontal plus vertical components of vectors
newly estimated for each block compared with those vectors
estimated in the previous run at the same spatial block position.
It should be noted that a lower figure implies better consistency.
SAA4992H
X X X X X X X X global activity (ACT) = summation over a field period of the horizontal
X X X X X X X X plus the vertical components of the vectors of all blocks
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DESCRIPTION(2)
0A7
read; F
X X X X X X X X Vector spatial consistency = summation over a field period of absolute
differences of horizontal and vertical components of vectors compared
with those of the neighbour blocks (L, R, U and D); in the comparison,
all vector data is used from the previous estimator run. It should be
noted that a lower figure implies better consistency
BlockErrCnt
0A8
read; F
X X X X X X X X burst error count (number of burst errors)
LeastErrSum
0A9
read; F
X X X X X X X X least error sum (summation over a field period of the smallest match
error that the estimator has found for each block: indicates reliability of
the estimation process)
YvecRangeErrCntmsb 0AA
read; F
X X X X X X X X Y vector range error count (number of vectors that have a vertical
component that is out of range for upconversion at the chosen
temporal position) (15 to 8)
YvecRangeErrCntlsb
0AB
read; F
X X X X X X X X Y vector range error count (7 to 0)
RefLineCountPrev
0AC
read; F
X X X X X X X X read out of (number of input (run-) lines − 40) used in previous field
RefLineCountNew
0AD
write; F
X X X X X X X X Write of [number of input (run-) lines − 40] to be used in new field
(actual maximum number of input lines in normal operation: 292;
register value 252). Nominally this is to be set as an exact copy of the
value read from RefLineCountPrev before a new field starts. In case
the effective number of input (run-) lines has increased,
RefLineCountNew should, for one field, be set to 255. This will occur
e.g. with decreasing vertical zoom magnification or changing from
525 lines video standard to 625 lines standard. If this is not done, a
deadlock will occur with too few lines processed correctly by the
motion estimator.
PanZoomVec0-X
0B0
read; F
X X X X X X X X pan-zoom vector 0 (8-bit X value)
PanZoomVec0-Y
0B1
read
26
VectSpatCons
S
PanZoomVec0-Y
F
0B2
read; F
PanZoomVec1-Y
0B3
read
StatusJump0
S
PanZoomVec1-Y
PanZoomVec2-X
F
0B4
read; F
SAA4992H identification: fixed bit, reading this bit as zero means
SAA4992H is present
X X X X X X X pan-zoom vector 0 (7-bit Y value)
X X X X X X X X pan-zoom vector 1 (8-bit X value)
X
read out of configuration pin JUMP0
X X X X X X X pan-zoom vector 1 (7-bit Y value)
X X X X X X X X pan-zoom vector 2 (8-bit X value)
SAA4992H
PanZoomVec1-X
0
Product specification
FalconIdent
Philips Semiconductors
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
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0B5
DESCRIPTION(2)
read
StatusJump1
S
PanZoomVec2-Y
F
X
read out of configuration pin JUMP1
X X X X X X X pan-zoom vector 2 (7-bit Y value)
27
PanZoomVec3-X
0B6
read; F
X X X X X X X X pan-zoom vector 2 (8-bit X value)
PanZoomVec3-Y
0B7
read; F
X X X X X X X pan-zoom vector 3 (7-bit Y value)
PanZoomVec4-X
0B8
read; F
X X X X X X X X pan-zoom vector 4 (8-bit X value)
PanZoomVec4-Y
0B9
read; F
X X X X X X X pan-zoom vector 4 (7-bit Y value)
PanZoomVec5-X
0BA
read; F
X X X X X X X X pan-zoom vector 5 (8-bit X value)
PanZoomVec5-Y
0BB
read; F
X X X X X X X pan-zoom vector 5 (7-bit Y value)
PanZoomVec6-X
0BC
read; F
X X X X X X X X pan-zoom vector 6 (8-bit X value)
PanZoomVec6-Y
0BD
read; F
X X X X X X X pan-zoom vector 6 (7-bit Y value)
PanZoomVec7-X
0BE
read; F
X X X X X X X X pan-zoom vector 7 (8-bit X value)
PanZoomVec7-Y
0BF
read; F
X X X X X X X pan-zoom vector 7 (7-bit Y value)
PanZoomVec8-X
0AE
read; F
X X X X X X X X pan-zoom vector 8 (8-bit X value)
PanZoomVec8-Y
0AF
read; F
EggSliceRgtMSB
0C0
read; F
X X X X X X X X result of right pixels egg-slice detector (15 to 8)
EggSliceRgtLSB
0C1
read; F
X X X X X X X X result of right pixels egg-slice detector (7 to 0)
EggSliceMixMSB
0C2
read; F
X X X X X X X X result of mixed pixels egg-slice detector (15 to 8)
EggSliceMixLSB
0C3
read; F
X X X X X X X X result of mixed pixels egg-slice detector (7 to 0)
X X X X X X X pan-zoom vector 8 (7-bit Y value)
Philips Semiconductors
PanZoomVec2-Y
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
HEX
Field and line rate converter with noise
reduction
2000 Feb 04
NAME
Notes
1. S means semi static, used at initialization or mode changes; F means field frequent, in general updated in each display field.
2. Selectable items are marked bold.
b) Write register 02F, bit 1: CndSet
c) Read register 0B0 to 0BF, 0AE and 0AF: pan_zoom_vectors, including FalconIdent (= 0), jump0 and jump1.
Product specification
a) Write register 025: power_on_reset
SAA4992H
3. Almost all of the R(ead) and W(rite) registers of SAA4992H are double buffered. The Write registers are latched by a signal called New_field.
New_field gets set, when RE_f rises after RSTR (New_field is effectively at the start of active video). The Read registers are latched by a signal
called Reg_upd. Reg_upd gets set, when half the number of active pixels of the fourth line of vertical blanking have entered the SAA4992H
(Reg_upd will effectively be active 3 and a halve lines after the RE_a, RE_c and RE_e have ended). The only exceptional registers, which are not
double buffered, are:
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+3.6
V
IDD
supply current
−
600
mA
Io
output current
−
2.0
mA
Vi
input voltage for all I/O pins
−0.5
+3.6
V
Tstg
storage temperature
−55
+150
°C
Tj
junction temperature
0
125
°C
10 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient in free air
27
K/W
Rth(j-c)
thermal resistance from junction to case
2.9
K/W
11 CHARACTERISTICS
VDD = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
General
VDD
supply voltage
3.0
3.3
3.6
V
IDD
supply current
−
400
550
mA
VOH
HIGH-level output voltage
2.4
−
−
V
VOL
LOW-level output voltage
−
−
0.4
V
VIH
HIGH-level input voltage
2.0
−
3.6
V
VIL
LOW-level input voltage
0
−
0.8
V
IOL
LOW-level output current
−
−
2
mA
Co(L)
output load capacitance
−
−
50
pF
Ci
input capacitance
−
−
8
pF
ILI
input leakage current
−
−
1
µA
Outputs; note 1; see Fig.5
IOZ
output current in 3-state mode
−
−
1
µA
td(o)
output delay time
−0.5 < Vo < 3.6
−
−
21
ns
th(o)
output hold time
4
−
−
ns
SR
slew rate
300
−
700
mV/ns
Inputs; note 2; see Fig.5
tsu(i)
input set-up time
8
−
−
ns
th(i)
input hold time
2
−
−
ns
2000 Feb 04
28
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SYMBOL
PARAMETER
SAA4992H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input CLK32; see Fig.5
tr
rise time
−
−
4
ns
tf
fall time
−
−
4
ns
δ
duty factor
40
−
60
%
Tcy
cycle time
30
−
39
ns
SNERT interface; see Fig.7
tSNRSTH
SNRST pulse HIGH time
500
−
−
ns
td(SNRST-SNCL)
delay SNRST pulse to SNCL LOW time
200
−
−
ns
Tcy(SNCL)
SNCL cycle time
0.5
−
1
µs
tsu(i)(SNCL)
input set-up time to SNCL
53
−
−
ns
th(i)(SNCL)
input hold time to SNCL
10
−
−
ns
th(o)
output hold time
30
−
−
ns
td(o)
output delay time
−
−
330
ns
to(en)
output enable time
210
−
−
ns
BST interface; see Fig.6
Tcy(BST)
BST cycle time
−
1
−
µs
tsu(i)(BST)
input set-up time
3
−
−
ns
th(i)(BST)
input hold time
6
−
−
ns
th(o)(BST)
output hold time
4
−
−
ns
td(o)(BST)
output delay time
−
−
30
ns
Notes
1. Timing characteristics are measured with CL = 15 pF; IOL = 2 mA; RL = 2 kΩ.
2. All inputs except SNERT, CLK32 and BST.
2000 Feb 04
29
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
tf
handbook, full pagewidth
90%
SAA4992H
tr
90%
CLOCK
1.5 V
10%
10%
INPUT
DATA
MHB175
tsu(i)
OUTPUT
DATA
th(i)
data
valid
data transition
period
th(o)
td(o)
Fig.5 Data input/output timing diagram.
Tcy(BST)
handbook, full pagewidth
TCK
TDI, TMS
t su(i)(BST)
t h(i)(BST)
TDO
t h(o)(BST)
t d(o)(BST)
Fig.6 Boundary scan test interface timing diagram.
2000 Feb 04
30
MHB649
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
handbook, full pagewidth
SNCL
write sequence:
SNDA
a0
a1
a2
a3
a4
a5
a6
a7
a0
a1
a2
a3
a4
a5
a6
a7
w0
w1
w2
w3
w4
w5
w6
w7
r0
r1
r2
r3
r4
r5
r6
r7
read sequence:
SNDA
driven by
master
SNDA
driven by
SAA4992H
SNCL
50%
t su(i)(SNCL)
write sequence:
SNDA
read sequence:
SNDA
driven by
master
50%
50%
t h(i)(SNCL)
a6
a7
a6
a7
w0
w1
t o(en)
SNDA
driven by
SAA4992H
r0
t d(o)
Fig.7 SNERT interface timing diagram.
2000 Feb 04
t h(o)
31
r1
t d(o)
MHB650
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
Table 2
SAA4992H
YUV formats; note 1
I/O PIN(1)
4 : 1 : 1 FORMAT(2)
4 : 2 : 2 FORMAT
4 : 2 : 2 DPCM
FORMAT(2)
YX7
Y07
Y17
Y27
Y37
Y07
Y17
Y07
Y17
YX6
Y06
Y16
Y26
Y36
Y06
Y16
Y06
Y16
YX5
Y05
Y15
Y25
Y35
Y05
Y15
Y05
Y15
YX4
Y04
Y14
Y24
Y34
Y04
Y14
Y04
Y14
YX3
Y03
Y13
Y23
Y33
Y03
Y13
Y03
Y13
YX2
Y02
Y12
Y22
Y32
Y02
Y12
Y02
Y12
YX1
Y01
Y11
Y21
Y31
Y01
Y11
Y01
Y11
YX0
Y00
Y10
Y20
Y30
Y00
Y10
Y00
Y10
UVX7
U07
U05
U03
U01
U07
V07
UC03
VC03
UVX6
U06
U04
U02
U00
U06
V06
UC02
VC02
UVX5
V07
V05
V03
V01
U05
V05
UC01
VC01
UVX4
V06
V04
V02
V00
U04
V04
UC00
VC00
UVX3
X
X
X
X
U03
V03
X
X
UVX2
X
X
X
X
U02
V02
X
X
UVX1
X
X
X
X
U01
V01
X
X
UVX0
X
X
X
X
U00
V00
X
X
Notes
1. Index X refers to different I/O buses:
a) X = A: input from 1st field memory
b) X = B: output to 2nd field memory
c) X = C: input from 2nd field memory
d) X = D: output to 3rd field memory
e) X = E: input from 3rd field memory
f) X = F: main output
g) X = G: 2nd output for matrix purposes.
The first index digit defines the sample number, the second defines the bit number.
2. X = don’t care or not available.
2000 Feb 04
32
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
12 PACKAGE OUTLINE
QFP160: plastic quad flat package;
160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height
SOT322-2
c
y
X
A
120
121
81
80
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
Lp
bp
L
pin 1 index
detail X
41
160
1
40
ZD
wM
bp
e
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
4.07
0.50
0.25
3.60
3.20
0.25
0.38
0.22
0.23
0.13
28.1
27.9
28.1
27.9
0.65
HD
HE
31.45 31.45
30.95 30.95
L
Lp
v
w
y
1.6
1.03
0.73
0.3
0.13
0.1
Z D(1) Z E (1)
1.5
1.1
1.5
1.1
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT322-2
135E12
MS-022
2000 Feb 04
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-11-03
00-01-19
33
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
13 SOLDERING
13.1
Introduction to soldering surface mount
packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
13.2
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
13.3
13.4
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2000 Feb 04
SAA4992H
34
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
13.5
SAA4992H
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
suitable(2)
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
14 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
15 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Feb 04
35
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 69
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/01/pp36
Date of release: 2000
Feb 04
Document order number:
9397 750 06587