PHILIPS TDA8790M

INTEGRATED CIRCUITS
DATA SHEET
TDA8790
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
Product specification
Supersedes data of 1995 May 08
File under Integrated Circuits, IC02
1996 Feb 21
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
FEATURES
APPLICATIONS
• 8-bit resolution
High-speed analog-to-digital conversion for:
• Operation between 2.7 and 5.5 V
• Video data digitizing
• Sampling rate up to 40 MHz
• Camera
• DC sampling allowed
• Camcorder
• High signal-to-noise ratio over a large analog input
frequency range (7.3 effective bits at 4.43 MHz
full-scale input at fclk = 40 MHz)
• Radio communication.
GENERAL DESCRIPTION
• CMOS/TTL compatible digital inputs and outputs
The TDA8790 is an 8-bit universal analog-to-digital
converter (ADC) for video and general purpose
applications. It converts the analog input signal from
2.7 to 5.5 V into 8-bit binary-coded digital words at a
maximum sampling rate of 40 MHz. All digital inputs and
outputs are CMOS/TTL compatible. A sleep mode allows
reduction of the device power consumption down to 4 mW.
• External reference voltage regulator
• Power dissipation only 30 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• Sleep mode (4 mW)
• No sample-and-hold circuit required.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDA
analog supply voltage
2.7
3.3
5.5
V
VDDD
digital supply voltage
2.7
3.3
5.5
V
VDDO
output stages supply voltage
2.5
3.3
5.5
V
∆VDD
supply voltage difference
−0.2
−
+0.2
V
VDDA − VDDD
−0.2
−
+2.25
V
IDDA
analog supply current
VDDD − VDDO
−
4
6
mA
IDDD
digital supply current
−
5
8
mA
IDDO
output stages supply current
fclk = 40 MHz; CL = 20 pF;
ramp input
−
1
2
mA
INL
integral non-linearity
fclk = 40 MHz; ramp input
−
±0.5
±0.75
LSB
DNL
differential non-linearity
fclk = 40 MHz; ramp input
−
±0.25
±0.5
LSB
fclk(max)
maximum clock frequency
40
−
−
MHz
Ptot
total power dissipation
VDDA = VDDD = VDDO = 3.3 V
−
30
53
mW
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8790M
SSOP20
plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
1996 Feb 21
2
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
BLOCK DIAGRAM
handbook, full pagewidth
V DDA
CLK
VDDD
5
1
3
2
CLOCK DRIVER
TDA8790
SLEEP
V RT 10
19 D7
18 D6
RLAD
analog
voltage input
VI
MSB
17 D5
9
ANALOG -TO - DIGITAL
CONVERTER
CMOS
OUTPUTS
LATCHES
16 D4
15 D3
V RM 8
data outputs
14 D2
13 D1
12 D0
20
VRB 7
6
VSSA
11
VSSO
analog
ground
output
ground
Fig.1 Block diagram.
1996 Feb 21
3
4
VSSD1
digital
ground
MBE502
LSB
VDDO
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
PINNING
SYMBOL
PIN
DESCRIPTION
CLK
1
clock input
SLEEP
2
sleep mode input
VDDD
3
digital supply voltage (2.7 to 5.5 V)
VSSD
4
digital ground
VDDA
5
analog supply voltage (2.7 to 5.5 V)
VSSA
6
analog ground
VRB
7
reference voltage BOTTOM input
VRM
8
reference voltage MIDDLE
VI
9
CLK
1
20 VDDO
SLEEP
2
19 D7
VDDD
3
18 D6
VSSD
4
17 D5
analog input voltage
VDDA
5
10
reference voltage TOP input
VSSA
6
15 D3
VSSO
11
digital output ground
VRB
7
14 D2
D0
12
data output; bit 0 (LSB)
VRM
8
13 D1
D1
13
data output; bit 1
12 D0
14
data output; bit 2
VI
9
D2
D3
15
data output; bit 3
D4
16
data output; bit 4
D5
17
data output; bit 5
D6
18
data output; bit 6
D7
19
data output; bit 7 (MSB)
VDDO
20
positive supply voltage for output
stage (2.7 to 5.5 V)
VRT
1996 Feb 21
16 D4
TDA8790
11 VSSO
VRT 10
MBE501
Fig.2 Pin configuration.
4
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDA
analog supply voltage
note 1
−0.3
+7.0
V
VDDD
digital supply voltage
note 1
−0.3
+7.0
V
VDDO
output stages supply voltage
note 1
−0.3
+7.0
V
∆VDD
supply voltage difference
VDDA − VDDD
−1.0
+4.0
V
VDDA − VDDO
−1.0
+4.0
V
−1.0
+4.0
V
VI
input voltage
VDDD − VDDO
referenced to VSSA
−0.3
+7.0
V
Vclk(p-p)
AC input voltage for switching
(peak-to-peak value)
referenced to VSSD
−
VDDD
V
IO
output current
−
10
mA
Tstg
storage temperature
−55
+150
°C
Tamb
operating ambient temperature
−20
+75
°C
Tj
junction temperature
−
+150
°C
Note
1. The supply voltages VDDA, VDDD and VDDO may have any value between −0.3 V and +7.0 V provided that the supply
voltage ∆VDD remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1996 Feb 21
PARAMETER
thermal resistance from junction to ambient in free air
5
VALUE
UNIT
120
K/W
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
CHARACTERISTICS
VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together;
Vi(p-p) = 1.84 V; CL = 20 pF; Tamb = 0 to +70 °C; typical values measured at Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDA
analog supply voltage
2.7
3.3
5.5
V
VDDD
digital supply voltage
2.7
3.3
5.5
V
VDDO
output stages supply voltage
2.5
3.3
5.5
V
∆VDD
supply voltage difference
−0.2
−
+0.2
V
VDDA − VDDD
−0.2
−
+2.25
V
IDDA
analog supply current
VDDD − VDDO
−
4
6
mA
IDDD
digital supply current
−
5
8
mA
IDDO
output stages supply current
−
1
2
mA
fclk = 40 MHz; ramp input;
CL = 20 pF
Inputs
CLOCK INPUT CLK (REFERENCED TO VSSD); see note 1
VIL
LOW level input voltage
0
−
0.3VDDD
V
VIH
HIGH level input voltage
0.7VDDD
−
VDDD
V
VDDD ≤ 3.6 V
0.6VDDD
−
VDDD
V
IIL
LOW level input current
Vclk = 0.3VDDD
−1
0
+1
µA
IIH
HIGH level input current
Vclk = 0.7VDDD
−
−
5
µA
ZI
input impedance
fclk = 40 MHz
−
4
−
kΩ
CI
input capacitance
fclk = 40 MHz
−
3
−
pF
INPUT SLEEP (REFERENCED TO VSSD); see Table 2
VIL
LOW level input voltage
0
−
0.3VDDD
V
VIH
HIGH level input voltage
0.7VDDD
−
VDDD
V
VDDD ≤ 3.6 V
0.6VDDD
−
VDDD
V
IIL
LOW level input current
VIL = 0.3VDDD
−1
−
−
µA
IIH
HIGH level input current
VIH = 0.7VDDD
−
−
+1
µA
VI (ANALOG INPUT VOLTAGE REFERENCED TO VSSA)
IIL
LOW level input current
VI = VRB
−
0
−
µA
IIH
HIGH level input current
VI = VRT
−
9
−
µA
ZI
input impedance
fi = 1 MHz
−
20
−
kΩ
CI
input capacitance
fi = 1 MHz
−
2
−
pF
1.1
1.2
−
V
Reference voltages for the resistor ladder; see Table 1
VRB
reference voltage BOTTOM
VTOP ≤ VDDA
VRT
reference voltage TOP
2.7
3.3
VDDA
V
Vdiff
differential reference voltage
VRT − VRB
1.5
2.1
2.7
V
Iref
reference current
−
0.95
−
mA
1996 Feb 21
6
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
SYMBOL
PARAMETER
TDA8790
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RLAD
resistor ladder
−
2.2
−
kΩ
TCRLAD
temperature coefficient of the
resistor ladder
−
1860
−
ppm
−
4092
−
mΩ/K
note 2
−
170
−
mV
VosB
offset voltage BOTTOM
VosT
offset voltage TOP
note 2
−
170
−
mV
Vi(p-p)
analog input voltage (peak-to-peak
value)
note 3
1.4
1.76
2.4
V
−
0.5
V
Outputs
DIGITAL OUTPUTS D7 TO D0 (REFERENCED TO VSSD)
VOL
LOW level output voltage
IO = 1 mA
0
VOH
HIGH level output voltage
IO = −1 mA
VDDO − 0.5 −
VDDO
V
IOZ
output current in 3-state mode
0.4 V < VO < VDDO
−20
−
+20
µA
Switching characteristics
CLOCK INPUT CLK; see Fig.4; note 1
fclk(max)
maximum clock frequency
40
−
−
MHz
tCPH
clock pulse width HIGH
9
−
−
ns
tCPL
clock pulse width LOW
9
−
−
ns
Analog signal processing
LINEARITY
INL
integral non-linearity
fclk = 40 MHz; ramp input;
see Fig.6
−
±0.5
±0.75
LSB
DNL
differential non-linearity
fclk = 40 MHz; ramp input;
see Fig.7
−
±0.25
±0.5
LSB
full-scale sine wave;
note 4
−
10
−
MHz
75% full-scale sine wave;
note 4
−
13
−
MHz
50% full-scale sine wave;
note 4
−
20
−
MHz
small signal at mid scale;
Vi = ±10 LSB at
code 128; note 4
−
350
−
MHz
BANDWIDTH (fclk = 40 MHz)
B
analog bandwidth
INPUT SET RESPONSE (fclk = 40 MHz; see Fig.8; note 5)
tSTLH
analog input settling time
LOW-to-HIGH
full-scale square wave
−
3
5
ns
tSTHL
analog input settling time
HIGH-to-LOW
full-scale square wave
−
3
5
ns
fi = 4.43 MHz
−
−50
−
dB
HARMONICS; (fclk = 40 MHZ; see Fig.9; note 6)
THD
total harmonic distortion
1996 Feb 21
7
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
SYMBOL
PARAMETER
TDA8790
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SIGNAL-TO-NOISE RATIO; see Fig.9; note 6
S/N
signal-to-noise ratio (full scale)
−
47
−
dB
fi = 300 kHz
−
7.8
−
bits
fi = 4.43 MHz
−
7.3
−
bits
fclk = 40 MHz;
PAL modulated ramp
−
1.5
−
%
fclk = 40 MHz;
PAL modulated ramp
−
0.25
−
deg
without harmonics;
fclk = 40 MHz;
fi = 4.43 MHz
EFFECTIVE BITS; see Fig.9; note 6
EB
effective bits
fclk = 40 MHz
DIFFERENTIAL GAIN; see note 7
Gdiff
differential gain
DIFFERENTIAL PHASE; see note 7
ϕdiff
differential phase
Timing (fclk = 40 MHz; CL = 20 pF); see Fig.4; note 8
tds
sampling delay time
−
−
5
ns
th
output hold time
5
−
−
ns
td
output delay time
VDDO = 4.75 V
8
12
15
ns
VDDO = 3.15 V
8
17
20
ns
VDDO = 2.7 V
8
18
21
ns
3-state sleep mode delay times; see Fig.5
tdZH
enable HIGH
−
14
18
ns
tdZL
enable LOW
−
16
20
ns
tdHZ
disable HIGH
−
16
20
ns
tdLZ
disable LOW
−
14
18
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. Analog input voltages producing code 0 up to and including 256:
a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (VRB) at Tamb = 25 °C.
b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
produces data outputs equal to 256 at Tamb = 25 °C.
1996 Feb 21
8
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 255 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.
V RT – V RB
a) The current flowing into the resistor ladder is I L = ----------------------------------------- and the full-scale input range at the converter,
R OB + R L + R OT
RL
to cover code 0 to code 255, is V i = R L × I L = ----------------------------------------- × ( V RT – V RB ) = 0.838 × ( V RT – V RB )
R OB + R L + R OT
b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio
RL
------------------------------------------ will be kept reasonably constant from part to part. Consequently variation of the output codes
R OB + R L + R OT
at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.
4. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, nor any significant attenuation is observed in the reconstructed signal.
5. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
6. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
7. Measurement carried out using video analyser VM700A, where video analog signal is reconstructed through a DAC.
8. Output data acquisition: the output data is available after the maximum delay time of td.
handbook, halfpage
VRT
9
ROT
VRM
code 255
RL
7
RLAD
IL
code 0
ROB
VRB
6
MGD284
Fig.3 Explanation of note 3.
1996 Feb 21
9
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
Table 1
TDA8790
Output coding and input voltage (typical values; referenced to VSSA)
BINARY OUTPUT BITS
VI(p-p)
(V)
D7
D6
D5
D4
D3
D2
D1
D0
Underflow
<1.37
0
0
0
0
0
0
0
0
0
1.37
0
0
0
0
0
0
0
0
1
.
0
0
0
0
0
0
0
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
STEP
254
.
1
1
1
1
1
1
1
0
255
3.13
1
1
1
1
1
1
1
1
Overflow
>3.13
1
1
1
1
1
1
1
1
Table 2
Sleep mode selection
SLEEP
D7 TO D0
IDDA + IDDD (typ.)
1
high impedance
1.2 mA
0
active
9 mA
t CPL
handbook, full pagewidth
t CPH
50 %
CLK
sample N
sample N + 1
sample N + 2
Vl
t ds
DATA
D0 to D7
th
VDDO
DATA
N-2
DATA
N-1
DATA
N
DATA
N+1
50 %
0V
td
MSA670
Fig.4 Timing diagram.
1996 Feb 21
10
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
handbook, full pagewidth
TDA8790
V DDD
50 %
SLEEP
t dHZ
t dZH
HIGH
90 %
output
data
50 %
t dLZ
LOW
t dZL
HIGH
output
data
50 %
LOW
10 %
V DDD
3.3 kΩ
S1
TDA8790
20 pF
SLEEP
TEST
S1
t dLZ
t dZL
VDDD
VDDD
t dHZ
GND
t dZH
GND
MBE503
fSLEEP = 100 kHz.
Fig.5 Timing diagram and test conditions of 3-state output delay time.
1996 Feb 21
11
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
MBE548
0.291
handbook, full pagewidth
A
(LSB)
0.178
0.065
−0.047
−0.160
−0.272
0
34
68
102
136
170
204
238
255
codes
Fig.6 Typical integral non-linearity (INL) performance.
MBE549
0.150
handbook, full pagewidth
A
(LSB)
0.091
0.032
−0.025
−0.84
−0.143
0
34
68
102
136
170
204
Fig.7 Typical differential non-linearity (DNL) performance.
1996 Feb 21
12
238
255
codes
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
t STHL
t STLH
handbook, full pagewidth
code 255
VI
50 %
50 %
code 0
5 ns
5 ns
CLK
50 %
50 %
2 ns
MBE504
2 ns
Fig.8 Analog input settling-time diagram.
MBE550
0
A
(dB)
20
40
60
80
100
120
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20
f (MHz)
Effective bits: 7.32; THD = 51.08 dB.
Harmonic levels (dB): 2nd = −68.99; 3rd = −51.62; 4th = −66.05; 5th = −63.23; 6th = −72.79.
Fig.9 Typical Fast Fourier Transform (fclk = 40 MHz; fi = 4.43 MHz).
1996 Feb 21
13
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
andbook, halfpage
V DDO
V DDA
D7 to D0
VI
V SSO
VSSA
MBE505
MLC857
Fig.11 Analog inputs.
Fig.10 CMOS data outputs.
handbook, halfpage
V DDO
VDDA
VRT
VRM
SLEEP
R LAD
VRB
VSSA
V SSO
MLC859
MBE506
Fig.12 SLEEP 3-state input.
1996 Feb 21
Fig.13 VRB, VRM and VRT.
14
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
V
DDD
handbook,
halfpage
1/2V
CLK
DDD
VSSD
MLC860
Fig.14 CLK input.
APPLICATION INFORMATION
CLK
SLEEP
VDDD
VSSD
VDDA
VSSA
(1)
VRB
VRM (1)
100
nF
VSSA
VI
100
nF
VRT
1
20
2
19
3
18
4
17
5
16
TDA8790
6
15
7
14
8
13
9
12
10
11
(1)
VSSA 100
nF
VDDO
D7
D6
D5
D4
D3
D2
D1
D0
VSSO
MBE507
VSSA
The analog and digital supplies should be separated and decoupled.
The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the
reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupled capacitor.
(1) VRB, VRM and VRT are decoupled to VSSA.
Fig.15 Application diagram.
1996 Feb 21
15
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
PACKAGE OUTLINE
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
D
SOT266-1
E
A
X
c
y
HE
v M A
Z
11
20
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.5
0.15
0
1.4
1.2
0.25
0.32
0.20
0.20
0.13
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.45
0.65
0.45
0.2
0.13
0.1
0.48
0.18
10
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
90-04-05
95-02-25
SOT266-1
1996 Feb 21
EUROPEAN
PROJECTION
16
o
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
cases reflow soldering is often used.
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering SSOP
Reflow soldering techniques are suitable for all SSOP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds at between 270 and
320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration:
45 minutes at 45 °C.
Wave soldering SSOP
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1996 Feb 21
17
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Feb 21
18
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
NOTES
1996 Feb 21
19
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SCDS47
© Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
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other industrial or intellectual property rights.
Printed in The Netherlands
537021/1100/03/pp20
Document order number:
Date of release: 1996 Feb 21
9397 750 00677