PHILIPS SAA7346

INTEGRATED CIRCUITS
DATA SHEET
SAA7346
Shock absorbing RAM addresser
Preliminary specification
File under Integrated Circuits, IC01
Philips Semiconductors
July 1994
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
FEATURES
GENERAL DESCRIPTION
• Absorbs shocks from x, y and z directions
The SAA7346 can be used to make a CD player
insensitive to shocks. To do this, SAA7346 operates
closely with a standard 1 Mbit or 4 Mbit DRAM. Audio data
is stored inside the DRAM and during shocks the data of
the DRAM can be played. The SAA7346 functions as a
customized DRAM controller with serial I/O and on-board
shock detectors.
• Absorbs rotational shocks
• Absorbs multiple shocks per second
• Interfaces directly to compact disc decoders SAA7345,
SAA7347 and SAA7370
• Multi-speed I2S-bus input with single-speed
I2S-bus output
• Controls 1 or 4 MBit of external Dynamic Random
Access Memory (DRAM)
• Easy serial interface for communication with common
microcontrollers
• Software selectable shock detectors
• By-pass/power-down mode
• Kill interface for DAC deactivation
• Can be used for:
– ‘sampling’ part of a disc
– to reduce access pauses between jumps
– to deliver a programmable delay
– to generate a fixed audio rate from Constant Angular
Velocity (CAV) discs.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage
3.3
5.0
5.5
V
IDD
supply current
−
12
−
mA
fclk
clock frequency
−
16.9344
−
MHz
fi(clk)
I2S input word clock frequency
44.1
88.2
176.4
kHz
fo(clk)
I2S
44.1
88.2
176.4
kHz
Tamb
operating ambient temperature
−40
−
+85
°C
Tstg
storage temperature
−65
−
+150
°C
output word clock frequency
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
SAA7346H
PINS
PIN POSITION
MATERIAL
CODE
44
QFP(1)
plastic
SOT307-2
Note
1. When using reflow soldering it is recommended that the Dry Packing instructions in the “Quality Reference
Pocketbook” are followed. The pocketbook can be ordered using the code 9398 510 34011.
July 1994
2
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
3
4
5
2
I 2S
INPUT
1
42
to
39
19 13
I 2S
OUTPUT
DATA
MULTIPLEXER
TMS
SIDA
SILD
V DD2
23 44
32, 30, 28,
26, 25, 27,
29, 31, 33,
34
ADDRESS
MULTIPLEXER
14
16
15
READ
POINTER
6
MICROCONTROLLER
INTERFACE
17
MONITOR
CONTROLLER
SHOCK
DETECTORS
24
43
9
18
TIMING
11 12
36 37 38 35
7
10
Fig.1 Simplified SAA7347 block diagram.
3
RCD2
CLKIN
OE
WE
CAS
RAS
RSB
SSD
OTD
MGB429
VSS1 VSS2
July 1994
A0
to
A9
8
WRITE
POINTER
REGISTER
SICL
V DD1
21 20 22
SAA7346
RESET
WCO
SDO
SCLO
S_NSF
D0 to D3
CFLG
KILL
SDI
WCI
SCLI
handbook, full pagewidth
KILLOUT
BLOCK DIAGRAM
CONFIG
FILL
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
PINNING
SYMBOL
PIN
DESCRIPTION
CFLG
1
correction flag input from CD decoder
KILL
2
kill input
SCLI
3
multi-speed I2S bit clock input
WCI
4
multi-speed I2S word clock input
SDI
5
multi-speed I2S data input
CONFIG
6
external DRAM select input; HIGH 4 Mbit, LOW 1 Mbit
CLKIN
7
16.9344 MHz system clock input
TMS
8
test mode select input; active HIGH
OTD
9
on/off track detector input
RCD2
10
DRAM read cycle divide-by-2 input; active HIGH
SSD
11
shock detected output; active HIGH when shock is detected
RSB
12
rotational shock busy output; active HIGH when rotational shock is detected
S_NSF
13
synthetic new subcode frame output
RESET
14
reset enable input; active LOW
SIDA
15
microcontroller interface input/output data line
SICL
16
microcontroller interface clock input
SILD
17
microcontroller interface read/write input
FILL
18
FIFO write enable output; active HIGH
KILLOUT
19
open drain output; active LOW; when in by-pass mode KILLOUT equals KILL
SDO
20
I2S data output
SCLO
21
I2S bit clock output
WCO
22
I2S word clock output
VDD1
23
supply voltage 1
VSS1
24
supply ground 1
A4
25
DRAM address bus output 4
A3
26
DRAM address bus output 3
A5
27
DRAM address bus output 5
A2
28
DRAM address bus output 2
A6
29
DRAM address bus output 6
A1
30
DRAM address bus output 1
A7
31
DRAM address bus output 7
A0
32
DRAM address bus output 0
A8
33
DRAM address bus output 8
A9
34
DRAM address bus output 9
OE
35
DRAM enable output; active LOW
RAS
36
DRAM row address strobe output; active LOW
CAS
37
DRAM column address strobe output; active LOW
WE
38
DRAM write enable output; active LOW
July 1994
4
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
RAS
OE
A9
35
34
37 CAS
36
38 WE
39 D3
handbook, full pagewidth
40 D2
supply voltage 2
D0
supply ground 2
44
41 D1
43
VDD2
44 V DD2
VSS2
42
DRAM data bus inputs/outputs
VSS2
CFLG
1
33
A8
A0
KILL
2
32
SCLI
3
31 A7
WCI
4
30
A1
SDI
5
29
A6
CONFIG
6
28
A2
CLKIN
7
27
A5
TMS
8
26
A3
OTD
9
25
A4
RCD2 10
24
VSS1
SSD 11
23
VDD1
WCO 22
SCLO 21
SDO 20
KILLOUT 19
FILL 18
SILD 17
SICL 16
SIDA 15
RSB 12
SAA7346
RESET 14
39 to 42
DESCRIPTION
43
D3 to D0
PIN
S_NSF 13
SYMBOL
SAA7346
MGB430
Fig.2 Pin configuration.
decoder clock speed and enables the word clock to vary
from 1.1 × fs to 4 × fs (typically 2 × fs). This is a requirement
of any electronic shock absorbing system since the disc
must be rotating faster than usual to assure the FIFO is full
to absorb a shock. The falling edge of WCO indicates the
start of a new transfer. Data is exchanged over the
SDI and SDO pins. The SAA7346 is compatible with a
variety of DAC ICs.
FUNCTIONAL DESCRIPTION
I2S input/output interfaces
The SAA7346 contains an asynchronous serial input and
a serial output interface. The serial operation of the
interfaces is under hardware control of the external
circuitry and uses the I2S protocol. The output presents a
continuous clock signal SCLO (typically 2.8224 MHz)
which is divided from the system clock, and a word select
signal WCO, typically 44.1 kHz (fs), which is used to
distinguish between right and left channels. When in
by-pass mode WCO and SCLO are the same as the input
interface signals WCI and SCLI, enabling data to pass
through the SAA7346. Since the serial input port is
asynchronous the device is independent of the CD
July 1994
New subcode frame regeneration
The SAA7346 has a digital phase-locked loop (PLL)
system which decodes the F1 and F6 flags, from the first
1-bit signal generated by the CD decoder correction flag
output shown in Fig.3. The F1 flag is the absolute time
sync signal of the New Subcode Frame (NSF). It relates
5
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
the position of the subcode-sync to the audio data. This
signal determines the accuracy with which the SAA7346
sews audio data together after a shock. When the CD
decoder preforms a jump the NSF will be missed. The PLL
system will insert the missing pulse. The resulting signal is
the S_NSF which can be used as a time out for reading the
subcode from the decoder shown in Fig.4. The S_NSF is
available externally and the NSF flag can be read via the
serial microcontroller interface. The F6 flag indicates at
least one hold has occurred in the decoder’s error
corrector and interpolator. The shock processor uses this
signal to evaluate whether a shock has occurred.
11.3
µs
handbook, full pagewidth
CFLG
F1
45.4 µs
F2
F3
F4
F5
F6
F7
F1
MGA370
Fig.3 CFLG input timing diagram.
0.37 ms
handbook, full pagewidth
6.6 ms
S_NSF
NSF
MGB431
Variable
NSF is set until read
by the microcontroller
Fig.4 S_NSF output timing diagram; n = 2.
decoder is rolling out of its FIFO. RSB will be set which
sets SSD again thus the FIFO will not start refilling. The
microcontroller should jump one track back and look for
the correct target position again. When the motor speed is
stable and the decoder does not roll out of its FIFO, the
audio data will be glued together.
Shock processor
The shock processor determines whether a shock has
occurred by processing all the shock detectors. The
SAA7346 will enter shock mode and set SSD when the:
• µCsd flag is set by the microcontroller in the command
register
SSD will be reset whenever the microcontroller sets PFB
or the flush flags in the command register, or when the
FIFO empties while the echo flag is LOW. Note if the
microcontroller wants SSD to be clear for a while the shock
detectors should be inhibited.
• OTD input is active while the jmp_bz flag is not set
• RSB output is set while the e_rot_sd flag is set
• NSF pulse is lost and the full flag is not read by the
microcontroller from the status register.
When the target position has been found the
microcontroller should set the PFB flag in the command
register. The SAA7346 will respond by clearing the SSD
flag and start refilling. If CFLG still indicates a hold, the
July 1994
FIFO controller and monitor
The SAA7346 uses a state machine to control and monitor
the conditions of the FIFO shown in Fig.5.
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Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
flush + reset +
(empty and echo)
handbook, full pagewidth
flush + reset
HOLD
6
flush + reset
RESET
0
reset and sow
first nibble
FILL
1
SSD
SSD and
(NSF + S_NSF)
SSD
full
FILL
2
SSD
NSF +
S_NSF
SHOCK
7
SSD
HOLD
5
PFB
HOLD
4
PFB
first nibble
FILL
3
MGB432
Fig.5 State machine flow diagram.
During normal operation the FIFO will fill up because
writing is carried out twice as fast as reading; this is the fill
mode. If the FIFO is full the monitor will detect and set the
full flag. At the same time the fill flag will be reset thus
preventing audio data from being written in to the FIFO.
When the microcontroller reads the full flag from the status
register, the servo control should jump back one track. The
microcontroller enters a wait loop until the same absolute
time subcode frame turns by again; this is the hold mode.
When the spot is found again the microcontroller should
set the PFB flag in the command register and the
SAA7346 will resume writing to the DRAM. While in fill
mode the write pointer address is saved at the end of each
subcode frame. When the player exists hold mode it
restores the saved address and continues writing after the
last sample.
Table 1
When a shock is detected the SAA7346 will enter shock
mode. The shock mode will last until the PFB is set by the
microcontroller or the FIFO is flushed, reset or runs empty.
Microcontroller interface
The SAA7346 has a 3-line microcontroller interface which
is compatible with TDA1301, TDA1303 and SAA7345.
WRITING DATA TO THE SAA7346
The SAA7346 command register is shown in Table 1. This
can be written to via the microcontroller interface as shown
in Fig.6. The command register flags functions are shown
in Table 2.
SAA7346 microcontroller interface registers.
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Command
flush
bypass
echo
jmp_bz
otd_p
e_rot_sd
µCsd
PFB
Status
Lm
Lm1
FRM_ER
NSF
full
empty
SSD
fill
July 1994
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Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
Table 2
SAA7346
Command register flag functions.
COMMAND
DESCRIPTION
Flush
Flush, when set, will empty the FIFO, reset the read and write pointer addresses. Then writing will
resume to the FIFO. Flag reset automatically.
Bypass
Bypass, when set, will power down the SAA7346. The I2S interface passes input to output directly.
The parallel interface port controls RAS, CAS, WE and OE which are pulled HIGH. KILL passes
directly to KILLOUT. When exiting by-pass mode the FIFO is automatically flushed.
Echo
Echo, when set, will cause the FIFO contents to be continuously played until the correct position is
found again.
jmp_bz
Jump busy, when set, indicates a jump is being preformed. The OTD shock detector input will be
disabled. After the jump has finished the flag should be reset by a write.
otd_p
OTD polarity enable. Enables the polarity of the OTD input to be switched from active HIGH set,
active LOW not set.
e_rot_sd
Enable rotational shock detection, when set, will detect shocks whenever the decoder rolls out of its
internal FIFO.
µCsd
Microcontroller shock detected is set when the microcontroller has detected a shock.
PFB
Position Found Back, when set, indicates that the microcontroller has found the absolute time frame
after a shock or hold cycle. The audio data will sew together and the flag reset automatically.
handbook, full pagewidth
SICL
SILD
SIDA
B7
B6
B5
B4
B3
B2
B1
B0
MGB433
Fig.6 Microcontroller WRITE timing.
Writing operation sequence:
READING STATUS OF SAA7346
• SILD is held HIGH by the microcontroller.
The SAA7346 has a status register shown in Table 1. This
can be read via the microcontroller interface shown in
Fig.7. The internal status signals are made available on
the SIDA pin and are shown in Table 3.
• Microcontroller data is clocked into the internal
command register on the LOW-to-HIGH clock transition
of SICL.
• SILD is pulled LOW by the microcontroller to latch-in
data to the command register.
• SICL and SILD are pulled HIGH by the microcontroller
to indicate that communications have finished.
July 1994
8
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
Table 3
SAA7346
Internal status signals.
STATUS
DESCRIPTION
Lm and Lm1
The two Most Significant Bits (MSB) of the FIFO. These can be used to display the FIFO length or
correct the subcode time information. The FIFO length is shown in Table 4.
FRM_ER
Framing error flag is set when:
1. The microcontroller did not accept the previous subcode flag on time. When this occurs the NSF
flag will be set together with FRM_ER.
2. The S_NSF generated signal does not coincide with the NSF signal generated by the decoder.
When this occurs there has been a FIFO overflow in the decoder or a jump.
Framing error flag is reset when status register is read.
NSF
New subcode frame is set when an absolute sync is recovered from the CFLG input. Reset when
status register is read. If the NSF is still set at the next occurrence of a subcode frame, FRM_ER will
be set indicating that the microcontroller has lost a frame.
Full
Full is set when the FIFO is full. When the flag is set the microcontroller must jump back to the
previous track. Reset when status register is read.
Empty
Empty is set when the FIFO is emptied during hold or shock modes. DRAM writing should resume
immediately unless echo is set in the command register. If set, writing can only resume when PFB or
flush are set in the command register. The latter will cause a discontinuity in music. Note when set
there is a complete word left in the FIFO giving the SAA7346 controller time to switch to fill mode.
SSD
Set shock detect is set when SAA7346 detects a shock.
Fill
Fill is set when writing data to the DRAM or by setting the command register flags PFB or flush. Reset
internally when full or SSD are set.
Table 4
FIFO length as a function of CONFIG, Lm and Lm1.
CONFIG
Lm
Lm1
0
0
0
0.00 to 0.19
0
0
1
0.19 to 0.39
0
1
0
0.39 to 0.58
0
1
1
0.58 to 0.78
1
0
0
0.00 to 0.75
1
0
1
0.75 to 1.50
1
1
0
1.50 to 2.25
1
1
1
2.25 to 2.97
handbook, full pagewidth
FIFO LENGTH (s)
SICL
SILD
SIDA
B7
B6
B5
B4
B3
B2
B1
B0
MGB434
Fig.7 Microcontroller READ timing.
July 1994
9
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
Read operation sequence:
System clock
• SILD is held LOW by the microcontroller.
The system clock input, CLKIN, recommended input signal
is 16.9344 MHz. The accuracy of this clock influences the
accuracy of the I2S output, therefore the performance of
the DAC and hence audio quality. The system clock is
divided by 384 to derive the I2S output word clock, WCO
divided by 8 to derive the I2S output bit clock, SCLO.
Therefore whatever clock jitter the user introduces on the
CLKIN signal will be reflected in the WCO and SCLO
outputs.
• Status information is clocked from the internal status
register on the LOW-to-HIGH clock transition of SICL.
• SICL and SILD are pulled HIGH by the microcontroller
to indicate that communications have finished.
DRAM interface
The SAA7346 may be connected to all standard 80 ns,
1M × 4 bit or 256K × 4 bit fast page mode DRAMs. The
best performance can be expected with the 4 Mbit DRAM.
The CONFIG input selects the DRAM configuration either
HIGH 4 Mbit or LOW 1 Mbit format. The SAA7346
converts audio data from serial to parallel and stores it as
4 bits. The addresses for read or write actions are
calculated by separate read and write pointers which are
multiplexed onto a 4 bits address bus. The control signal
outputs associated with the parallel inputs/outputs are
shown in Table 5.
Table 5
Reset
Reset should be applied for four system clock cycles.
Reset will:
• Clear SSD
• Clear the command register but leave the bypass flag
set.
After a reset has been applied the SAA7346 will start-up in
bypass mode.
Command register flag functions.
COMMAND
Kill interface
DESCRIPTION
WE
indicates write enable action
RAS
row address strobe
CAS
column address strobe
OE
output buffer enable for external memory
during cycle.
The kill interface can be used to deactivate the DAC. The
kill input is passed directly to the KILLOUT output when the
bypass flag in the command register is set. When the flag
is not set KILLOUT is generated by the SAA7346. It is
LOW after leaving bypass mode, a reset or a FIFO flush. It
will be LOW until the first error free word is read from the
FIFO. The kill input has no effect or function when the
bypass flag is not set.
When the SAA7346 leaves bypass mode where all parallel
Port control lines are pulled HIGH, the device initiates a
DRAM power-up routine in accordance with the JEDEC
standard.
July 1994
Read cycle divide (RCD2)
The RCD2 input enables the modes of operation shown in
Table 6. When RCD2 is HIGH the DRAM-read requests
are halved allowing I2S output speeds to vary. The factor
n is called the over-speed factor.
10
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
Table 6
SAA7346
SAA7346 I2S output speeds.
I2S INPUT
SPEED
RCD2
I2S OUTPUT
SPEED
APPLICATION
LOW
CAV(1)
n=1
CAV CDROM player with standard audio speed
LOW(2)
n=1
n=1
delay line feature
LOW
n=2
n=1
shock proof CD player
LOW
n=4
n=1
high data rate CDROM/CDI player with standard audio speed
HIGH
n=2
n = 1⁄2
musicians feature
HIGH
n=4
n=
1⁄
2
musicians feature
Notes
1. CAV with n = 4 speed at outer edge of disc; n = 1.5 at inner edge of disc.
2. To build-up a delay, RCD2 should be made HIGH temporarily for twice the delay time.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
0
6.5
V
Pmax
maximum power dissipation
−
500
mW
Tstg
storage temperature
−55
+125
°C
Tamb
operating ambient temperature
−40
+85
°C
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
80
K/W
thermal resistance from junction to ambient in free air
CHARACTERISTICS
VDD = 3.3 to 5.5 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
3.3
5.0
5.5
V
IDD
supply current
VDD = 5.0 V
−
12
−
mA
IDDb
bypass supply current
VDD = 5.0 V;
bypass mode
−
4
−
mA
IDDq
quiescent supply current
−
−
100
µA
V
Digital inputs
INPUTS: WCI, SDI, CLKIN, OTD AND RCD2; NORMAL CMOS
VIL
LOW level input voltage
−0.3
−
0.3VDD
VIH
HIGH level input voltage
0.7VDD
−
VDD + 0.3 V
ILI
input leakage current
−10
−
+10
µA
CI
input capacitance
−
−
10
pF
July 1994
VI = 0 V to VDD
11
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SYMBOL
SAA7346
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
INPUT CLKIN
fclk
system clock frequency
−
16.9344 −
MHz
tH
system clock HIGH time
35
−
65
ns
tr
system clock rise time
0.8 V to (VDD − 0.8 V)
−
−
20
ns
tf
system clock fall time
(VDD − 0.8 V) to 0.8 V
−
−
20
ns
V
INPUTS: CFLG, KILL, CONFIG AND SILD; WITH PULL-UP
VIL
LOW level input voltage
−0.3
−
0.3VDD
VIH
HIGH level input voltage
0.7VDD
−
VDD + 0.3 V
RPU
input pull-up resistance
−
50
−
kΩ
CI
input capacitance
−
−
10
pF
−0.3
−
0.3VDD
V
VI = 0 V
INPUT TMS; WITH PULL-DOWN
VIL
LOW level input voltage
VIH
HIGH level input voltage
RPD
input pull-down resistance
CI
input capacitance
VI = VDD
0.7VDD
−
VDD + 0.3 V
−
50
−
kΩ
−
−
10
pF
INPUTS: RESET, SCLI AND SICL; SCHMITT-TRIGGER
Vthr
switching threshold voltage rising
−
−
0.8VDD
V
Vthf
switching threshold voltage falling
0.2VDD
−
−
V
Vhys
hysteresis voltage
−
0.33VDD −
V
CI
input capacitance
−
−
10
pF
236
−
−
ns
INPUT RESET
tRW
RESET pulse width; active LOW
Digital outputs
OUTPUTS: FILL, S_NSF, RSB AND SSD; PUSH-PULL
VOL
LOW level output voltage
IOL = 4 mA
0
−
0.4
V
VOH
HIGH level output voltage
IOL = −4 mA
VDD − 0.4
−
VDD
V
CL
load capacitance
−
−
50
pF
tr
output rise time
0.8 V to (VDD − 0.8 V); −
CL = 50 pF
−
15
ns
tf
output fall time
(VDD − 0.8 V) to 0.8 V; −
CL = 50 pF
−
15
ns
0
−
0.4
V
OUTPUTS: SDO, SCLO, WCO, WE, OE, RAS, CAS, A0 TO A9; SLEW RATE PUSH-PULL
VOL
LOW level output voltage
IOL = 4 mA
VOH
HIGH level output voltage
IOL = −4 mA
CL
load capacitance
tr
tf
July 1994
VDD − 0.4
−
VDD
V
−
−
50
pF
output rise time
0.8 V to (VDD − 0.8 V); −
CL = 50 pF
−
20
ns
output fall time
(VDD − 0.8 V) to 0.8 V; −
CL = 50 pF
−
20
ns
12
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SYMBOL
PARAMETER
SAA7346
CONDITIONS
MIN.
TYP.
MAX.
UNIT
OUTPUT KILLOUT; OPEN DRAIN
VOL
LOW level output voltage
0
−
0.4
V
IO
output current
−
−
2
mA
CL
load capacitance
−
−
50
pF
tf
output fall time
(VDD − 0.8 V) to 0.8 V; −
CL = 50 pF
−
30
ns
V
IOL = 2 mA
INPUTS/OUTPUTS: D0 TO D3; NORMAL CMOS WITH SLEW RATE CONTROLLED PUSH-PULL
VIL
LOW level input voltage
−0.3
−
0.3VDD
VIH
HIGH level input voltage
0.7VDD
−
VDD + 0.3 V
ILI
input leakage current
VI = 0 V to VDD
−10
−
+10
CI
input capacitance
−
−
10
pF
VOL
LOW level output voltage
IOL = 4 mA
0
−
0.4
V
VOH
HIGH level output voltage
IOL = −4 mA
VDD − 0.4
−
VDD
V
CL
load capacitance
−
−
50
pF
tr
output rise time
0.8 V to (VDD − 0.8 V); −
CL = 50 pF
−
20
ns
tf
output fall time
(VDD − 0.8 V) to 0.8 V; −
CL = 50 pF
−
20
ns
V
µA
INPUT/OUTPUT SIDA; NORMAL CMOS WITH PUSH-PULL
VIL
LOW level input voltage
−0.3
−
0.3VDD
VIH
HIGH level input voltage
0.7VDD
−
VDD + 0.3 V
ILI
input leakage current
−10
−
+10
µA
CI
input capacitance
−
−
10
pF
VOL
LOW level output voltage
IOL = 4 mA
0
−
0.4
V
VOH
HIGH level output voltage
IOL = −4 mA
CL
load capacitance
tr
tf
VI = 0 V to VDD
VDD − 0.4
−
VDD
V
−
−
50
pF
output rise time
0.8 V to (VDD − 0.8 V); −
CL = 50 pF
−
15
ns
output fall time
(VDD − 0.8 V) to 0.8 V; −
CL = 50 pF
−
15
ns
I2S timing
RECEIVER (SEE FIG.9)
Clock input SCLI
Tcy
tH
tL
clock cycle time
118.1(1)
236.2(2)
472.4(3)
ns
clock HIGH time
41.3(1)
−
−
ns
clock LOW time
41.3(1)
−
−
ns
Inputs: SDI and WCI
tsu
set-up time
23.6
−
−
ns
th
hold time
10
−
−
ns
July 1994
13
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SYMBOL
SAA7346
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
TRANSMITTER (SEE FIG.8)
Clock output SCLO
Tcy
clock cycle time
−
472.4(3)
944.8(4)
ns
tH
clock HIGH time
165.3
−
−
ns
tL
clock LOW time
165.3
−
−
ns
Outputs: SDO and WCO
td
delay time
−
−
377
ns
th
hold time
40
−
−
ns
180
−
−
ns
Microcontroller interface timing (see Figs 12 and 13)
INPUTS: SICL AND SILD
tH
input HIGH time
tL
input LOW time
180
−
−
ns
tr
rise time
0.8 V to (VDD − 0.8 V)
−
−
240
ns
tf
fall time
(VDD − 0.8 V) to 0.8 V
−
−
240
ns
Read mode (see Fig.12)
td
delay time SILD to SIDA valid
120
−
−
ns
tpd
propagation delay time SICL to SIDA
−
−
110
ns
Write mode (see Fig.13)
tsu1
set-up time SIDA to SICL
40
−
−
ns
th
hold time SICL to SIDA
−
−
180
ns
tsu2
set-up time SICL to SILD
180
−
−
ns
July 1994
14
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SYMBOL
PARAMETER
SAA7346
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DRAM interface timing (see Figs 14 and 15)
Tcy
read or write cycle time
160
−
−
ns
tCAC
access time from CAS
−
−
20
ns
tOAC
access time from OE
−
−
20
ns
th3
OE to data input hold time
0
−
−
ns
tRH
RAS HIGH time
70
−
−
ns
tRL
RAS LOW time
80
−
10000
ns
th1
RAS hold time
20
−
−
ns
th2
RAS hold time to OE LOW
20
−
−
ns
tCL
CAS LOW time
20
−
10000
ns
th4
CAS hold time
80
−
−
ns
tCRd
delay time from CAS HIGH to RAS
10
−
−
ns
tRCd
delay time from RAS to CAS
25
−
−
ns
tRd
RAS to column address delay time
20
−
−
ns
tsu1
row address set-up time
0
−
−
ns
tRAh
row address hold time
15
−
−
ns
tsu2
column address set-up time
0
−
−
ns
tCAh
column address hold time
20
−
−
ns
tRh
column address hold time from RAS
LOW
60
−
−
ns
tl
column address to RAS lead time
40
−
−
ns
tRCh
read command hold time
0
−
−
ns
tRRh
read command hold time to RAS
12
−
−
ns
tWsu
write command set-up time
0
−
−
ns
tWh1
write command hold time
15
−
−
ns
tWL
write command LOW time
15
−
−
ns
tWh2
write command hold time from RAS
60
−
−
ns
tWCl
write command to CAS lead time
20
−
−
ns
tWRl
write command to RAS lead time
20
−
−
ns
tDsu
data output set-up time
0
−
−
ns
tDh
data output hold time
15
−
−
ns
tDRh
data output hold time from RAS
60
−
−
ns
Notes
1. n = 4.
2. n = 2.
3. n = 1.
4. n = 1⁄2.
July 1994
15
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
Tcy
handbook, full pagewidth
tH
tL
V DD – 0.8 V
SCLI
0.8 V
th
t su
V DD – 0.8 V
SDI
WCI
0.8 V
MGB436
Fig.8 I2S input timing.
Tcy
handbook, full pagewidth
tH
tL
V DD – 0.8 V
SCLO
0.8 V
th
td
V DD – 0.8 V
SDO
WCO
0.8 V
MGB435
Fig.9 I2S output timing.
handbook, full pagewidth
SCLI
4.2336 MHz
WCI
LEFT CHANNEL
RIGHT CHANNEL
88.2 kHz
5.67 µ s
SDI
MGB437
MSB
LSB
MSB
LSB
Fig.10 Typical I2S data input waveform; f = 4.2 MHz; n = 2.
July 1994
16
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
handbook, full pagewidth
SCLO
2.1168 MHz
WCO
LEFT CHANNEL
RIGHT CHANNEL
44.1 kHz
11.34 µs
SDO
MGB438
LSB
MSB
MSB
LSB
Fig.11 Typical I2S data output waveform; f = 2.1 MHz; n = 1.
tf
tr
handbook, full pagewidth
V DD – 0.8 V
SILD
0.8 V
td
tr
tf
tH
V
DD
– 0.8 V
SICL
0.8 V
tL
t pd
V DD – 0.8 V
SIDA
0.8 V
MGB439
Fig.12 Microcontroller timing; READ mode.
July 1994
17
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
tf
handbook, full pagewidth
tL
tr
V DD – 0.8 V
SILD
0.8 V
tf
tr
tH
t su2
V DD – 0.8 V
SICL
0.8 V
tL
t su1
th
V DD – 0.8 V
SIDA
0.8 V
MGB440
Fig.13 Microcontroller timing; WRITE mode.
July 1994
18
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t RH
t Rh
VDD – 0.8V
RAS
0.8 V
t h4
t CRd
t RCd
t h1
t CRd
t CL
VDD – 0.8V
CAS
0.8 V
tl
t Rd
t su1
A0
to
A9
t CAh
t RAh
t su2
VDD – 0.8V
ROW
COLUMN
0.8 V
Philips Semiconductors
Shock absorbing RAM addresser
July 1994
Tcy
t RL
t RCh
19
t RRh
VDD – 0.8V
WE
0.8 V
t h2
t OAC
OE
t CAC
t h3
handbook, full pagewidth
0.8 V
MGB441
SAA7346
Fig.14 READ cycle timing.
INPUT
Preliminary specification
VDD – 0.8V
D0 to D3
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
Tcy
handbook, full pagewidth
t RL
t RH
t Rh
V
– 0.8V
DD
RAS
0.8 V
t h4
t CRd
t RCd
t h1
t CRd
t CL
VDD – 0.8V
CAS
0.8 V
t Rl
t Rd
t CAh
t RAh
t su1
t su2
VDD – 0.8V
A0
to
A9
ROW
COLUMN
0.8 V
t Wsu
t Wh1
t WL
V DD – 0.8V
WE
0.8 V
t Wh2
t RWI
t WCI
VDD – 0.8V
OE
t DRh
t Dh
t Dsu
VDD – 0.8V
D0 to D3
OUTPUT
0.8 V
MGB442
Fig.15 WRITE cycle timing.
July 1994
20
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
APPLICATION INFORMATION
handbook, full pagewidth
1 M x 4 bit
DRAM
VDD
D3 to D0 WE CAS RAS OE
100 nF
39
to
42
44 43
CFLG
KILL
38 37
36 35
1
2
3
I 2S bus from
CD decoder
5V
16.9 MHz
CLKIN
OTD
RCD2
SSD
A9 to A0
25 to 34
4
5
6
SAA7346
7
8
9
10
24
11
23
VDD
12 13 14 15 16 17 18 19 20 21 22
microcontroller
interface
S_NSF
RSB
RESET
5V
10
kΩ
I 2S bus
to DAC
KILLOUT
Fig.16 SAA7346 application diagram.
July 1994
21
100 nF
MGB443
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
PACKAGE OUTLINE
handbook, full pagewidth
seating
plane
S
0.1 S
12.9
12.3
44
1.2
(4x)
0.8
34
B
33
1
pin 1 index
0.15 M B
0.8
11
23
12
10.1
9.9
12.9
12.3
0.40
0.20
22
0.8
0.40
0.20
1.2
(4x)
0.8
0.15 M A
10.1
9.9
X
A
0.85
0.75
1.85
1.65
0.25
0.14
0.25
0.05
MBB944 - 2
detail X
0.95
0.55
2.10
1.70
0 to 10 o
Dimensions in mm.
Fig.17 Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm; (SOT307-2; QFP44).
July 1994
22
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
SOLDERING
Plastic quad flat-packs
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
BY WAVE
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
July 1994
23
Philips Semiconductors – a worldwide company
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SCD31
© Philips Electronics N.V. 1994
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Document order number:
Date of release: July 1994
9397 736 30011