PCKEL14 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip Rev. 01 — 14 October 2002 Product data 1. Description The PCKEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL, or if positive power supplies are used, PECL input signal. The PCKEL14 is designed to operate in ECL or PECL mode for a voltage supply range of −2.375 V to −3.8 V (or 2.375 V to 3.8 V). The PCKEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor), the SEL pin will select the differential clock input. The common enable (EN) is synchronous, so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled, as can happen with an asynchronous control. The internal flip-flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. The VBB pin (an internally generated voltage supply) is available to this device only. For single-ended conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC-coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.1 mA. When not used, VBB should be left open. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 50 ps output-to-output skew at 3.3 V Synchronous enable/disable Multiplexed clock input ESD protection: > 2.5 kV HBM The PCK series contains temperature compensation PECL mode operating range: VCC = 2.375 V to 3.8 V, with VEE = 0 V NECL mode operating range: VCC = 0 V, with VEE = −2.375 V to −3.8 V Internal 75 kΩ pull-down resistors on all inputs, plus a 37.5 kΩ pull-up on CLK Q output will default LOW with inputs open or at VEE Meets or exceeds JEDEC spec EIA/JESD78 IC latch-up test Moisture sensitivity level 1 Flammability rating: UL-94 code V-0 @ 1/8” PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 3. Pinning information 3.1 Pinning 20 VCC Q0 1 20 VCC Q0 2 19 EN Q0 2 19 EN Q1 3 18 VCC Q1 3 18 VCC Q1 4 17 NC Q1 4 17 NC Q2 5 16 SCLK Q2 5 Q2 6 15 CLK Q2 6 Q3 7 14 CLK Q3 7 Q3 8 13 VBB Q3 8 13 VBB Q4 9 12 SEL Q4 9 12 SEL Q4 10 11 VEE Q4 10 11 VEE 002aaa217 PCKEL14PW 1 PCKEL14D Q0 16 SCLK 15 CLK 14 CLK 002aaa353 Fig 1. SO20 pin configuration. Fig 2. TSSOP pin configuration. 3.2 Pin description Table 1: Symbol 3.2.1 Pin description Pin Description Q0-Q4 1, 3, 5, 7, 9 ECL differential clock outputs, non-inverted Q0-Q4 2, 4, 6, 8, 10 ECL differential clock outputs, inverted VEE 11 negative supply voltage SEL 12 ECL clock select input VBB 13 reference voltage output CLK 14 ECL differential clock input, inverted CLK 15 ECL differential clock input, non-inverted SCLK 16 ECL scan clock input NC 17 no connect EN 19 ECL synchronous enable, Active-LOW VCC 18, 20 positive supply voltage Power supply connection CAUTION All VCC and VEE pins must be connected to an appropriate power supply to guarantee proper operation. MSC895 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 2 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 4. Ordering information Table 2: Ordering information Type number Package Name Description Version PCKEL14D SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 PCKEL14PW TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 5. Logic diagram Q0 Q0 Q1 Q1 Q2 Q2 1 19 2 EN 3 4 Q 5 D 16 6 15 SCLK CLK 1 Q3 Q3 Q4 Q4 7 14 0 8 13 9 12 CLK VBB SEL 10 002aaa218 Fig 3. Logic diagram. CAUTION All VCC and VEE pins must be connected to an appropriate power supply to guarantee proper operation. MSC895 6. Function table Table 3: Function table X = Don’t care. CLK SCLK SEL EN Q L X L L L H X L L H X L H L L X H H L H X X X H L[1] [1] On next negative transition of CLK or SCLK. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 3 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 7. Limiting values Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCC power supply PECL mode; VEE = 0 V 0 4.1 V VEE power supply NECL mode; VCC = 0 V 0 −4.1 V VI input voltage PECL mode; VEE = 0 V; VI ≤ VCC 0 4.1 V NECL mode; VCC = 0 V; VI ≥ VEE 0 −4.1 V continuous - 50 mA surge - 100 mA Io output current IBB VBB sink/source −0.1 +0.1 mA Tamb ambient temperature −40 +85 °C Tstg storage temperature −65 +150 °C Rth(j-a) thermal resistance from junction to ambient 0 LFPM - 90 °C/W 500 LFPM - 60 °C/W Rth(j-c) thermal resistance from junction to case std bd 30 35 °C/W Tsld soldering temperature < 2 to 3 sec @ 248 °C - 265 °C ESDHBM electrostatic discharge Human Body Model; 1.5 kΩ; 100 pF - >2.50 kV ESDMM electrostatic discharge Machine Model; 0 kΩ; 200 pF - >100 V ESCCDM electrostatic discharge Charge Device Model - >1000 V [1] Maximum ratings are those values beyond which device damage may occur. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 4 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 8. Static characteristics Table 5: PECL DC characteristics[1] VCC = 2.5 V; VEE = 0 V [2] Symbol Parameter Tamb = −40 °C Conditions Min - Typ Max VOL LOW-level output voltage [3] 670 VIH HIGH-level input voltage single-ended [4] 1310 - 1620 1335 - 1620 1335 - 1620 mV VIL LOW-level input voltage single-ended [4] 690 - 1025 690 - 1025 690 - 1025 mV VBB output voltage reference 1.07 - 1.25 1.15 - 1.25 1.15 - 1.31 V VIHCMR HIGH-level input voltage, common mode range (differential) 1.2 - 2.1 1.2 - 2.1 1.2 - 2.1 V IIH HIGH-level input current - - 150 - - 150 - - 150 µA IIL LOW-level input current CLK 0.5 - - 0.5 - - 0.5 - - µA −300 - - −300 - - −300 - - µA CLK [1] [2] [3] [4] [5] 690 31 Max 1325 1460 1620 1435 1545 1620 1475 1545 1620 mV 880 - Typ [3] 795 40 Min HIGH-level output voltage 690 30 Max power supply current 945 - Typ Unit IEE 805 40 Min Tamb = +85 °C VOH [5] 28 Tamb = +25 °C 795 42 880 mA mV Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V. All loading with 50 Ω to VCC − 2 V. Do not use VBB at VCC < 3.0 V. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 5 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip Table 6: Positive DC characteristics[1] VCC = 3.3 V; VEE = 0 V [2] Symbol Parameter IEE power supply current Tamb = −40 °C Conditions Min - Typ 32 Tamb = +25 °C Max 40 Min - Typ 32 Tamb = +85 °C Max 40 Min - Typ 34 Unit Max 42 mA VOH HIGH-level output voltage [3] VOL LOW-level output voltage [3] VIH HIGH-level input voltage single-ended 2110 - 2420 2135 - 2420 2135 - 2420 mV VIL LOW-level input voltage single-ended 1490 - 1825 1490 - 1825 1490 - 1825 mV VBB output voltage reference 1.87 - 2.05 1.95 - 2.05 1.95 - 2.11 V VIHCMR HIGH-level input voltage, common mode range (differential) 1.3 - 2.9 1.2 - 2.9 1.2 - 2.9 V 1.5 - 2.9 1.4 - 2.9 1.4 - 2.9 V - - 150 - - 150 - - 150 µA IIH HIGH-level input current IIL LOW-level input current [1] [2] [3] [4] Vp-p < 500 mV Vp-p ≥ 500 mV [4] 2125 2260 2420 2235 2345 2420 2275 2345 2420 mV 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV CLK −300 - - −300 - - −300 - - µA others 0.5 - 0.5 - 0.5 - µA - - - Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. Outputs are terminated through a 50 Ω resistor to VCC − 2V. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between Vp-p(min) and 1 V. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 6 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip Table 7: Negative DC characteristics[1] VCC = 0.0 V; VEE = − 3.8 V to −2.375 V[2] Symbol Parameter Tamb = −40 °C Conditions Min Typ Max Min Min Typ −1175 −1040 −880 VOL LOW-level output voltage [3] −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH HIGH-level input single-ended voltage −1190 - −880 VIL LOW-level input voltage −1810 - −1475 −1810 - −1475 −1810 - −1475 mV VBB output voltage reference −1.43 - −1.25 −1.35 - −1.25 −1.35 - −1.19 V VIHCMR HIGH-level input Vp-p < 500 mV voltage, Vp-p ≥ 500 mV common mode range (differential) −2.0 - −0.4 −2.1 - −0.4 −2.1 - −0.4 V −1.8 - −0.4 −1.9 - −0.4 −1.9 - −0.4 V - - 150 - - 150 - - 150 µA CLK −300 - - −300 - - −300 - - µA others 0.5 - - 0.5 - - 0.5 - - µA LOW-level input current [1] [2] [3] [4] −1065 −955 −1165 - 40 - −880 −1025 −955 −880 34 Max [3] IIL 32 Max HIGH-level output voltage HIGH-level input current - Typ VOH [4] 40 Unit power supply current single-ended 32 Tamb = +85 °C IEE IIH - Tamb = +25 °C −1165 - 42 mA −880 mV −880 mV Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. Outputs are terminated through a 50 Ω resistor to VCC − 2 V. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between Vp-p(min) and 1 V. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 7 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 9. Dynamic characteristics Table 8: AC characteristics (VCC = 2.375 V to 3.8 V; VEE = 0 V) or (VCC = 0 V; VEE = −2.375 V to −3.8 V) [1] Symbol Parameter Tamb = −40 °C Conditions Tamb = +25 °C Tamb = +85 °C Min Typ Max Min Typ Max Min Typ Max - >1 - - >1 - - >1 - Unit fmax maximum toggle frequency see Figure 4 tPLH LOW-to-HIGH propagation delay CLK to Q (diff); 3.3 V 400 - 720 450 - 780 475 - 830 ps CLK to Q (diff); 2.5 V 400 - 800 450 - 940 500 - 970 ps HIGH-to-LOW propagation delay CLK to Q (SE) 330 - 770 350 680 830 370 - 880 ps SCLK to Q 330 - 770 350 680 830 370 - 880 ps skew time part-to-part tPHL tSKEW GHz - - 200 - - 200 - - 200 ps within-device; 3.3 V [2] - - 50 - - 50 - - 50 ps within-device; 2.5 V [2] - - 70 - - 70 - - 70 ps tJITTER cycle-to cycle jitter - 0.2 <1 - 0.2 <1 - 0.2 <1 ps tsu EN set-up time 0 - - 0 - - 0 - - ps th EN hold time 0 - - 0 - - 0 - - ps 150 - 1000 150 - 1000 150 - 1000 mV Q pins (20% - 80%); 3.3 V 230 - 500 230 - 500 230 - 500 ps Q pins (20% - 80%); 2.5 V 230 - 600 230 - 600 230 - 625 ps Vi(p-p) input swing CLK tr/tf output rise/fall times [1] [2] [3] [3] VEE can vary ±0.3 V. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions. Vi(p-p)(min) is minimum input swing for which AC parameters are guaranteed. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 8 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 002aaa219 900 VO (mVp-p) Vi(p-p)@150 mV Vi(p-p)@1000 mV 800 700 600 500 400 300 200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 40 100 FREQUENCY (MHz) Fig 4. fmax @ 150 mV and 1000 mV input. 10. Application information Q D DRIVER DEVICE RECEIVER DEVICE Q D 50 Ω 50 Ω VTT 002aaa220 VTT = VCC − 2.0 V. Fig 5. Typical termination for output driver and device evaluation. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 9 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 11. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 Fig 6. SO20 package outline (SOT163-1). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 10 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-153 Fig 7. TSSOP20 package outline (SOT360-1). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 11 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 12. Soldering 12.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 12.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C small/thin packages. 12.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 12 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 12.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 12.5 Package related soldering information Table 9: Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] Soldering method Reflow[2] Wave BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[3] suitable PLCC[4], SO, SOJ suitable suitable recommended[4][5] LQFP, QFP, TQFP not SSOP, TSSOP, VSO not recommended[6] [1] [2] [3] [4] [5] [6] suitable suitable For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 13. Revision history Table 10: Revision history Rev Date 01 20021014 CPCN Description - Product data; initial version (9397 750 09564). Engineering Change Notice 853-2372 2877 (date: 20020909). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Product data Rev. 01 — 14 October 2002 13 of 15 PCKEL14 Philips Semiconductors 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip 14. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 15. Definitions 16. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09564 Rev. 01 — 14 October 2002 14 of 15 Philips Semiconductors PCKEL14 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip Contents 1 2 3 3.1 3.2 3.2.1 4 5 6 7 8 9 10 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 16 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power supply connection . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 12 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 13 Package related soldering information . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 © Koninklijke Philips Electronics N.V. 2002. Printed in the U.S.A All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 October 2002 Document order number: 9397 750 09564