INTEGRATED CIRCUITS 74LVC169 Presettable synchronous 4-bit up/down binary counter specification Supersedes data of 1996 Aug 23 IC24 Data Handbook 1998 May 20 Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter 74LVC169 The 74LVC169 is a synchronous presettable binary counter which features an internal lookahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for PE are met). FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Synchronous counting and loading • Up/down counting • Modular 16 binary counter • Two count enable inputs for n-bit cascading • Built-in lookahead carry capability • Presettable for programmable operation • Positive-edge triggered clock This action occurs regardless of the levels at CP, PE, CET and CEP inputs This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The lookahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: DESCRIPTION The 74LVC169 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. 1 fmax = _______________________________ tp(max) (CP to TC) + tSU (CEP to CP) QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; TR = TF 2.5ns PARAMETER SYMBOL CONDITIONS Propagation delay CP to Qn CP to TC CET to TC tPHL/tPLH fMAX TYPICAL CL = 50 pF VCC = 3.3V 5.0 6.5 5.3 maximum clock frequency CI input capacitance CPD power dissipation capacitance per gate notes 1 and 2 UNIT ns 200 MHz 5.0 pF 42 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD x VCC2 x fi +Σ (CL x VCC2 x fo ) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL x VCC2 x fo ) = sum of the outputs 2. The condition is V1 = GND to VCC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 16-Pin Plastic SO –40°C to +85°C 74LVC169 D 74LVC169 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +85°C 74LVC169 DB 74LVC169 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC169 PW 74LVC169PW DH SOT403-1 1998 May 20 2 853-1866 19421 Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter PIN CONFIGURATION 74LVC169 PIN DESCRIPTION U/D 1 16 VCC CP 2 15 TC D0 3 14 Q0 D1 4 13 Q1 D2 5 12 Q2 D3 6 11 Q3 CEP 7 10 CET GND 8 9 PE PIN NUMBER SYMBOL FUNCTION 1 U/D up/down control input 2 CP clock input (LOW-to-HIGH, edge-triggered) 3,4,5,6 D0 to D3 7 CEP count enable inputs (active LOW) 8 GND ground (0V) 9 PE 10 CET 14,13,12,11 Q0 to Q3 15 TC terminal count output (active LOW) 16 VCC positive supply voltage data inputs parallel enable input (active LOW) SF00766 LOGIC SYMBOL 9 PE 1 U/D 2 CP 3 4 5 6 D0 D1 D2 D3 count enable carry input (active LOW) flip-flop outputs LOGIC SYMBOL (IEEE/IEC) CTR DIV 16 7 CEP 10 CET TC 15 9 M1 [LOAD] M2 [COUNT] Q0 Q1 Q2 1 Q3 M3 [UP] M4 [DOWN] 10 14 13 12 7 11 2 VCC = Pin 16 GND = Pin 8 G5 3, 5 CT=15 G6 4, 5 CT=0 15 2, 3, 5, 6+/C7 2, 4, 5, 6– SF00786 3 4 5 6 1, 7D [1] [2] [4] [8] 14 13 12 11 SF00787 1998 May 20 3 Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter STATE DIAGRAM 74LVC169 TYPICAL TIMING SEQUENCE 0 1 2 3 4 MR PE 15 5 D0 D1 14 6 13 7 D2 D3 CP 12 11 10 9 CEP 8 CET COUNT DOWN Q0 COUNT UP SF00788 Q1 Q2 Q3 FUNCTION TABLE TC INPUTS 12 OUTPUTS OPERATING MODES CP U/D CEP CET PE Dn Qn TC Parallel load (Dn→Qn) ↑ X X X l l L * ↑ X X X X X H * Count Up (increment) ↑ h l l h X Count Up * Count Down (decrement) ↑ l l l h X Count Down * Hold (do nothing) ↑ X h X h X qn * ↑ X X X h X qn H 14 15 0 COUNT 1 2 INHIBIT SY00069 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one, and two; inhibit H = High voltage level steady state h = High voltage level one setup time prior to the Low-to-High clock transition L = Low voltage level steady state l = Low voltage level one setup time prior to the Low-to-High clock transition q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition * = The TC is Low when CET is Low and the counter is at Terminal Count. Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL). 1998 May 20 13 RESET PRESET 4 Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter 74LVC169 LOGIC DIAGRAM 3 D D0 Q CP Q D1 4 D D 5 PE D 6 Q1 12 Q2 Q CP Q 9 13 Q CP Q D3 Q0 Q CP Q D2 14 11 Q3 7 CEP 10 CET CP U/D 2 1 15 VCC = Pin 16 GND = Pin 8 1998 May 20 TC SF00789 5 Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter 74LVC169 APPLICATION CP U/D PE D0 D1 D2 D3 D0 D1 D2 D3 PE D0 D1 D2 D3 PE PE PE U/D U/D U/D U/D CP CP CP CP TC CEP CET Q0 Q1 Q2 TC CEP CET Q3 Q0 Q1 Q2 TC CEP CET Q3 Q0 Q1 Q2 D1 D0 D2 D3 TC CEP CET Q3 Q0 LEAST SIGNIFICANT 4-BIT COUNTER Q1 Q2 Q3 MOST SIGNIFICANT 4-BIT COUNTER SF00790 Synchronous multistage counting scheme RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS LIMITS MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 UNIT V VI DC input voltage range 0 5.5 VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V Tamb Operating free-air temperature range tr, tf Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V V ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC PARAMETER CONDITIONS DC supply voltage RATING UNIT –0.5 to +6.5 V mA IIK DC input diode current VI 0 –50 –0.5 to +5.5 V 50 mA –0.5 to VCC +0.5 V VI DC input voltage Note 2 IOK DC output diode current VO VCC or VO 0 VO DC output voltage Note 2 IO DC output source or sink current VO = 0 to VCC IGND, ICC Tstg PTOT DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) 50 mA 100 mA –65 to +150 °C above +70°C derate linearly with 8 mW/K 500 above +60°C derate linearly with 5.5 mW/K 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 May 20 6 Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter 74LVC169 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 TYP1 V VCC = 1.2V GND V VCC = 2.7 to 3.6V HIGH level output voltage 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC0.2 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC1.0 VCC VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100µA II ∆ICC Input leakage current VCC = 3 3.6V; 6V; VI = 5 5.5V 5V or GND Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 1998 May 20 7 V 0.40 GND VCC = 3.0V; VI = VIH or VIL; IO = 24mA ICC UNIT MAX 0.20 V 0.55 0 1 0.1 5 µA 0.1 10 µA 5 500 µA Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter 74LVC169 AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 500; Tamb = –40C to +85C LIMITS SYMBOL tPHL/tPLH tPHL/tPLH tPHL/tPLH tPHL/tPLH tW tsu tsu PARAMETER propagation delay CP to Qn propagation delay CP to TC propagation delay CET to TC propagation delay U/D to TC clock pulse width HIGH or LOW set-up time Dn to CP set-up time PE tsu tsu to CP set-up time U/D to CP set-up time CEP, CET to CP VCC = 3.3V ±0.3V WAVEFORM VCC = 2.7V VCC = 1.2V UNIT MIN. TYP1 MAX. MIN. MAX. TYP 1 - 5.0 8.5 - 9.5 24 ns 1 - 6.5 10.8 - 12.8 30 ns 2 - 5.3 8.7 - 9.7 19 ns 4 - 5.7 9.5 - 10.5 24 ns 1 4.0 1.2 - 5.0 - - ns 3 2.5 1.0 - 3.0 - - ns 3 3.0 1.2 - 3.5 - - ns 5 5.5 2.8 - 6.5 - - ns 5 4.5 2.1 - 5.5 - - ns 3 and 5 0 2.5 - 0 - - ns 1 125 200 - 110 - - MHz hold time th fmax Dn, PE, CEP, CET, U/D to CP maximum clock pulse frequency NOTE: 1. These typical values are measured at VCC = 3.3V and Tamb = 25°C. 1998 May 20 8 Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter 74LVC169 AC WAVEFORMS VM = 1.5 V at VCC 2.7 V VM = 0.5 S VCC at VCC < 2.7 V VOL and VOH are the typical output voltage drop that occur with the output load. VI 1/fMAX PE INPUT GND VI CP INPUT GND VOH VM tSU VM CP INPUT tPLH tw tPHL tSU th VI th VM GND tSU VM Qn, TC OUTPUT VOL VI Dn INPUT tSU th th VM GND SY00071 The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform 1. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock frequency. SC00137 Waveform 4. Setup and hold times for the input (Dn) and parallel enable input (PE). VI CET VM VM tPHL CEP, CET INPUT GND tPLH VM tsu TC VM VM tsu th th VI VM CP INPUT SF00792 VM GND Waveform 2. Input (CET) to output (TC) propagation delays and output transition times. NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SC00138 Waveform 5. U/D VM VM tPHL TC CEP and CET setup and hold times. TEST CIRCUIT tPLH VM VM S1 VCC SF00793 2 * VCC Open GND 500Ω Waveform 3. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master reset to clock (CP) removal times. VO VI PULSE GENERATOR D.U.T. 50pF RT CL 500Ω SWITCH POSITION TEST tPLH/tPHL S1 Open VCC VI < 2.7V VCC 2.7–3.6V 2.7V SV00903 Waveform 6. 1998 May 20 9 Load circuitry for switching times. Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter SO16: plastic small outline package; 16 leads; body width 3.9 mm 1998 May 20 10 74LVC169 SOT109-1 Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1998 May 20 11 74LVC169 SOT338-1 Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 1998 May 20 12 74LVC169 SOT403-1 Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter NOTES 1998 May 20 13 74LVC169 Philips Semiconductors Product specification Presettable synchronous 4-bit up/down binary counter 74LVC169 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04498