INTEGRATED CIRCUITS DATA SHEET TDA1313; TDA1313T Stereo continuous calibration DAC (CC-DAC) Objective specification File under Integrated Circuits, IC01 July 1993 Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T FEATURES GENERAL DESCRIPTION • 4/8 × oversampling (multiplexed/simultaneous input) possible The TDA1313; 1313T is a voltage driven digital-to-analog converter, and is of a new generation of DACs which incorporates the innovative technique of Continuous Calibration (CC). The largest bit-currents are repeatedly generated from one single current reference source. This duplication is based upon an internal charge storage principle having an accuracy which is insensitive to ageing, temperature and process variations. • Voltage output (capable of driving headphone) • Space saving package (SO16 or DIL16) • Low power consumption • Wide dynamic range (16-bit resolution) • Continuous Calibration concept The TDA1313; 1313T is fabricated in a 1.0 µm CMOS process and features an extremely low power dissipation, small package size and easy application. Furthermore, the accuracy of the intrinsic high coarse-current combined with the implemented symmetrical offset decoding method preclude zero-crossing distortion and ensures high quality audio reproduction. Therefore, the CC-DAC is eminently suitable for use in (portable) digital audio equipment. • Easy application: – single 3 to 5.5 V supply rail – output voltage is proportional to the supply voltage – integrated current-to-voltage converter • Internal bias current ensures maximum dynamic range • Wide operating temperature range (−40 °C to +85 °C) • Compatible with most current Japanese input format multiplexed/simultaneous, two's complement and CMOS) • No zero crossing distortion • Cost efficient • High signal-to-noise ratio • Low total harmonic distortion. ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS PIN POSITION CODE 16 DIL plastic SOT38GG TDA1313T(2) 16 SO16 plastic SOT109AG Notes 1. SOT38-1; 1996 August 15. 2. SOT109-1; 1996 August 15. July 1993 MATERIAL TDA1313(1) 2 Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD supply voltage 3.0 5.0 5.5 V IDD supply current VDD = 5 V; at code 0000H − 8 9.5 mA VFS full scale output voltage VDD = 5 V 3.8 4.2 4.6 V (THD+N)/S total harmonic distortion plus noise at 0 dB signal level − −88 −81 dB − 0.004 0.009 % at 0 dB signal level; see Fig.8 − −70 − dB − 0.03 − % at −60 dB signal level − −36 −28 dB − 1.6 4.0 % at −60 dB; A-weighted − −38 − dB − 1.3 − % 93 98 − dB S/N signal-to-noise ratio at bipolar zero tCS current setting time to ±1LSB − 0.2 − µs BR input bit rate at data input − − 18.4 Mbits/s fBCK clock frequency at clock input − − 18.4 MHz TCFS full scale temperature coefficient at analog outputs (VOL; VOR) − 400 − ppm Tamb operating ambient temperature −40 − +85 °C Ptot total power dissipation VDD = 5 V; at code 0000H − 40 53 mW VDD = 3 V; at code 0000H − 15 − mW July 1993 A-weighted at code 0000H 3 July 1993 4 WS SI/LSI LRSEL/RSI 15 2 1 16 3 LOUT 9 4/8FSSEL BCK VOL C1 1 nF LIN 10 VREF OP1 4 kΩ R1 5 6 VDDO Fig.1 Block diagram. 100 nF VSSO 100 nF VDDD C4 C3 14 1 CALIBRATED SPARE SOURCE 1 CALIBRATED SPARE SOURCE TDA1313 TDA1313T 32 (5-BIT) CALIBRATED CURRENT SOURCES handbook, full pagewidth 32 (5-BIT) CALIBRATED CURRENT SOURCES VSSA 12 100 nF C5 REFERENCE SOURCE 11-BIT PASSIVE DIVIDER RIGHT BIT SWITCHES RIGHT OUTPUT REGISTER RIGHT INPUT REGISTER VDDA 11 VREF OP2 4 kΩ R2 MGE230 4 8 VREF ROUT 7 RIN C6 1 µF VOR C2 1 nF Stereo continuous calibration DAC (CC-DAC) VSSD 13 CONTROL AND TIMING 11-BIT PASSIVE DIVIDER LEFT BIT SWITCHES LEFT OUTPUT REGISTER LEFT INPUT REGISTER Philips Semiconductors Objective specification TDA1313; TDA1313T Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T PINNING SYMBOL PIN DESCRIPTION LRSEL/RSI 1 left/right select; right serial input SI/LSI 2 serial input; left serial input 4/8FSSEL 3 4/8 oversampling select VREF 4 reference voltage output VSSO 5 VDDO handbook, halfpage LRSEL/RSI 1 16 BCK operational amplifier ground SI/LSI 2 15 WS 6 operational amplifier supply voltage 4/8FSSEL 3 14 VDDD VREF 4 RIN 7 right analog input 8 right analog output VSSO 5 ROUT LOUT 9 left analog output VDDO 6 11 VDDA LIN 10 left analog input RIN 7 10 LIN VDDA 11 analog supply voltage ROUT 8 9 LOUT VSSA 12 analog ground VSSD 13 digital ground VDDD 14 digital supply voltage WS 15 word select BCK 16 bit clock input MGE229 Fig.2 Pin configuration. converter operation. The output of one calibrated source is connected to an 11-bit binary current devider which consists of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed by switching only the LSB currents. FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value IREF, the switch S1 is opened and S2 is switched to the other position (Fig.3b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to IREF and this exact duplicate of IREF is now available at the IO terminal. The TDA1313; T (CC-DAC) accepts serial input data format of 16 bit word length. The most significant bit (bit 1) must always be first. The timing is illustrated in Fig.4 and the input data formats are illustrated in Figs 5 and 6. Data is placed in the right and left input registers (Fig.1). The data in the input registers is simultaneously latched to the output registers which control the bit switches. VREF and VFS are proportional to VDD. Where: VDD1/VDD2 = VFS1/V = VREF1/VREF2 In the TDA1313; 1313T, 32 current sources and one spare current source are continuously calibrated (see Fig.1). The spare current source is included to allow continuous July 1993 13 VSSD TDA1313 TDA1313T 12 V SSA 5 Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T IO handbook, halfpage IO IREF IREF IREF S2 S2 S1 S1 + Cgs M1 M1 + Cgs Vgs (a) Vgs (b) MGE231 Fig.3 Calibration principle; (a) calibration (b) operation. Table 1 Mode application 4/8FSSEL LRSEL/RSI MODE FIGURE 0 1 4FS/left = HIGH 6 0 0 4FS/left = LOW 6 1 data right 8FS 5 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage − 6.0 V TXTAL maximum crystal temperature − +150 °C Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −40 +85 °C VES electrostatic handling note 1 −2000 +2000 V note 2 −200 +200 V Notes 1. Human body model: C = 100 pF; R = 1500 Ω; 3 zaps positive and negative. 2. Machine model: C = 200 pF; L = 0.5 µH; R = 10 Ω; 3 zaps positive and negative. THERMAL RESISTANCE SYMBOL Rth j-a July 1993 PARAMETER THERMAL RESISTANCE from junction to ambient in free air DIL16 75 K/W SO16 120 K/W 6 Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T CHARACTERISTICS VDDD = VDDA = VDDO = 5 V; Tamb = 25 °C; measured in Fig.7; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage 3.0 5.0 5.5 V IDD total supply current at code 0000H − 8.0 9.5 mA IDDD digital supply current at code 0000H; no clock running − 0.2 − mA IDDA analog supply current − 4.6 5.5 mA IDDO operational amplifier supply − 3.4 4 mA − 30 − dB current PSRR power supply ripple rejection at code 0000H; note 1 Digital inputs; pins WS, BCK, 4/8FSSEL, LRSEL/RSI and SI/LSI IIL input leakage current LOW VI = 0.V − − 10 µA IIH input leakage current HIGH VI = 5.5 V − − 10 µA fBCK clock frequency − − 18.4 MHz BR bit rate data input − − 18.4 Mbits/s fWS word select input frequency − − 384 kHz − − 12 ns Timing (see Fig.4) tr rise time tf fall time − − 12 ns tCY bit clock cycle time 54 − − ns tBCKH bit clock pulse width HIGH 15 − − ns tBCKL bit clock pulse width LOW 15 − − ns tSU;DAT data set-up time 12 − − ns tHD:DAT data hold time to bit clock 10 − − ns tHD:WS word select hold time 10 − − ns tSU;WS word select set-up time 12 − − ns July 1993 7 Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) SYMBOL PARAMETER TDA1313; TDA1313T CONDITIONS MIN. TYP. MAX. UNIT Analog outputs; pins VOL and VOR VFS full-scale voltage 3.8 4.2 4.6 V TCFS full-scale temperature coefficient − ±400 − ppm RL load resistance 3 − − kΩ CL load capacitance − − 200 pF VREF reference output voltage 3.16 3.33 3.5 V VDC output DC voltage 2.25 2.5 2.75 V (THD+N)/S total harmonic distortion plus noise − −88 −81 dB at 0 dB signal level; note 2 − 0.004 0.009 % at 0 dB signal level; see − −70 − dB Fig.8 − 0.03 − % at −60 dB signal level; note 2 − −36 −28 dB − 1.6 4.0 % − −38 − dB − 1.3 − % − −84 −70 dB − 0.006 0.03 % − 0.2 − µs at −60 dB signal level; A-weighted; note 2 at 0 dB signal level; f = 20 Hz to 20 kHz tcs current settling time to ±1 LSB α channel separation δIO unbalance between outputs td time delay between outputs S/N signal-to-noise ratio at bipolar zero 86 95 − dB see Fig.8 − 70 − dB note 2 − 0.2 0.3 dB − ±0.2 − µs A-weighted; at code 0000H 93 98 − dB Notes 1. Vripple = 1% of the supply voltage; fripple = 100 Hz. 2. Measured with 1 kHz sinewave generated at a sampling rate of 384 kHz. QUALITY SPECIFICATION In accordance with UZW-BO/FQ-0601. July 1993 8 Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T TEST AND APPLICATION INFORMATION handbook, full pagewidth WS tr <12 tHB >15 tf <12 tHD; WS >10 tLB >15 >12 tSU; WS BCK tCY >54 DATAR DATAL tSU; DAT >12 tHD; DAT >10 MSB LSB MGE234 SAMPLE OUT Fig.4 Timing of input signals. July 1993 9 July 1993 10 WS if LRSEL = 0 WS if LRSEL = 1 SAMPLE OUT MSB SAMPLE OUT MSB LEFT LEFT Fig.6 Format of input signals at 4FS. LSB Fig.5 Format of input signals at 8FS. MSB RIGHT RIGHT LSB LSB MGE236 MGE235 Stereo continuous calibration DAC (CC-DAC) BCK SI WS BCK RSI LSI Philips Semiconductors Objective specification TDA1313; TDA1313T Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T APPLICATION INFORMATION handbook, full pagewidth 10 7 1 nF 1 nF 9 VOUTL VOUTR 8 TDA1313T 200 pF 3 16 1 2 15 3 kΩ 4 22 µF 13 14 100 nF 5 6 12 100 nF VDDD 3 kΩ 200 pF 11 100 nF VDDO VDDA MGE232 Fig.7 TDA1313T as line driver with 3 kΩ/200 pF load. handbook, full pagewidth 10 8.2 kΩ VOUTL 7 2 nF 2 nF 9 8 100 µF 32 Ω 100 µF TDA1313T 3 16 1 2 15 4 14 100 nF 5 6 100 nF VDDD VDDO 12 11 100 nF VDDA MGE233 Fig.8 TDA1313T as headphone driver with 32 Ω load. 11 VOUTR 32 Ω 22 µF 13 July 1993 8.2 kΩ Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.7 1.40 1.14 0.53 0.38 0.32 0.23 21.8 21.4 6.48 6.20 2.54 7.62 3.9 3.4 8.25 7.80 9.5 8.3 0.254 2.2 inches 0.19 0.020 0.15 0.055 0.045 0.021 0.015 0.013 0.009 0.86 0.84 0.26 0.24 0.10 0.30 0.15 0.13 0.32 0.31 0.37 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT38-1 050G09 MO-001AE July 1993 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-10-02 95-01-19 12 Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0098 0.39 0.014 0.0075 0.38 0.050 0.24 0.23 0.041 0.039 0.016 0.028 0.020 inches 0.0098 0.057 0.069 0.0039 0.049 0.16 0.15 0.01 0.01 0.028 0.004 0.012 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07S MS-012AC July 1993 EIAJ EUROPEAN PROJECTION ISSUE DATE 91-08-13 95-01-23 13 o 8 0o Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. July 1993 14 Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. July 1993 15