PHILIPS TDA8792M

INTEGRATED CIRCUITS
DATA SHEET
TDA8792
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
Product specification
Supersedes data of 1995 Apr 26
File under Integrated Circuits, IC02
1996 Feb 21
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
FEATURES
APPLICATIONS
• 8-bit resolution
Analog-to-digital conversion for:
• Sampling rate up to 25 MHz
• General purpose
• 30 MHz input signal bandwidth (full scale)
• Hand-held equipment
• High signal-to-noise ratio over a large analog input
frequency range (7.3 effective bits at 4.43 MHz
full-scale input at fclk = 25 MHz)
• Mobile telecommunication
• Instrumentation
• Video.
• CMOS compatible digital inputs
• External reference voltage regulator
GENERAL DESCRIPTION
• Power dissipation only 53 mW (typical)
The TDA8792 is a 8-bit analog-to-digital converter (ADC)
for low-voltage, portable applications. It operates at 3.3 V
and converts the analog input signal into 8-bit
binary-coded digital words at a maximum sampling rate of
25 MHz. The output data is valid after a delay of 6 clock
cycles.
• Standby mode (only 1.2 mW typical)
• Low analog input capacitance, no buffer amplifier
required
• No sample-and-hold circuit required.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDA
analog supply voltage
2.85
3.3
3.6
V
VDDD
digital supply voltage
2.70
3.3
3.6
V
VDDO
output stages supply voltage
2.5
3.3
3.6
V
IDDA
analog supply current
−
12
20
mA
IDDD
digital supply current
−
3
6
mA
IDDO
output stages supply current
fclk = 25 MHz; CL = 15 pF;
ramp input
−
1
2
mA
INL
integral non-linearity
fclk = 25 MHz; ramp input
−
±0.4
±0.8
LSB
DNL
differential non-linearity
fclk = 25 MHz; ramp input
−
±0.3
±0.75
LSB
fclk(max)
maximum clock frequency
25
−
−
MHz
Ptot
total power dissipation
−
53
100
mW
fclk = 25 MHz; CL = 15 pF;
ramp input
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8792M
SSOP24
plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
1996 Feb 21
2
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
BLOCK DIAGRAM
ndbook, full pagewidth
STDBY 1
V DDD
24
23
2
22
4
VI
5
V DDA 6
21 D7
DECODER
LATCHES
8
18 D4
data outputs
17 D3
16 D2
REFERENCE
LADDER
15 D1
DAC
14 D0
VSSA2 12
13 OE
MLD119 - 1
Fig.1 Block diagram.
1996 Feb 21
MSB
19 D5
OUTPUT
BUFFER
V RT 8
V RB 10
VDDO
20 D6
7x8
OFFSET
COMPENSATED
COMPARATORS
I bias 7
VRM 9
VSSO
TDA8792
VSSD2
3
VSSA1
CLK
3
LSB
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
PINNING
SYMBOL
PIN
DESCRIPTION
STDBY
1
standby input
VDDD
2
digital supply voltage (+3.3 V)
VSSD2
3
digital ground 2
VSSA1
4
analog ground 1
VI
5
analog input voltage
VDDA
6
Ibias
handbook, halfpage
STDBY
1
24 CLK
analog supply voltage (+3.3 V)
V DDD
2
23 VSSO
7
bias current input
VSSD2 3
22 V
VRT
8
reference voltage TOP input
VSSA1
4
21 D7
VRM
9
reference voltage MIDDLE
20 D6
10
reference voltage BOTTOM input
VI
5
VRB
n.c.
11
not connected
VSSA2
12
analog ground 2
13
output enable input (CMOS level
input, active LOW)
D0
14
data output; bit 0 (LSB)
D1
15
data output; bit 1
D2
16
data output; bit 2
D3
17
data output; bit 3
D4
18
data output; bit 4
D5
19
data output; bit 5
D6
20
data output; bit 6
D7
21
data output; bit 7 (MSB)
VDDO
22
positive supply voltage for output
stage (+3.3 V)
VSSO
23
output ground
CLK
24
clock input
OE
1996 Feb 21
V
DDA
DDO
19 D5
6
TDA8792
I bias
7
18 D4
V RT
8
17 D3
V RM
9
16 D2
V RB 10
15 D1
n.c. 11
14 D0
VSSA2 12
13 OE
MLD120 - 1
Fig.2 Pin configuration.
4
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDA
analog supply voltage
note 1
−0.5
+5.0
V
VDDD
digital supply voltage
note 1
−0.5
+5.0
V
VDDO
output stages supply voltage
note 1
−0.5
+5.0
V
∆VDD1
supply voltage differences between
∆VDD1 = VDDA − VDDD
−0.3
+0.3
V
∆VDD2
supply voltage differences between
∆VDD2 = VDDD − VDDO
−1.0
+1.0
V
∆VDD3
supply voltage differences between
∆VDD3 = VDDA − VDDO
−1.0
+1.0
V
VI
input voltage
referenced to VSSA
−0.5
+5.0
V
Vclk(p-p)
AC input voltage for switching
(peak-to-peak value)
referenced to VSSD
−
VDDD
V
IO
output current
−
10
mA
Tstg
storage temperature
−55
+150
°C
Tamb
operating ambient temperature
−20
+75
°C
Tj
junction temperature
−
+125
°C
Note
1. The supply voltages VDDA, VDDD and VDDO may have any value between −0.5 V and +5.0 V provided that the
differences ∆VDD1, ∆VDD2 and ∆VDD3 are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1996 Feb 21
PARAMETER
thermal resistance from junction to ambient in free air
5
VALUE
UNIT
119
K/W
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
CHARACTERISTICS
VDDA = V6 to V4,12 = 2.85 to 3.6 V; VDDD = V2 to V3 and V1 = 2.7 to 3.6 V; VDDO = V22 to V23 = 2.5 to 3.6 V;
VSSA, VSSD and VSSO shorted together; VDDA to VDDD = −0.15 to +0.15 V; fclk = 25 MHz; 50% duty factor; VIL = 0 V;
VIH = VDDD; CL = 15 pF; Tamb = 0 to +70 °C; typical values measured at VDDA = VDDD = VDDO = 3.3 V and Tamb = 25 °C;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDA
analog supply voltage
2.85
3.3
3.6
V
VDDD
digital supply voltage
2.7
3.3
3.6
V
VDDO
output stages supply voltage
2.5
3.3
3.6
V
IDDA
analog supply current
−
12
20
mA
IDDD
digital supply current
−
3
6
mA
IDDO
output stages supply current
−
1
2
mA
CL = 15 pF; ramp input
Inputs
CLOCK INPUT CLK (REFERENCED TO VSSD); note 1
VIL
LOW level input voltage
0
−
0.8
V
VIH
HIGH level input voltage
2.0
−
VDDD
V
IIL
LOW level input current
Vclk = 0.4 V
−10
−
−
µA
IIH
HIGH level input current
Vclk = 2.7 V
−
−
10
µA
CI
input capacitance
−
10
−
pF
INPUTS OE AND STDBY (REFERENCED TO VSSD); see Tables 2 and 3
VIL
LOW level input voltage
0
−
0.8
V
VIH
HIGH level input voltage
2.0
−
VDDD
V
IIL
LOW level input current
VIL = 0.4 V
−10
−
−
µA
IIH
HIGH level input current
VIH = 2.7 V
−
−
+10
µA
VI (ANALOG INPUT VOLTAGE REFERENCED TO VSSA)
IIL
LOW level input current
VI = 0 V
−20
−
−
µA
IIH
HIGH level input current
VI = 1.5 V
−
−
+20
µA
ZI
input impedance
fi = 4.43 MHz
−
35
−
kΩ
CI
input capacitance
fi = 4.43 MHz
−
5
−
pF
Reference voltages for the resistor ladder; see Table 1
VRB
reference voltage BOTTOM
0
−
0.15
V
VRT
reference voltage TOP
1.4
−
1.6
V
Vdiff
differential reference voltage VRT − VRB
1.25
1.5
1.6
V
Iref
reference current
−
1.3
−
mA
RLAD
resistor ladder
−
1250
−
Ω
TCRLAD
temperature coefficient of the resistor
ladder
−
1
−
Ω/K
1996 Feb 21
6
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
SYMBOL
TDA8792
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Outputs
DIGITAL OUTPUTS D7 TO D0 (REFERENCED TO VSSO)
VOL
LOW level output voltage
IO = 1 mA
0
VOH
HIGH level output voltage
IO = −1 mA
IOZ
output current in 3-state mode
0.4 V < VO < VDDO
−
0.4
V
VDDO − 0.4 −
VDDO
V
−10
−
+10
µA
Switching characteristics
CLOCK INPUT CLK (VDDA = 3.15 TO 3.45 V; VDDD = 3.15 TO 3.45 V); see Fig.3 and note 1
fclk(max)
maximum clock frequency
25
−
−
MHz
fclk(min)
minimum clock frequency
0.5
−
−
MHz
tCPH
clock pulse width HIGH
16
−
−
ns
tCPL
clock pulse width LOW
16
−
−
ns
Analog signal processing
LINEARITY
INL
integral non-linearity
ramp input
−
±0.4
±0.8
LSB
DNL
differential non-linearity
ramp input
−
±0.3
±0.75
LSB
full-scale sine wave;
note 2
20
30
−
MHz
small signal at mid-scale;
Vi = ±10 LSB at
code 128; note 2
−
35
−
MHz
BANDWIDTH (VDDA = 3.15 TO 3.45 V; VDDD = 3.15 TO 3.45 V); TAMB = 25 °C
B
analog bandwidth
tSTLH
analog input settling time LOW-to-HIGH full-scale square wave;
Fig.5; note 3
−
8
12
ns
tSTHL
analog input settling time HIGH-to-LOW full-scale square wave;
Fig.5; note 3
−
8
12
ns
h1
fundamental harmonics (full scale)
fi = 4.43 MHz
−
−
0
dB
hall
harmonics (full scale); all components
fi = 4.43 MHz
second harmonics
−
−61
−
dB
third harmonics
−
−61
−
dB
fi = 4.43 MHz
−
−58
−
dB
without harmonics;
fclk = 25 MHz;
fi = 4.43 MHz
−
46
−
dB
HARMONICS
THD
total harmonic distortion
SIGNAL-TO-NOISE RATIO; see Figs 6 and 11; note 4
S/N
signal-to-noise ratio (full scale)
1996 Feb 21
7
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
SYMBOL
TDA8792
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
EFFECTIVE BITS; see Figs 6 and 11; note 4
EB
effective bits
fclk = 25 MHz
fi = 2.0 MHz
−
7.4
−
bits
fi = 4.43 MHz
−
7.3
−
bits
fi = 7.5 MHz
−
7.2
−
bits
fi = 10 MHz
−
7.0
−
bits
fclk = 25 MHz;
PAL modulated ramp
−
1.5
−
%
fclk = 25 MHz;
PAL modulated ramp
−
0.5
−
deg
−
2
ns
DIFFERENTIAL GAIN; see note 5
Gdiff
differential gain
DIFFERENTIAL PHASE; see note 5
ϕdiff
differential phase
Timing (fclk = 25 MHz); see Fig.3 and note 6
tds
sampling delay time
−
th
output hold time
6
−
−
ns
td
output delay time
8
13
25
ns
3-state output delay times; see Fig.4
tdZH
enable HIGH
−
17
28
ns
tdZL
enable LOW
−
22
30
ns
tdHZ
disable HIGH
−
20
28
ns
tdLZ
disable LOW
−
22
30
ns
ns
Standby mode output delay times
tdSTBLH
standby (LOW-to-HIGH transition)
−
−
200
tdSTBHL
start-up (HIGH-to-LOW transition)
−
−
note 7 ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. The analog bandwidth is defined as the maximum full-scale input sine wave frequency which can be applied to the
device. No glitches greater than 8 LSBs are observed in the reconstructed signal neither is there any significant
attenuation.
3. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
5. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
6. Output data acquisition: the output data is available after the maximum delay time of td. In the event of 25 MHz clock
operation, the hardware design must be taken into account the td and th limits with respect to the input characteristics
of the acquisition circuit.
7000
7. Maximum value standby mode start-up output delay time (HIGH-to-LOW transition): 100 + ------------------------ .
f clk (MHz)
1996 Feb 21
8
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
Table 1
TDA8792
Output coding and input voltage (typical values; referenced to VSSA)
BINARY OUTPUT BITS
STEP
VI(p-p) (V)
D7
D6
D5
D4
D3
D2
D1
D0
Underflow
<0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
.
0
0
0
0
0
0
0
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
254
.
1
1
1
1
1
1
1
0
255
1.5
1
1
1
1
1
1
1
1
Overflow
>1.5
1
1
1
1
1
1
1
1
Table 2
Mode selection
Table 3
Standby selection
OE
D7 TO D0
STDBY
D7 TO D0
IDDA + IDDD (typ.)
1
high impedance
1
LOW
0.4 mA
0
active; binary
0
active
15 mA
t CPL
t CPH
1.4 V
CLK
sample N 1
sample N 2
sample N 6
Vl
t ds
DATA
D0 to D7
th
V DDO
DATA
N 6
DATA
N 5
DATA
N 1
DATA
N
50%
0.4 V
td
MLD121
Fig.3 Timing diagram.
1996 Feb 21
9
0.4 V
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
handbook, full pagewidth
TDA8792
V DDD
50 %
OE
t dHZ
t dZH
HIGH
90 %
output
data
50 %
t dLZ
LOW
t dZL
HIGH
output
data
50 %
LOW
10 %
V DDD
3.3 kΩ
S1
TDA8792
15 pF
TEST
S1
t dLZ
t dZL
VDDD
VDDD
t dHZ
GND
t dZH
GND
OE
MLD122
fOE = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
1996 Feb 21
10
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
t STHL
t STLH
code 255
VI
50 %
50 %
code 0
2 ns
2 ns
CLK
50 %
50 %
2 ns
MLD123
2 ns
Fig.5 Analog input settling-time diagram.
MLD118
0
handbook, full pagewidth
A
(dB)
20
40
60
80
100
120
0
1.56
3.13
4.69
6.25
7.82
9.38
10.9
12.5
f (MHz)
Effective bits: 7.42; THD = −57.27 dB;
Harmonic levels (dB): 2nd = −60.76; 3rd = −60.96; 4th = −76.17; 5th = −80.63; 6th = −66.96.
Fig.6 Typical Fast Fourier Transform (fclk = 25 MHz; fi = 4.43 MHz).
1996 Feb 21
11
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
INTERNAL PIN CONFIGURATIONS
V
DDA
D7 to D0
V
V
MLD124
I
SSA
MLD125
Fig.8 Analog inputs.
Fig.7 Digital data outputs.
handbook, halfpage
VDDA
handbook, halfpage
V
DDD
VRT
OE,
CLK or STDBY
VRM
R LAD
VRB
V
SSD
VSSA
MLD126 - 1
MLC859
Fig.9 Digital inputs.
Fig.10 VRB, VRM and VRT.
V
DDA
I bias
V
SSA
MLD127
Fig.11 Bias current input.
1996 Feb 21
12
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
APPLICATION INFORMATION
STDBY
handbook, full pagewidth
V DDD
3.3 V
1
24
2
23
3
22
VI
V DDA
3.3 V
100 nF
I bias
22 kΩ
VSSO
V
VSSD2
VSSA1
CLK
DDO
3.3 V
D7
4
21
5
20
6
19
100 nF
D6
D5
TDA8792
D4
7
18
8
17
9
16
10
15
11
14
12
13
(1)
V RT
3.3 V
100 nF
D3
(1)
100 nF
V RM
D2
(1)
V RB
100 nF
100 nF
(2)
D0
n.c.
V
D1
SSA2
OE
MLD128 - 1
The analog and digital supplies should be separated and decoupled.
The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. The reference
ladder voltages can also be derived from a well regulated VDDA supply through a resistor bridge and a decoupled capacitor.
For applications where the input signal must remain well centred around middle scale, VRM must be decoupled and connected to analog input signal
(pin 5) through a resistor. The values must be defined in accordance with the input signal frequency in order to avoid direct coupling into the ADC ladder
(e.g. R = 5 kΩ and C = 100 nF).
(1) VRB, VRM and VRT are decoupled to VSSA.
(2) Pin 11 should be connected to VSSA in order to prevent noise influence.
Fig.12 Application diagram.
1996 Feb 21
13
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
PACKAGE OUTLINE
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
D
SOT340-1
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.0
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.8
0.4
8
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
SOT340-1
1996 Feb 21
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
93-09-08
95-02-04
MO-150AG
14
o
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING SSOP
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
cases reflow soldering is often used.
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SSOP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from 215 to
250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds at between 270 and
320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1996 Feb 21
15
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Feb 21
16
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
NOTES
1996 Feb 21
17
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
NOTES
1996 Feb 21
18
Philips Semiconductors
Product specification
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
TDA8792
NOTES
1996 Feb 21
19
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SCDS47
© Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the
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Document order number:
Date of release: 1996 Feb 21
9397 750 00675