INTEGRATED CIRCUITS SA5753 Audio processor — filter and control section Product specification Replaces data of 1995 July 7 IC17 Data Handbook 1997 Nov 07 Philips Semiconductors Product specification Audio processor – filter and control section DESCRIPTION SA5753 PIN CONFIGURATION The SA5753 is a high performance low power CMOS audio signal processing system especially designed to meet the requirements for small size and low voltage operation of hand-held equipment. The SA5753 subsystem includes complementary transmit/receive voice band (300-3000Hz), switched capacitor bandpass filters with pre-emphasis and de-emphasis respectively, a transmit low pass filter, peak deviation limiter for transmit, digitally controlled attenuators for signal level and volume control, audio path mute switches, a programmable DTMF generator, power-down circuitry for low current standby, power-on reset capability, and an I2C interface. When the SA5753 is used with an SA5752 (companding function), the complete audio processing system of an AMPS, TACS, NAMPS or NTACS cellular telephone is easily implemented. DK Package TXBFIN 1 TXBFOUT 20 TX OUT 19 DATA 2 IN PREMPIN 3 18 TX MUTE 4 17 SDA VOXCTL 5 16 SCL VDD HPDN 6 SA5753 DEMPOUT 7 14 CLKIN AUDIOIN 8 13 DFT SPKROUT 9 The system also meets the requirements of the proposed NAMPS or NTACS specification, and can be used in cordless telephone applications. EAROUT 15 GND 12 RX MUTE 10 11 RX DEMODIN SR00666 The SA5753 can be operated without the I2C bus interface by pulling DFT (Pin 13) HIGH. Figure 1. Pin Configuration FEATURES BENEFITS • Low 3V supply • Miniature SSOP package • Low power • High performance • Built-in programmable DTMF generator • Built-in digitally controlled attenuators for modulation and volume • Very compact application • Long battery life in portable equipment • Complete cellular audio function with the SA5752 APPLICATIONS • Cellular radio • Mobile communications • High performance cordless telephones • 2-way radio control • Built-in peak-deviation limiter • I2C Bus controlled • Power-on reset • Power down capability • Programmable mute control • Meets AMPS/TACS/NAMPS/NTACS requirements ORDERING INFORMATION DESCRIPTION 20-Pin Plastic Shrink Small Outline Package (SSOP) TEMPERATURE RANGE ORDER CODE DWG # -40 to +85°C SA5753DK SOT266-1 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER VDD Power supply voltage range VIN Voltage applied to any other pin TA 1997 Nov 07 RATING UNIT -0.3 to 6 V -0.3 to VDD+0.3 V Storage temperature -65 to +150 oC Ambient operating temperature -40 to +85 °C 2 853-1722 18666 Philips Semiconductors Product specification Audio processor – filter and control section SA5753 PIN DESCRIPTIONS PIN NO. SYMBOL 1 TXBFIN 2 TXBFOUT Transmit bandpass filter output 3 PREMPIN Pre-emphasis input 4 VDD 5 VOXCTL DESCRIPTION Transmit bandpass filter input Positive supply Vox control output 6 HPDN 7 DEMPOUT Power-down I/O 8 AUDIOIN Audio input De-emphasis output 9 SPKROUT Audio output to speaker 10 EAROUT Audio output to earpiece 11 RX DEMODIN 12 RX MUTE 13 DFT 14 CLKIN Clock input (1.2MHz) 15 GND Ground 16 SCL I2C serial clock line 17 SDA I2C serial data line 18 TX MUTE 19 DATAIN Data input 20 TXOUT Transmit output 1997 Nov 07 Rx demodulated audio signal input RX audio signal mute input Default input, non-I2C or stand-alone operation Tx audio signal mute input 3 Philips Semiconductors Product specification Audio processor – filter and control section SA5753 DC ELECTRICAL CHARACTERISTICS TA = 25oC, VDD = +3.3V, unless otherwise specified. See test circuit, Figure 2. SYMBOL VDD PARAMETER TEST CONDITIONS Power supply voltage LIMITS MIN TYP MAX 3.0 3.3 5.5 Operating IDLE Power Down (PWDN) IDD Supply current Input current high TX MUTE, RX MUTE, HPDN DFT VIN = VDD IIH Input current low TX MUTE, RX MUTE, HPDN, DFT VIN = GND IIL VIH Input voltage high VIL Input voltage low 1.7 600 200 UNIT V mA µA µA –10 0 0 +10 +10 +30 µA µA –30 –10 –10 0 0 +10 µA µA 0.7VDD VDD V 0 0.3VDD V AC ELECTRICAL CHARACTERISTICS TA = 25oC, VDD = +3.3V. See test circuit, Figure 2. Clock frequency = 1.2MHz; test level = 0dBV = 77.5mVRMS = -20dBm, unless otherwise specified. All gain control blocks (Attenuators) = 0dB gain, NAMPS and VCO bits set to 0. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN RX BPF anti alias rejection RX BPF input impedance f= 1kHz UNIT 40 dB 100 kΩ f = 1kHz RX BPF gain with de-emphasis f = 100Hz RX BPF gain with de-emphasis f = 300Hz 8.5 9.6 11.5 dBm0 RX BPF gain with de-emphasis f = 3kHz -11.5 -10.0 -8.5 dBm0 RX BPF gain with de-emphasis f = 5.9kHz -58 dBm0 300Hz-3kHz 200 µVRMS with deemphasis 80 RX dynamic range DEMPOUT output impedance f = 1kHz DEMPOUT output swing (1%) 2kΩ to VDD/2; f = 1kHz 0 1.0 -30 dB dBm0 dB 40 Ω 2.4 VP-P VP-P SPKROUT ouput swing (1%) 50kΩ toVDD/2; f = 1kHz VDD -1 2.4 EAROUT output swing (1%) 50kΩ to VDD/2; f = 1kHz VDD -1 2.4 VP-P 200 µVRMS SPKROUT noise / EAROUT noise CLKIN high 2.1 CLKIN low TX LPF gain 1.0 V V f > 50kHz 40 f = 3kHz 100 KΩ 300 - 3000kHz 200 µVRMS TX BPF input impedance TX BPF noise 3.0 0 TX BPF anti alias rejection 1997 Nov 07 MAX RX BPF gain with de-emphasis RX BPF noise with de-emphasis -1.0 TYP dB f = 5.9kHz -39 TX LPF gain with pre-emphasis f = 1kHz, 0dBV 2.43 dB TX LPF gain with pre-emphasis f = 100Hz -19 dBm0 TX LPF gain with pre-emphasis f = 300Hz -10.45 dBm0 TX LPF gain with pre-emphasis f = 3kHz 9.14 dBm0 TX LPF gain with pre-emphasis f = 5900Hz -28 dBm0 TX LPF gain with pre-emphasis f = 9kHz -48 dBm0 TX overall gain 1kHz 2.43 TX overall gain 100Hz -58 -44 dBm0 TX overall gain 300Hz -10.4 -8.5 dBm0 4 -11.5 -36 dBm0 dB Philips Semiconductors Product specification Audio processor – filter and control section SA5753 AC ELECTRICAL CHARACTERISTICS (continued) SYMBOL PARAMETER TEST CONDITIONS TX overall gain 3kHz TX overall gain 5.9kHz LIMITS MIN TYP 8 TX BPF dynamic range Slew rate 9 9.6 dBm0 -52 -45 dBm0 TBD dB f = 3kHz 100 kΩ CL = 15pF 0.75 PREMPIN input impedance TXOUT Output impedance V/µs f = 3kHz Ω 40 Output swing (limiting) 5kΩ load (25°C) Output swing (1% THD) UNIT MAX Tx DTMF signal with TXLPF and pre-emphasis 1.2 VP-P 1.0 VP-P 0.45 Rx DTMF sidetone –0.8 Time delay to mute from RX MUTE or TX MUTE transition V/kHz 5.2 VIN = VIL to VIH VIN = VIH to VIL dBm0 µs µs 0.5 0.5 Table 1. Gain Control Blocks (Bit 0 is Least Significant Bit) TYPICAL GAIN (dB) SYMBOL Bits TYPICAL STEP (dB) A1 4 –0.8 –12.0 0 A2a 5 ±0.25 –3.75 +3.75 A2b 2 –6, (–12 on first) –24.0 0 A3 4 –1.0 –17.0 –2.0 A4 4 ±0.5 –3.5 +3.5 A6 4 –2.0 –30.0 0 A7 4 ±0.5 –3.5 +3.5 NAMPS 1 VCO 1 MAX +1.9 in A2b –7.6 in A4 +6.0 in A4 For A2a, A4 and A7: MSB sets the sign of the gain MSB = 0 for gain MSB = 1 for attenuation For all Gain Blocks: All bits set to 0 = 0dB gain All bits set to 1 = maximum gain or attenuation a. A1 compensates for microphone gain variations in the transmit path. FUNCTIONAL DESCRIPTION The SA5753 is an audio signal processor designed to meet the requirements of compact low voltage radio telephone equipment. It includes transmit and receive bandpass filters for voiceband (300-3000Hz) with pre-emphasis and de-emphasis respectively, a transmit peak deviation limiter, voice channel mute switches and a data path which can be summed into the transmit channel. An I2C interface is provided for software programmability of a DTMF generator, mute polarity, selection of different power down and operating modes and control of the gain in both the transmit and receive channels. b. A2a compensates for transmitter dynamic range variations due to manufacturing tolerances of the SA5753 and SA5752 compandor companion device. To meet AMPS requirements, the dynamic range between the zero crossing signal level of the compandor and the peak signal allowed by the deviation limiter is adjusted to 12.34dB. c. A2b allows coarse attenuation to be inserted in the transmit path to eliminate positive feedback effects in hands-free speaker applications. First step is 12dB followed by two steps of 6dB. Software programmable gain control allows the device to be automatically optimized during equipment production and offers flexibility during normal operation. d. A3 sets the gain between the DATAIN pin (Pin 19) and the TXOUT pin (Pin 20) and should be adjusted after A2a and A4 have been previously optimized. The SA5753 will interface directly with the UMA1000T data processor (which produces a 2Vpk data signal). For NAMPS applications an additional 10 to 14dB resistive divider must be added at the DATAIN pin (Pin 19) for a 2V data signal. Gain Blocks The programmable gain blocks are shown in Table 1 and Figure 2. The purpose for each block is as follows: 1997 Nov 07 MIN 5 Philips Semiconductors Product specification Audio processor – filter and control section SA5753 Although the POWER DOWN mode exhibits lower power consumption, glitches may occur when transferring to an active mode because of the previous high impedance of the I/O pins. e. A4 compensates for transmit gain variations due to manufacturing tolerances of the SA5753, SA5752 and VCO connected to TXOUT (Pin 20). After A2a has been adjusted to set dynamic range then A4 is used to set the peak output voltage at TXOUT (Pin 20) such that a nominal 10kHz/V VCO produces a peak deviation of 12kHz to meet AMPS specifications. The VOXCTL and HPDN pins (Pins 5 and 6) still have the same value as R8B7 and R5B1 in all low power modes. Operation Without Using the I2C Bus f. A6 is the volume control for both the SPKROUT and EAROUT. The SA5753 can be operated in a default mode with the I2C bus bypassed. To use this mode, the DFT pin (Pin 13) is pulled HIGH, then the I2C bus is bypassed and the SA5753 operates as if all register bits in the I2C address map table are set to ‘0’ except R1B2 (S13), R0B0 (S10) and R0B1 (S9), which are set to ‘1’ to enable the receiver output. R6B2 (PWDN), which is controlled by the state of the HPDN pin (Pin 6), which is an input in DEFAULT mode. g. A7 compensates for manufacturing tolerances in the SA5753 and preceeding demodulator. For AMPS requirements, a 1kHz tone with 2.9kHz deviation should produce an output signal at DEMPOUT (Pin 7) corresponding to the zero crossing signal level of the expandor. NAMPS and VCO Offsets When HPDN is pulled HIGH, the R6B2 bit is set to ‘0’ and the SA5753 is placed in it’s normal operating mode with all Gain Control Blocks set to 0dB except A3, which is set to –2dB. For NAMPS applications, a ‘1’ programmed into R5B3 (register 5, bit 3) will offset the transmit gain for NAMPS applications. It is recommended that A2a and A4 be programmed after the NAMPS option is set to compensate for manufacturing tolerances in the NAMPS offset, itself. When HPDN is pulled LOW, the R6B2 bit is set to ‘1’ and the SA5753 enters POWER DOWN. When the VCO bit of R5B2 is a ‘1’, an extra gain of 6dB is provided at TXOUT for direct interface to VCOs with a nominal gain of 5kHz/V. There is no on-chip pull-up or pull-down structure on the HPDN pin and so it must not be allowed to float in DEFAULT mode since the operating mode of the SA5753 will then be undetermined. Operation Using the I2C Communications Bus The SA5753 includes on-chip gain blocks and options which can be programmed through an I2C interface bus. To use this capability, the DFT pin (Pin 13) must be pulled LOW. In this mode, all signal level adjustments can be made through software with no external potentiometers required. The Tx MUTE and Rx MUTE pins must be pulled LOW to enable the transmit and receive paths, respectively. With DFT pulled LOW, the HPDN pin (Pin 6) is an OUTPUT having the same value as the program bit in register 5 bit 1 (R5B1) of the control register bit map. The value at the VOXCTL output (Pin 5) is the same as the program bit in R8B7. The HPDN and VOXCTL outputs can be used to control the state of the SA5752 companion device. The DTMF is disabled in the DEFAULT mode. The VOXCTL pin (Pin 5) will follow the value of the control bit stored in R8B7 prior to pulling DFT HIGH. Programming Without the I2C Protocol In the default mode, with DFT (Pin 13) and HPDN (Pin 6) pulled HIGH, the registers in the control register bit map are chained together so that bit 0 of a register is connected to bit 7 of the preceeding register with R0B6, R0B7, R1B6 and R1B7 bypassed, i.e., R0B5 is connected to R1B0, R1B5 is connected to R2B0, R2B7 is connected to R3B0, etc. Bits can then be loaded as a serial stream through the SDA pin of the I2C bus by the negative edge of a shifting clock applied at the SCL pin of the I2C bus. When a bit is loaded at SDA it will load first into R0B0 and then will be shifted to R8B7 after 68 clock edges. Power On Reset and Power Down Modes In order to avoid undefined states of the SA5753 when power is initially applied, a power-on-reset circuit is incorporated which defaults RxP and TxP such that the receive and transmit paths are muted if a ‘high’ voltage is applied to RX MUTE and TX MUTE (Pins 12 and 18). RX MUTE and TX MUTE include on-chip pull up resistors so, during power up, the user may apply a logic ‘1’ to these pins or leave them floating. After power up, the registers can be programmed and the mutes removed by a quick access write to R0. A total of 68 clock pulses (applied at SCL) are therefore required to completely load the registers. In this mode of operation the contents of the register map are also shifted out from the VOXCTL pin since it takes the same value as R8B7. After power up there is no reset within the registers so the first 68 bits clock out at the VOXCTL pin will have an indeterminate value. Three software controlled low power modes are provided on the SA5753. These are POWER DOWN (PWDN), IDLE and DENA and can be selected by programming a ‘1’ into R6B2, R6B1 or R6B0 as follows. In PWDN mode (R6B2=1) both the voice and data channels are powered down with the respective I/O pins at a high impedance. In DENA mode (R6B1=1) the voice channels are powered down, but the data channel (from DATAIN and TXOUT) is fully active. In IDLE mode (R6B1=1, R6B0=1) both voice and data channels are powered down. (See Table on page 8.) Summary: To use this capability, the DFT pin and the HPDN pin must be pulled HIGH, the serial bit stream loaded through SCL synchronous with the negative clock edge applied at SCL for 68 clock pulses, and then the DFT pin pulled LOW. NOTE: Default Mode is not tested in production. The difference between selecting IDLE and PWDN is that the former maintains the normal operational bias voltages at all voice and data I/O pins and provides a glitch-free transfer from power down to a fully active mode and vice-versa. 1997 Nov 07 6 Philips Semiconductors Product specification Audio processor – filter and control section SA5753 Cordless Telephone Applications I2C Bus Data Configurations For cordless telephone applications, a switch S12 is provided (R5B0) to route data through the complete transmit path while inhibiting the voice channel. In the receive path, a quick access mode is provided through the I2C to disable both EAROUT and SPKROUT, by setting R0B0 and R0B1, when data is detected at the DEMPOUT pin (Pin 7). The SA5753 is always a slave receiver in the I2C bus configuration). The slave address consists of eight bits in the serial mode and is internally fixed. Control Registers The control register bit map is shown below. Either a quick access or normal address mode can be used, determined by the two MSB bits in the first word following the SA5753 address word. If the quick access mode is used, the registers R0 or R1 can be updated by sending only two bytes of information (address plus update). If R0 or R1 are updated using the address mode, then B7 and B6 of the data word are ignored. In all access modes, incremental register addressing is supported with following words updating the next register until a ‘stop’ bit is sent. I2C CHARACTERISTICS The I2C bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both SDA and SCL are bidirectional lines connected to a positive supply voltage via a pull-up resistor. When the bus is free, both lines are HIGH. Data transfer may be initiated only when the bus is not busy (both lines HIGH). The output devices, or stages, connected to the bus must have an open drain or open collector output in order to perform the wired-AND function. High Tone DTMF Register Data at the I2C bus can be transferred at a rate up to 100kbits/s. The number of devices connected to the bus is solely dependent on the maximum allowed bus capacitance of 400pF. The eight bits determine the output frequency by the following formula.: MSB LSB HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 High Frequency = 1200kHz/6/HD where HD is the value of the register. For devices operating over a wide range of supply voltages, such as the SA5753, the following levels have been defined for a logical LOW and HIGH; Low Tone DTMF Register MSB LSB LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 VILMAX = 0.3VDD (max. input LOW voltage) VIHMIN = 0.7VDD (min. input HIGH voltage) The eight bits determine the output frequency by the following formula.: Data Transfer Data is transferred from a transmitting device to a receiving device with one data bit transferred during each clock pulse on the SCL line. The transmitter also generates the clock once arbitration has given it control of the SCL line. The data on the SDA line must remain stable during the HIGH period of the clock cycle, otherwise it may be interpreted as a control signal. Low Frequency = 1200kHz/14/LD where LD is the value of the register. The operation of the 96ms DTMF timer is initiated by the loading of the low tone DTMF register. This timer terminates transmission of the tones as the generated tones cross the reference level after 96ms. The on time of the tones can thus vary by up to one cycle of the tones. Start and Stop Conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH to LOW transition of the data line while the clock line is HIGH is defined as a start condition. A LOW to HIGH transition of the data line while the clock is HIGH is defined as a stop condition. Continuous tones can be obtained by again loading DTC = 1 in R1, bit 5. Single tones can be obtained by loading 2 into the unused tone register to silence it. Acknowledgement Loading a value of 1 or 0 into the registers will default the register value to 257 or 256 for high tone or low tone, respectively. Following each byte of data transfered, the receiver must acknowledge successful reception. To do this the transmitter releases the SDA line (allowing it to go HIGH) at the end of each transmitted byte, and it is pulled LOW by the receiver. If this condition is maintained during the next HIGH period of the clock pulse (called the acknowledge clock pulse) then data transfer is resumed. If the receiver does not pull the SDA line LOW, the transmitter will abort the transfer. 1997 Nov 07 Phase continuous frequency modulation can be produced by loading a new value into a DTMF register during continuous operation (DTC=1). 7 Philips Semiconductors Product specification Audio processor – filter and control section SA5753 I2C Address and Access S A7 A6 A5 A4 A3 A2 A1 A0 ACK F7 F6 F5 F4 F3 F2 F1 F0 ACK ... P S = start, A0 = 0, ACK = acknowledge, P = stop, A7–0 = SA5753 address fixed internally at 1000000. Access mode is determined by F7, F6. All access modes support incremental addressing. Mode F7 F6 quick access 0 0 Load F5–F0 to R0B5 – R0B0 quick access 0 1 Load F5-F0 to R1B5 – R1B0 test mode 1 0 For test only. DO NOT USE. address mode 1 1 F3–F0 point to register Address Map Address REG F3 F2 F1 F0 Action Register Bits B6 Y RxM TxM A2bb1 A2bb0 S9 S10 Y Y DTC S4 S8 S13 S7 S2 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 A1b3 A1b2 A1b1 A1b0 A4b3 A4b2 A4b1 A4b0 1 A6b3 A6b2 A6b1 A6b0 NAMPS VCO HPDN S12 1 0 A2ab4 A2ab3 A2ab2 A2ab1 A2ab0 PWDN IDLE 1 IDLE 0 1 1 1 A3b3 0 0 0 R0 0 0 0 0 R1 0 0 0 1 R2 0 0 1 0 R3 0 0 1 1 R4 0 1 0 0 R5 0 1 0 R6 0 1 R7 0 R8 1 B7 Y A3b2 VOXCTL S3 B5 B4 B3 B2 B1 B0 A3b1 A3b0 A7b3 A7b2 A7b1 A7b0 S5 S6 S11 RxP TxP S1 Y = ignored in address mode. For all bits TRUE = ‘1’ A1b3–0 = program bits for gain block A1 TxP = transmit mute polarity DTC = DTMF continuous A2ab4–0 = program bits for gain block A2a A2bb1–0 = program bits for gain block A2b S1 = bypass TXBPF A3b3–0 = program bits for gain block A3 S2 = bypass compressor in TX path, inhibit pre-emph input S3 = bypass pre-emp and limiter in Tx path A4b4–0 = program bits for gain block A4 S4 = enable DTMF to TX path and inhibit PREMPIN and S2. A5b2–0 = program bits for gain block A5 A6b3–0 = program bits for gain block A6 S5 = bypass RXBPF A7b3–0 = program bits for gain block A7 S6 = bypass de-emph in RX path HD7–0 = high tone DTMF S7 = bypass expandor in RX path, inhibit audio input LD7–0 = low tone DTMF S8 = enable DTMF to RX path and inhibit AUDIOIN and S7. NAMPS = program bit for NAMPS offset S9 = enable SPKROUT VCO = 6dB higher TXOUT S10 = enable EAROUT S11 = bypass TXLPF RxM = receive mute S12 = cordless data option established TxM = transmit mute RxP = receive mute polarity S13 = enable data path VOXCTL = enable VOX of compandor/expander circuit. This bit appears at the VOXCTL pin (Pin 5) of the SA5753. HPDN = enable power down of compandor circuit. This bit appears at the HPDN pin (Pin 6) of the SA5753 PWDN, IDLE1, IDLE0 see Table below Low Power Modes (R6B0 – R6B2) PWDN IDLE1 IDLE0 1 X X (PWDN) Complete power down except I2C, I/Os high impedance. 0 0 0 0 1 1 0 0 0 1 0 1 (DENA) Low power, I/Os at VDD/2, DATAIN to TXOUT enabled. (IDLE) Low power, I/Os at VDD/2, DATAIN to TXOUT disabled. Normal operation. DATAIN to TXOUT disabled. X = don’t care. 1997 Nov 07 SR00667 8 Philips Semiconductors Product specification Audio processor – filter and control section SA5753 220nF 20 S12 TXOUT S11 S1 ATTN 4 220nF 1 TXBFIN MUTE TX TXLPF S13 220nF ATTN 1 2 TXBFOUT Σ TXBPF S12 VREF 33nF ATTN 3 S3 3 18 TX MUTE 17 SDA 16 SCL I2C R8B1 S2 VDD DATAIN PREEMPH AND SOFT LIM 33nF PREMPIN 19 ATTN 2 I2C R0B4 4 S2 .1µF S4 I2C INTERFACE AND VOXCTL 5 I2C R8B7 HPDN 6 I2C R5B1 REGISTERS S4 DTMF GEN 15 GND S6 2.2µF 1.2MHz 14 DEEMPH 7 DEMPOUT CLKIN S7 S8 S5 220nF 8 AUDIOIN RXBPF 13 DFT 12 RX MUTE S8 S7 I2C R0B5 220nF 9 I2C R8B3 MUTE RX S9 SPEAKER OUT ATTN 6 220nF EAROUT 10 ATTN 7 S10 11 RX DEMODIN 220nF SR00668 Figure 2. SA5753 Test and Application Circuit 1997 Nov 07 9 1997 Nov 07 43k R2 4.7 µ F C2 + 10 Figure 3. Application Diagram for the Audio Processor 2.2 µ F EXPCAP VCC 10 µ F VREF GND VOXTR VOXOUT + C6 + C5 5.6k R4 R3 3 2 1 10 9 8 7 6 5 4.3k 4 22nF 220nF C1 C3 2.2 µ F C4+ NCAN CAP RECTGRES R1 Avset PREAMPGRES MIC IN REF SA5752 BANDGAP VOLTAGE VOX NOISE CANCEL PREAMP EXP COMP BUFFER COMPCAP3 COMPCAP3 C7 EXP IN HPDN VOX CTL C8 V DD EAR OUT SPKR OUT AUDIO IN DE EMPH OUT HPDN VOX CTL 0.1 µ F 33nF C10 PRE EMPH IN TXBPF OUT TXBPF IN 10 9 8 7 6 5 4 3 2 1 S12 S7 S7 S10 S9 S8 S8 S4 S3 ATTN 6 DEEMPH S6 I2C R5B1 I2C R8B7 S2 S2 ATTN 1 TXBPF S1 SA5753 MUTE RX S5 RXBPF DTMF GEN S4 ATTN 2 PREEMPH AND SOFT LIM TXLPF S11 ATTN 7 MUTE TX Tx MUTE R0B4 I2C R8B3 Rx MUTE R0B5 REGISTERS AND ATTN 4 I2C R8B1 V REF I 2 C INTERFACE ATTN 3 S13 Σ IN 1.2MHz CLOCK MUTE IN RX DEMOD 11 12 RX 13 DFT 14 15 GND 16 SCL 17 SDA TX MUTE 18 19 OUT DATA TX 20 IN Audio processor – filter and control section TDA7050T 220nF C15 220nF C16 + 2.2 µ F COMPCAP2 2.2 µ F + COMPOUT + 2.2 µ F C11 220nF C12 220nF EXPOUT 11 12 13 14 15 C13 COMP IN 220nF 220nF C9 16 17 18 19 20 C14 NCAN OUT SIDE TONE S12 Philips Semiconductors Product specification SA5753 SR00669 Philips Semiconductors Product specification Audio processor – filter and control section SA5753 Companding and Amplifier Section Filter and Control Section SA5752 SA5753 PREAMP MICROPHONE NOISE CANCEL TX BANDPASS FILTER SUMMING AMP AUDIO TO TRANSMITTER GAIN CONTROL VOX VOX OUTPUT TX PRE– EMPHASIS TX LOW PASS FILTER RX DE– EMPHASIS RX BANDPASS FILTER COMPRESSOR AUDIO FROM RECEIVER DEMODULATOR EXPANDOR DTMF GENERATOR HEADPHONE PA ATTENUATOR I2C BUS INTERFACE CLOCK 1.2MHz PA FROM SYSTEM CONTROLLER I 2 C BUS SPEAKER VOX CONTROL TDA7050T SR00661 Figure 4. Typical Configuration of Audio Processor (APROC) System Chip Set 1997 Nov 07 11 Philips Semiconductors Product specification Audio processor – filter and control section SA5753 DEMOD DATA DATA PROCESSOR POWER SUPPLY TXEN DATA DEMOD SA5752 RF BLOCK MOD POWER SUPPLY ENABLE LOGIC UNIT SA5753 TDA7050 VOX 8 I2C MIC EAR CONTROL UNIT SPEAKER SR00670 Figure 5. APROC Application Diagram 2.5 2.5 2 2 1.5 Icc (mA) Icc (mA) +85°C +25°C 1 -40°C NORMAL 1.5 1 IDLE 0.5 0.5 ICC vs VCC vs TEMP 0 2 2.5 3 3.5 4 VCC (V) 4.5 5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) SR00671 SR00672 Figure 6. SA5753 Normal Operation 1997 Nov 07 POWER DOWN 0 5.5 Figure 7. SA5753 Power Mode Comparison (ICC) 12 Philips Semiconductors Product specification Audio processor – filter and control section SA5753 1000 900 0.8 0.6 -40°C 0.4 0.2 +25°C 0 -0.2 800 NOISE LEVEL (uV) ERROR (dB) 1 +85°C -0.4 -0.6 700 600 500 400 300 200 -0.8 -1 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 100 -8 -6 -4 -2 0 0 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 ATTENUATION LEVEL (dB) POWER SUPPLY (V) SR00674 SR00673 Figure 8. Gain Control, A6 Linearity 1997 Nov 07 Figure 9. Power Supply vs Noise at TXBPF (25°C) 13 Philips Semiconductors Product specification Audio processor — filter and control section SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm 1997 Nov 07 14 SA5753 SOT266-1 Philips Semiconductors Product specification Audio processor — filter and control section SA5753 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1997 Nov 07 15