PHILIPS PHX3055L

Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic full-pack envelope. The
device features high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal cycling performance with low
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general
purpose
switching
applications.
PINNING - SOT186A
PIN
PHX3055L
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Ptot
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
60
9.4
28
0.18
V
A
W
Ω
PIN CONFIGURATION
SYMBOL
DESCRIPTION
d
case
1
gate
2
drain
3
source
g
case isolated
1 2 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
ID
Continuous drain current
IDM
PD
∆PD/∆Ths
VGS
VGSM
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Non-repetitive gate source
voltage
Single pulse avalanche
energy
Peak avalanche current
Ths = 25 ˚C; VGS = 10 V
Ths = 100 ˚C; VGS = 10 V
Ths = 25 ˚C
Ths = 25 ˚C
Ths > 25 ˚C
EAS
IAS
Tj, Tstg
Operating junction and
storage temperature range
MIN.
MAX.
UNIT
-
9.4
5.9
26
28
0.22
± 15
± 20
A
A
A
W
W/K
V
V
-
25
mJ
-
6
A
- 55
150
˚C
tp≤50µs
VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω;
VGS = 10 V
VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω;
VGS = 10 V
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
Visol
R.M.S. isolation voltage from all
three terminals to external
heatsink
f = 50-60 Hz; sinusoidal
waveform;
R.H. ≤ 65% ; clean and dustfree
Cisol
Capacitance from T2 to external f = 1 MHz
heatsink
October 1997
1
MIN.
TYP.
-
-
10
MAX.
UNIT
2500
V
-
pF
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
PHX3055L
THERMAL RESISTANCES
SYMBOL
PARAMETER
Rth j-hs
Thermal resistance junction to
heat sink.
Thermal resistance junction to
ambient
Rth j-a
CONDITIONS
MIN.
TYP.
MAX.
UNIT
-
-
4.5
K/W
-
55
-
K/W
MIN.
TYP.
MAX.
UNIT
ELECTRICAL CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(BR)DSS
VGS = 0 V; ID = 0.25 mA
60
-
-
V
∆V(BR)DSS /
∆Tj
RDS(ON)
VGS(TO)
gfs
IDSS
Drain-source breakdown
voltage
Drain-source breakdown
voltage temperature coefficient
Drain-source on resistance
Gate threshold voltage
Forward transconductance
Drain-source leakage current
VDS = VGS; ID = 0.25 mA
-
0.06
-
V/K
IGSS
Gate-source leakage current
1.0
3.5
-
0.13
1.5
5.5
0.1
1
10
0.18
2.0
25
250
100
Ω
V
S
µA
µA
nA
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 10 A; VDD = 48 V; VGS = 10 V
-
7.5
1.9
5.5
10
3
7
nC
nC
nC
td(on)
tr
td(off)
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 10 A;
RG = 24 Ω; RD = 2.7 Ω
-
12
105
26
35
-
ns
ns
ns
ns
Ld
Internal drain inductance
-
4.5
-
nH
Ls
Internal source inductance
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
290
103
40
-
pF
pF
pF
MIN.
TYP.
MAX.
UNIT
-
-
9.4
A
-
-
48
A
VGS = 10 V; ID = 6 A
VDS = VGS; ID = 0.25 mA
VDS = 50 V; ID = 6 A
VDS = 60 V; VGS = 0 V
VDS = 48 V; VGS = 0 V; Tj = 150 ˚C
VGS = ±30 V; VDS = 0 V
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Ths = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
IS
VSD
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
trr
Reverse recovery time
Qrr
Reverse recovery charge
ISM
October 1997
CONDITIONS
IS = 10 A; VGS = 0 V
-
-
1.5
V
IS = 10 A; VGS = 0 V;
dI/dt = 100 A/µs
-
40
-
ns
-
0.1
-
µC
2
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
120
PHX3055L
Normalised Power Derating
PD%
10
with heatsink compound
110
Zth(j-hs)
Transient Thermal Impedance (K/W)
PHX3055E
0.5
100
90
1
80
70
0.2
0.1
0.05
60
0.1
0.02
0.01
0
50
40
PD
30
tp
D=
tp
T
20
10
0
20
40
60
80
Ths / C
100
120
0.001
140
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Ths)
120
t
T
0
100us 1ms 10ms
tp, pulse width (s)
0.1s
1s
10s
PHP3055E
ID, Drain current (Amps)
15
with heatsink compound
110
10us
Fig.4. Transient thermal impedance.
Zth j-hs = f(t); parameter D = tp/T
Normalised Current Derating
ID%
1us
Tj = 25 C
10 V
7V
100
90
6.5 V
80
70
10
6V
60
50
5.5 V
40
5
5V
30
VGS = 4.5 V
20
10
0
0
20
40
60
80
Ths / C
100
120
0
140
0
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Ths); conditions: VGS ≥ 10 V
5
10
15
20
VDS, Drain-Source voltage (Volts)
ID, Drain current (Amps)
RDS(on), Drain-Source on resistance (Ohms)
0.4
5.5 V
/ID
DS
RD
10
6V
6.5 V
PHP3055E
7V
tp = 10 us
N
O
S(
0.3
100 us
0.2
1 ms
10 V
DC
10 ms
100 ms
1
30
Fig.5. Typical output characteristics.
ID = f(VDS); parameter VGS
100
V
)=
25
0.1
VGS = 15 V
Tj = 25 C
0.1
0
1
10
100
VDS, Drain-source voltage (Volts)
1000
Fig.3. Safe operating area. Ths = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
October 1997
0
5
10
ID, Drain current (Amps)
15
20
Fig.6. Typical on-state resistance.
RDS(ON) = f(ID); parameter VGS
3
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
ID, Drain current (Amps)
VDS = 30 V
15
PHX3055L
VGS(TO) / V
PHP3055E
max.
4
Tj = 25 C
Tj = 175 C
typ.
3
10
min.
2
5
1
0
0
0
2
4
6
VGS, Gate-source voltage (Volts)
8
-60
10
PHP3055E
gfs, Transconductance (S)
-20
0
20
40
60
Tj / C
80
100
120
140
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
4
-40
1E-01
SUB-THRESHOLD CONDUCTION
ID / A
VDD = 30 V
Tj = 25 C
3
1E-02
Tj = 175 C
2%
1E-03
typ
98 %
2
1E-04
1
0
1E-05
1E-06
0
5
10
ID, Drain current (Amps)
0
15
Fig.8. Typical transconductance.
gfs = f(ID); parameter Tj
a
1
2
VGS / V
3
4
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised RDS(ON) = f(Tj)
Ciss, Coss, Crss, Junction capacitances (pF)
1000
PHP3055E
1.5
Ciss
Coss
1.0
100
Crss
0.5
0
-60 -40 -20
0
20
40 60
Tj / C
80
10
100 120 140
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 10 V
October 1997
1
10
VDS, Drain-source voltage (Volts)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
4
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
15
VGS, Gate-Source voltage (Volts)
PHX3055L
PHP3055E
20
PHP3055E
IF, Source-drain diode current (Amps)
VGS = 0 V
ID = 10 A
Tj = 25 C
VDS = 30 V
48 V
15
Tj = 25 C
Tj = 175 C
10
10
5
5
0
0
5
10
Qg, Gate charge (nC)
0
15
Switching times (ns)
PHP3055E
120
VDD = 30 V
VGS = 10 V
RD = 2.7 Ohms
ID = 10 A
Tj = 25 C
100
1.5
EAS, Normalised unclamped inductive energy (%)
110
100
90
80
70
tr
10
0.5
1
VSDS, Source-drain voltage (Volts)
Fig.16. Source-Drain diode characteristic.
IF = f(VSDS); parameter Tj
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
1000
0
60
td(off)
tf
50
40
td(on)
30
20
10
1
0
20
40
60
RG, Gate resistance (Ohms)
80
0
100
20
Fig.14. Typical switching times.
td(on), tr, td(off), tf = f(RG)
1.15
40
60
80
100
Starting Tj ( C)
120
140
Fig.17. Normalised unclamped inductive energy.
EAS% = f(Tj)
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj
+
V(BR)DSS @ 25 C
1.1
VDD
L
1.05
VDS
-
VGS
1
-ID/100
0.9
0.85
-100
RGS
-50
0
50
Tj, Junction temperature (C)
100
R 01
shunt
150
Fig.18. Unclamped inductive test circuit.
EAS = 0.5 ⋅ LID2 ⋅ V(BR)DSS /(V(BR)DSS − VDD )
Fig.15. Normalised drain-source breakdown voltage.
V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj)
October 1997
T.U.T.
0
0.95
5
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
PHX3055L
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
10.3
max
4.6
max
3.2
3.0
2.9 max
2.8
Recesses (2x)
2.5
0.8 max. depth
6.4
15.8
19
max. max.
15.8
max
seating
plane
3 max.
not tinned
3
2.5
13.5
min.
1
0.4
2
3
M
1.0 (2x)
0.6
2.54
0.9
0.7
0.5
2.5
5.08
1.3
Fig.19. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
October 1997
6
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
PHX3055L
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
October 1997
7
Rev 1.000