INTEGRATED CIRCUITS DATA SHEET PCA1070 Multistandard programmable analog CMOS transmission IC Product specification Supersedes data of 1996 Mar 06 File under Integrated Circuits, IC03 1997 Jun 20 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 FEATURES • Line interface with: – Voltage regulator with programmable DC voltage drop – Programmable set impedance – Output to control an external switching MOS transistor for pulse dialling • Facility to regulate parameters with line current: – Value of DC line current (bit code) readable via the I2C-bus – Programmable DC voltage during pulse dialling – Circuitry for short DC settling time – Line loss compensation with fully software programmable characteristics (control range, stop current) of microphone/earpiece/DTMF amplifiers • Interface to peripheral circuits with: – Supply for microcontroller and DTMF diallers – Input to sense supply voltage of microcontroller and output for reset of microcontroller – Fully software programmable control of sidetone balance and DC voltage drop as a function of line length. – I2C-bus (programming of parameters, control of all logic signals) – High impedance DTMF signal input APPLICATIONS – Input for external oscillator signal with on-chip DC blocking • Wired telephony (basic till feature phones) – Power-down via the I2C-bus • Combi-terminals (e.g. telephone and answering machine or FAX) – Stabilized supply for electret microphone • Modems and base units of cordless telephones. • Microphone and DTMF amplifiers: – Low-noise microphone preamplifier suitable for various types of microphones GENERAL DESCRIPTION The PCA1070 is a CMOS integrated circuit performing all speech and line interface functions in fully electronic telephone sets. The device requires a minimum of external components. The transmission parameters are programmable via the I2C-bus. This makes the IC adaptable to nearly all worldwide country requirements and to a various range of speech transducers, without changing the (few) external components. – Symmetrical high impedance microphone preamplifier inputs – Programmable gain for microphone and DTMF channels – Sending mute via the I2C-bus to disable microphone amplifier and enable DTMF amplifier – Sending mute also to be used as privacy switch The parameters are stored in the EEPROM of a microcontroller and are loaded into the PCA1070 during the start-up phase of the transmission IC after hook-off. – Dynamic limiting (speech controlled) to prevent distortion of line signal and sidetone; programmable maximum sending level • Receiving amplifier: The PCA1070 also allows adaptation to the connected telephone line by reading the line current via the I2C-bus and processing it in the microcontroller. – Suitable for various types of earpieces (including piezo) – Programmable gain and hearing protection level – Receiving mute via the I2C-bus to disable receiving amplifier and enable DTMF confidence tone – On-chip anti-sidetone circuit with programmable sidetone balance – Confidence tone in the earpiece during DTMF dialling 1997 Jun 20 2 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION PCA1070P DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1 PCA1070T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 BLOCK DIAGRAM positive line handbook, full pagewidth peripheral supply SLPE LN REG LSI DOC V DD VMC RMC OREC(1) Vref 24 2 4 3 23 22 18 8 7 5 TX 1 14 QR LINE INTERFACE BIAS AND REFERENCE POWER CONTROL SCR 6 BTL RECEIVE OUTPUT 15 QR VSLPE Zset DST VSS 13 PRES maximum level load select PD DPI RRG (0 dB) ANTI SIDETONE PCA1070 sidetone balance Iline RECEIVE PROG-AMP (-6 dB)(2) (−25 dB) SEND PROG-AMP (15 dB)(2) gain Gra receive mute 17 DTMF GAIN CONTROL MICROPHONE SUPPLY gain Gma (0 dB) line current DYNAMIC LIMITER 10 V P 12 MIC MICROPHONE PREAMPLIFIER (20 dB) (0 dB) 11 MIC CLOCK INTERFACE 2 I C-BUS INTERFACE TEST CONTROL send mute threshold 19 21 20 16 9 CLK SDA SCL TST(1) OMIC(1) (1) Test pins. (2) Default value. Fig.1 Block diagram. 1997 Jun 20 3 MLA944 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 PINNING SYMBOL PIN DESCRIPTION TX 1 drive output REG 2 voltage regulator decoupling DOC 3 dial output connection LSI 4 line signal input LN 5 positive line terminal SCR 6 sending current resistor Vref 7 OREC OMIC VP TX 1 24 SLPE voltage reference decoupling REG 2 23 VDD 8 output receiving preamplifier; to be left open-circuit in application DOC 3 22 VMC 9 output microphone preamplifier; to be left open-circuit in application LSI 4 21 SDA LN 5 20 SCL SCR 6 10 supply for electret microphones MIC− 11 inverting input microphone preamplifier MIC+ 12 non-inverting input microphone preamplifier VSS 13 negative line terminal QR+ 14 non-inverting output of receiving amplifier QR− 15 inverting output of receiving amplifier TST 16 test pin; to be connected to VSS in application DTMF 17 dual tone multi-frequency input RMC 18 reset output for microcontroller CLK 19 clock signal input SCL 20 serial clock line input; I2C-bus SDA 21 serial data line input/output; I2C-bus VMC 22 input to sense supply voltage microcontroller VDD 23 positive supply decoupling SLPE 24 slope (DC resistance) adjustment 1997 Jun 20 handbook, halfpage 19 CLK PCA1070 Vref 7 18 RMC OREC 8 17 DTMF OMIC 9 16 TST VP 10 15 QR− MIC− 11 14 QR+ MIC+ 12 13 VSS MGE338 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 FUNCTIONAL DESCRIPTION All values in the Chapter “Functional description” are typical unless stated otherwise. handbook, halfpage RLN-SLPE Line interface LN CP CREG CLSI Ca Ra DC VOLTAGE DROP SLPE Power for the PCA1070 and its peripheral circuits is obtained from the telephone line. The IC develops its own supply voltage at VDD and regulates its DC voltage drop between pins SLPE and VSS. This voltage (VSLPE) can be programmed via the I2C-bus interface between 3.1 to 5.9 V and is default at 4.7 V (see Table 8). REG LSI Leq VSLPE Zset C Rb RP RLSI MGE342 The DC line voltage at pin LN can be calculated using the following equation: VSS Fig.3 Equivalent impedance ZLN. VLN = VSLPE + (Iline − ILN) × RLN-SLPE where: where: ILN = DC bias current flowing into pin LN (≈3 mA if Iline > 17 mA) Ca = DC blocking capacitor (influence negligible at f ≥ 300 Hz for given value of CLSI) RLN-SLPE = external 20 Ω resistor between LN and SLPE. CLSI = capacitor at pin LSI (100 nF) CP = internal capacitor (12 nF) At line currents below 6 mA the DC voltage VSLPE is automatically adjusted to a lower value. This means that the operation of more sets, connected in parallel, is possible with reduced sending and receiving levels and relaxed performance. At line currents below 16 mA the DC bias current ILN is reduced from ≈3 mA to a lower value to ensure maximum possible transmit level capability under all line current conditions. CREG = capacitor at pin REG (470 nF) Leq = artificial inductor (= RP × RLN-SLPE × CREG = 10.1 H at VSLPE = 4.7 V) RLN-SLPE = DC slope resistance (20 Ω) RP = internal resistor (1075 kΩ at VSLPE = 4.7 V) RLSI = internal resistor (240 kΩ). SUPPLY FOR PERIPHERAL CIRCUITS SET IMPEDANCE The supply voltage VDD can be used for peripheral circuitry. The supply capabilities depend on the programmed DC voltage drop VSLPE and on several other parameters as given in the following equation: In normal conditions Iline >> ILN and the static behaviour is equivalent to a voltage regulator diode with a series resistor RLN-SLPE. In the audio frequency range the dynamic impedance ZLN is determined mainly by the internal component Zset = Ra + (Rb // C). The equivalent impedance ZLN is shown in Fig.3. The values of Ra, Rb and C can be programmed via the I2C-bus interface (see Tables 9, 10 and 11). VDD = VSLPE − (IDD + Ip + IVP) × RSLPE−VDD where: IDD = internal current consumption PCA1070 (2.3 mA) Ip = current to peripheral circuitry IVP = current taken from VP for electret microphone RSLPE−VDD = external resistor between SLPE and VDD. 1997 Jun 20 5 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 DC STARTING AND SETTLING TIME The IC is equipped with circuitry for fast DC start-up. This circuit is automatically activated as soon as VDD reaches 3 V after hook-off, and is deactivated when VSLPE drops below 5.9 V. This ensures that only a relatively short time is needed to reach the default DC setting (VSLPE) of the circuit and that VDD will not exceed the maximum permitted voltage of 6 V. handbook, halfpage MGE339 VVMC low voltage condition VRESET 0 The start-up circuit can also be activated under software control by setting bit code DST to logic 1 via the I2C-bus. The start-up time can be optimized by programming the bit code DST to logic 1 during the start-up procedure. In practice this is possible as soon as the microcontroller has become operational. The DST bit can also be used to quickly restore the DC settings (VSLPE) after long line breaks or during reprogramming of VSLPE. RMC logic 1 logic 0 It should be noted that the AC impedance into pin LN is reduced considerably when DST = 1. Fig.4 VMC timing diagram. Power control POWER-DOWN/STANDBY MODES INTERNAL RESET PCA1070 The circuit can be set in power-down or standby mode. These modes are intended for use with pulse dialling during long line breaks and applications with memory retention. The PCA1070 has an internal reset circuit that monitors the supply voltage VDD. If VDD is below the threshold level (1.2 V) then the circuit is in reset-mode. In this mode the current consumption is low and the internal reset is active and writes the default values into all registers. The status bit PRES will be set to logic 1. The microcontroller can read this bit via the I2C-bus interface; once read it will be set to logic 0 again. With control bits PDx = 01, the circuit is in the power-down mode; the typical current consumption at pin VDD is reduced from IDD = 2.3 mA to 30 µA; the typical current consumption at pin VMC is 4 µA. When PDx = 11 the circuit is in the standby mode and IDD and IVMC are reduced to 2 µA. In both conditions (power-down and standby) the voltage stabilizer will be disabled. When VDD passes the threshold (increasing VDD), the circuit becomes partly active and the internal ring/speech detector will be activated (see Section “Start-up and switch-off behaviour”). START-UP AND SWITCH-OFF BEHAVIOUR This description refers to the basic application where VDD and VMC are connected together and one supply capacitor is used (see Fig.8). RESET OUTPUT FOR MICROCONTROLLER The voltage at pin VMC (microcontroller supply voltage) is monitored by a reset circuit. If VVMC is below the threshold level the output RMC is set to logic 1. This threshold level is 2 V in the normal operating and power-down mode and 2.1 V in the standby mode (see Fig.4). 1997 Jun 20 6 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 Speech condition DIAL PULSE INPUT (DPI) After hook-off, line current will be applied to the line input LN and the supply capacitor connected to VDD and VMC will be charged. The DPI bit controls output DOC (open-drain) that drives the gate of an external MOS interrupter transistor. DPI is controlled via the I2C-bus interface. The internal reset signal will change from logic 1 to logic 0 when VDD passes the threshold level (1.2 V) and the circuit becomes partly active [the line interface part is kept in power-down mode, so that all of the line current is available to charge the supply capacitor(s)]; The PCA1070 can receive data via the I2C-bus (standard I2C specifications are fulfilled for VDD ≥ 2.5 V; relaxed performance for VDD = 1.8 to 2.5 V). If DPI is set to logic 1, pin DOC will be pulled down to switch-off the MOSFET to generate a line break. If DPI = 0 pin DOC is high-ohmic and the interrupter transistor will conduct the line current. Sending channel The PCA1070 has symmetrical microphone inputs and accepts input signals of maximum 70 mV (peak) for THD = 2% (VDD ≥ 2.5 V). Its input impedance is 100 kΩ and its gain is default 41 dB. Dynamic, magnetic, piezoelectric and electret (with built-in FET source follower) microphones can be used. Some possible microphone arrangements are shown in Fig.5. When VVMC passes the microcontroller reset level of 2 V (2.1 V in standby mode) the output RMC changes from logic 1 to logic 0 and the circuit is switched to the normal operating mode. After hook-on VVMC decreases and the output RMC will change from logic 0 to logic 1 when VVMC passes the threshold level, however the PCA1070 will stay in the normal operating mode until the internal reset at 1.2 V takes place. The gain of the sending channel can be programmed between 30 dB and 51 dB in 1 dB steps using bit code GMAx (6 bits). The gain of the microphone preamplifier is 20 dB (with dynamic limiter not active) and GMAx sets the gain of the ‘sending prog-amp’ (allowed range Gma = 4 to 25 dB). The gain of the line interface is 6 dB. By decreasing VDD the internal reset signal will change from logic 0 to logic 1 when VDD passes 1.2 V and the circuit will go into the reset mode (line interface part in power-down and all programmable parameters reset to default values). Thus the total gain of the sending channel (GM) is as follows: GM = 20 + Gma + 6 (dB) Default: GM = 20 + 15 + 6 = 41 dB Ringer condition Where Gma = ‘gain sending prog-amp’. In this condition the supply capacitor connected to VDD and VMC is charged by the rectified ringer signal; no line current is applied to pin LN. Programming the gain of the ‘sending prog-amp’ is given in Table 13. VDD and VVMC are increasing and when VDD passes the internal reset threshold level (1.2 V), the internal ring/speech-detector will be activated and the circuit will switch to the standby condition (IDD < 5 µA; IVMC < 5 µA) before the voltage at VMC reaches the threshold level for microcontroller reset. When VVMC passes this threshold level (2.1 V) output RMC changes from logic 1 to logic 0 and the circuit will stay in the standby mode until line current is applied to pin LN. By setting the ‘Reset Ring’ control bit (RRG) to logic 1 via the I2C-bus interface, the ring/speech detector will be disabled. 1997 Jun 20 7 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC handbook, full pagewidth MIC+ MIC− PCA1070 VP VP VP MIC+ MIC+ MIC+ MIC− MIC− MIC− VSS VSS VSS (b) (a) (c) (d) MGE341 (a) Dynamic or piezo. (b) Low impedance electret with built-in pre-amplifier. (c) High impedance electret with built-in pre-amplifier. (d) Symmetrical connection of electret. Fig.5 Microphone arrangements. Dynamic limiter DTMF channel To prevent distortion of the transmitted speech signal, the gain of the microphone amplifier is reduced rapidly when signal peaks on the line exceed an internally determined threshold level. The time in which the gain is reduced, the attack time, is very short. The circuit stays in this gain-reduced condition until the peaks of the sending signal remain below the threshold level. The sending gain then returns to normal after a time also determined on the chip, the release time. The threshold level of the AC peak-to-peak line voltage on pin LN is default at 3.5 V (p-p). A level of 2.6 V (p-p) can be programmed by setting bit code DLT to logic 1. The PCA1070 has an asymmetrical DTMF input. Its input impedance is 200 kΩ // 45 pF and its gain is default at 21 dB. DTMF signals can be sent to the line by setting control bit ‘Sending Mute’ (SM) to logic 1 (default SM = 0); by setting ‘Receiving Mute’ (RM) also to logic 1 (default RM = 0), the dialling tones are also sent to the receiving output to generate a confidence tone in the earpiece. The gain between the DTMF input and the line LN can be programmed between 1 dB and 21 dB in 1 dB steps using bit code GMAx (6 bits). The confidence tone gain (between DTMF input and earpiece outputs QR) can be programmed between −40 dB and −19 dB (symmetrical drive of earpiece) using bit code GRAx (6 bits). GMAx sets the gain of the ‘sending prog-amp’ (recommended range in DTMF mode for Gma = −5 to 15 dB) and GRAx sets the gain of the ‘rec prog-amp’ (allowed range Gra = −25 to 0 dB). The internal threshold level is lowered automatically if the DC voltage setting of the circuit (VSLPE) is not high enough to reach the programmed level. Also when the DC current in the transmit output stage is insufficient to drive the line load, the internal threshold level is lowered automatically. Dynamic limiting considerably improves sidetone performance in over-drive conditions (less distortion and limited sidetone level). 1997 Jun 20 8 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 The total gain of the DTMF channel between the DTMF input and the line LN is as follows: The gain of the receiving channel can be programmed between −19 dB and +11 dB (symmetrical drive) in 1 dB steps using bit code GRAx (6 bits). GDTMF = Gma + 6 (dB) GRAx sets the gain of the ‘rec prog-amp’ (allowed range Gra = −19 dB to +11 dB; default Gra = −6 dB). Default GDTMF = 15 + 6 = 21 dB The confidence tone gain (DTMF to QR outputs) is: The total gain of the receiving channel is as follows: With symmetrical drive of earpiece GCTs = Gra − 19 (dB) Symmetrical drive GRS = Gra (dB) Default GCTss = −6 − 19 = −25 dB. Default GRS = −6 dB. At low gain settings (Gra < −10 dB), the confidence tone gain will be slightly higher than the calculated value. This is caused by a residual signal. Asymmetrical or single-ended drive GRA = GRS − 6 (dB) Default Gra = −6 − 6 (dB) = −12 dB. Programming the gain of the ‘sending prog-amp’ and the ‘rec prog-amp’ is given in Table 13. Programming the gain Gra of the ‘rec prog-amp’ is given in Table 13. Receiving channel Sidetone balance The gain of the receiving channel is defined between the line connection LN and the earpiece outputs QR+ and QR−. Its voltage gain is default −6 dB (differential drive). The LN terminal accepts receiving signals up to 1 V (RMS) for THD = 2%. The outputs may be used to connect dynamic, magnetic or piezoelectric earpieces with single-ended or differential drive. The load select bit RFC is set default to logic 1 to guarantee stable operation in case of a capacitive load (piezoelectric earpiece). With a resistive load (dynamic capsule) RFC should be set to logic 0 via the I2C-bus interface to obtain optimum performance with respect to distortion and bandwidth. The PCA1070 has an on-chip anti-sidetone circuit. An internal balance impedance Zoss can be programmed via the I2C-bus interface to match the external line impedance Zline to give optimum sidetone suppression. Zoss = Rsa + (Rsb // Cs). Programming the sidetone balance impedance is given in Tables 14, 15 and 16. Line current control The DC line current can be read via the I2C-bus interface. This information can be used for the adaptation of transmission parameters (for example line loss compensation, sidetone balance and DC characteristic). Two levels for hearing protection can be selected via the I2C-bus interface with control bit HPL. The earpiece arrangements are illustrated in Fig.6. The bit code LCx as a function of line current is given in Table 17. handbook, halfpage QR+ QR+ QR− QR− VSS MGE340 (a) (b) symmetrical single-ended Fig.6 Earpiece arrangements. 1997 Jun 20 9 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 I2C-BUS PROGRAMMING Table 1 Programmable parameters The following parameters (see Fig.1) can be programmed by means of a bit code via the I2C-bus: SYMBOL PARAMETER BLOCK BITS VDCx VSLPE line interface 3 DC voltage SLPE-VSS ZSAx set impedance line interface 3 Ra of set impedance line interface 3 Rb of set impedance ZSBx ZSPx DESCRIPTION line interface 4 fp (pole frequency) of set impedance DST DST line interface 1 DC Start Time PDx PD power control 2 Power-Down DPI DPI power control 1 Dial Pulse Input RRG RRG power control 1 Reset RinG detector HPL maximum receiving level BTL receiving output 1 Hearing Protection Level RFC load select BTL receiving output 1 Resistive/Capacitive load ZOSAx anti-sidetone 4 Rsa of sidetone impedance ZOSBx sidetone impedance anti-sidetone 4 Rsb of sidetone impedance ZOSPx anti-sidetone 4 Cs of sidetone impedance RM receiving mute receiving mute 1 Receiving Mute GRAx gain Gra receiving prog-amp 6 Gain receiving prog-amp GMAx gain Gma sending prog-amp 6 Gain sending prog-amp SM sending mute sending mute 1 Sending Mute DLT threshold dynamic limiter 1 Dynamic Limiter Threshold Table 2 Readable parameters The following parameters (see also Fig.1) can be read as a bit code via the I2C-bus: SYMBOL PARAMETER BLOCK BITS PRES power control 1 PCA1070 Reset line current gain control 5 Line Current PRES LCx DESCRIPTION I2C interface The I2C-bus interface (see “The I2C-bus and how to use it” 12NC: 9398 393 40011) is used to program the transmission parameters and control functions. Table 3 Device address A6 A5 A4 A3 A2 A1 A0 R/W 0 1 0 0 0 1 0 X All functions can be accessed by writing an 8-bit word to the PCA1070. In order to set up the PCA1070, a control message consisting of the device address, a R/W bit, a subaddress byte and one or more data bytes must be written to the PCA1070. If more than one data byte follows the subaddress, these bytes are stored in the successive registers by the automatic increment feature. 1997 Jun 20 10 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC Table 4 The control word format for the slave receiver DEVICE ADDRESS S 0 PCA1070 1 0 0 0 1 0 SUB ADDRESS 0(1) DATA/CONTROL BYTE A I7 I6 I5 I4 I3 I2 I1 I0 A D7 D6 D5 D4 D3 D2 D1 D0 A P Note 1. This bit is R/W. Table 5 Bit arrangement of each data byte used in the control word: PCA1070 receive (see note 1) FUNCTION SUB ADDRESS D7 D6 D5 D4 D3 VDC2 VDC1 VDC0 DC voltage H00 Sidetone and set impedance H01 ZOSB3 ZOSB2 ZOSB1 ZOSB0 H02 ZOSP3 ZOSP2 ZOSP1 ZOSP0 ZSB2 ZSB1 ZSB0 GMA5 GRA5 H03 Sending channel H04 DLT Receiving channel H05 RFC HPL Control H06 PD1 PD0 D2 D1 D0 DST ZOSA3 ZOSA2 ZOSA1 ZOSA0 ZSA2 ZSA1 ZSA0 ZSP3 ZSP2 ZSP1 ZSP0 GMA4 GMA3 GMA2 GMA1 GMA0 GRA4 GRA3 GRA2 GRA1 GRA0 RRG RM SM DPI Note 1. The bits that are not indicated must be set to logic 0. Table 6 The control word format for the slave transmitter DEVICE ADDRESS S 0 1 0 0 0 1 DATA/STATUS BYTE 0 1(1) A D7 D6 D5 D4 D3 D2 D1 D0 A P Note 1. Change in direction of R/W bit. Table 7 PCA1070 send FUNCTION PCA1070 status D7 D6 D5 D4 D3 D2 D1 D0 PRES(1) − − LC4(2) LC3(2) LC2(2) LC1(2) LC0(2) Notes 1. Indicates if PCA1070 has received internal reset; PRES will be set to logic 1 with internal reset and is set to logic 0 after reading the register via the I2C-bus. 2. Information about value of line current. 1997 Jun 20 11 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 WRITE AND READ TABLES DC voltages Table 8 DC voltage at pin SLPE VDC2 VDC1 VDC0 VSLPE (V) 0 0 0 3.1 0 0 1 3.5 0 1 0 3.9 0 1 1 4.3 1 0 0 4.7 1 0 1 5.1 1 1 0 5.5 1 1 1 5.9 REMARK default Set impedance Programming the impedance in the audio frequency range seen at pin LN: Ra + (Rb // C) Table 9 Programming Ra ZSA2 ZSA1 ZSA0 Ra (Ω) 0 0 0 0 0 0 1 100 0 1 0 200 0 1 1 300 1 0 0 400 1 0 1 500 note 1 1 1 X 600 notes 1 and 2 REMARK default Notes 1. For Zset combinations where Ra = 0 only Rb = 600 Ω is allowed. If Ra ≥ 500 Ω it is obligatory that Rb = 0. This is to safeguard stable operation of the line interface under all practical conditions. If Zref requires Ra = 0 and Rb ≠ 600 Ω use Ra = 100 Ω instead and reduce the original Rb by 100 Ω. 2. X = don’t care. 1997 Jun 20 12 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 Table 10 Programming Rb Rb (Ω) REMARK 0 0 note 1 1 600 1 0 700 0 1 1 800 default 1 X 0 900 note 2 1 X 1 1000 note 2 ZSB2 ZSB1 ZSB0 0 0 0 0 0 Notes 1. For Zset combinations where Ra = 0 only Rb = 600 Ω is allowed. If Ra ≥ 500 Ω it is obligatory that Rb = 0. This is to safeguard stable operation of the line interface under all practical conditions. If Zref requires Ra = 0 and Rb ≠ 600 Ω use Ra = 100 Ω instead and reduce the original Rb by 100 Ω. 2. X = don’t care. Table 11 Programming pole frequency: CORRESPONDING VALUE OF C (nF)(1) ZSP3 ZSP2 ZSP1 ZSP0 fp (Hz) Rb (600 Ω) Rb (700 Ω) Rb (800 Ω) Rb (900 Ω) Rb (1000 Ω) 0 0 0 0 828 320 275 240 214 192 0 0 0 1 1095 242 207 182 161 145 0 0 1 0 1448 183 157 137 122 110 0 0 1 1 1915 139 119 104 92 83 0 1 0 0 2533 105 90 79 70 63 0 1 0 1 3350 79 68 59 53 48 0 1 1 0 4430 60 51 45 40 36 0 1 1 1 5859 45 39 34 30 27 1 X X X 12000 22 19 17 15 13 Notes 1. 1 C = ------------------------------2π × R b × f p 2. X = don’t care. Reset functions Monitoring of internal reset PCA1070. Table 12 Status bit PRES PRES DESCRIPTION 1 internal reset has occurred; default values in all registers 0 register has been read via the I2C-bus interface 1997 Jun 20 13 REMARK default note 2 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 Programmable amplifier (prog-amp) An identical programmable amplifier called ‘prog-amp’ is used both in the sending and receiving channel. The bit codes GMAx and GRAx are given in Table 13. The permitted adjustment range differs for the two amplifiers and is also different for DTMF and speech mode. This is indicated in the corresponding sections. Table 13 Bit code prog-amp GAIN GMA5 GMA4 GMA3 GMA2 GMA1 GMA0 (dB) GRA5 GRA4 GRA3 GRA2 GRA1 GRA0 GAIN GMA5 GMA4 GMA3 GMA2 GMA1 GMA0 (dB) GRA5 GRA4 GRA3 GRA2 GRA1 GRA0 −25 1 1 1 0 0 1 +0 0 0 0 0 0 0 −24 1 1 1 0 0 0 +1 0 0 0 0 0 1 −23 1 1 0 1 1 1 +2 0 0 0 0 1 0 −22 1 1 0 1 1 0 +3 0 0 0 0 1 1 −21 1 1 0 1 0 1 +4 0 0 0 1 0 0 −20 1 1 0 1 0 0 +5 0 0 0 1 0 1 −19 1 1 0 0 1 1 +6 0 0 0 1 1 0 −18 1 1 0 0 1 0 +7 0 0 0 1 1 1 −17 1 1 0 0 0 1 +8 0 0 1 0 0 0 −16 1 1 0 0 0 0 +9 0 0 1 0 0 1 −15 1 0 1 1 1 1 +10 0 0 1 0 1 0 −14 1 0 1 1 1 0 +11 0 0 1 0 1 1 −13 1 0 1 1 0 1 +12 0 0 1 1 0 0 −12 1 0 1 1 0 0 +13 0 0 1 1 0 1 −11 1 0 1 0 1 1 +14 0 0 1 1 1 0 0 0 1 1 1 1 −10 1 0 1 0 1 0 +15(2) −9 1 0 1 0 0 1 +16 0 1 0 0 0 0 −8 1 0 1 0 0 0 +17 0 1 0 0 0 1 −7 1 0 0 1 1 1 +18 0 1 0 0 1 0 −6(1) 1 0 0 1 1 0 +19 0 1 0 0 1 1 −5 1 0 0 1 0 1 +20 0 1 0 1 0 0 −4 1 0 0 1 0 0 +21 0 1 0 1 0 1 −3 1 0 0 0 1 1 +22 0 1 0 1 1 0 −2 1 0 0 0 1 0 +23 0 1 0 1 1 1 −1 1 0 0 0 0 1 +24 0 1 1 0 0 0 −0 1 0 0 0 0 0 +25 0 1 1 0 0 1 Notes 1. Default value ‘rec prog-amp’ GRAx. 2. Default value ‘sending prog-amp’ GMAx. 1997 Jun 20 14 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 Sidetone balance impedance Table 15 Programming Rsb Internal balance impedance Zoss to match the external line impedance Zline to give optimum sidetone suppression. Zoss = Rsa + (Rsb // Cs). ZOSB MSB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 The optimum setting of Rsa depends on the value of the set impedance. To safeguard stable operation of the anti-sidetone circuit under all practical conditions, the following condition must be fulfilled: Rsa ≥ 0.5Ra. Table 14 Programming Rsa ZOSA3 ZOSA2 ZOSA1 ZOSA0 Rsa (Ω) LSB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 134 0 0 0 1 153 0 0 1 0 193 0 0 1 1 221 0 1 0 0 246 0 1 0 1 277 0 1 1 0 295 0 1 1 1 341 1 0 0 0 369 Note 1 0 0 1 443 1. Default value. 1 0 1 0 492(1) 1 0 1 1 − 1 1 0 0 − 1 1 0 1 − MSP 1 1 1 0 − 1 1 1 1 − 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 465 637 710 803 893 1003 1259(1) 1410 1572 1773 1978 2216 − − − − Table 16 Programming Cs ZOSP Note 1. Default value. LSP 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Note 1. Default value. 1997 Jun 20 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Rsb (Ω) 15 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Cs (nf) 5 55 58 69 76 85 96 105 121 134(1) 145 166 186 207 232 259 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 Line current control Table 17 Bit code LCx and DC line current LC4 LC3 LC2 LC1 LC0 Iline (typ.) (mA) 0 0 0 0 0 <12.5 0 0 0 0 1 15.0 0 0 0 1 0 17.5 0 0 0 1 1 20.0 0 0 1 0 0 22.5 0 0 1 0 1 25.0 0 0 1 1 0 27.5 0 0 1 1 1 30.0 0 1 0 0 0 32.5 0 1 0 0 1 35.0 0 1 0 1 0 37.5 0 1 0 1 1 40.0 0 1 1 0 0 42.5 0 1 1 0 1 45.0 0 1 1 1 0 47.5 0 1 1 1 1 50.0 1 0 0 0 0 52.5 1 0 0 0 1 55.0 1 0 0 1 0 58.0 1 0 0 1 1 61.0 1 0 1 0 0 64.0 1 0 1 0 1 66.5 1 0 1 1 0 69.0 1 0 1 1 1 71.5 1 1 0 0 0 74.0 1 1 0 0 1 77.5 1 1 0 1 0 80.0 1 1 0 1 1 82.5 1 1 1 0 0 85.0 1 1 1 0 1 88.0 1 1 1 1 0 91.0 1 1 1 1 1 >94.0 1997 Jun 20 16 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VLN positive line voltage at pin LN −0.8 +12 V Vi input voltage on pins SLPE, DOC, REG, TX and LSI −0.8 +12 V VDD supply voltage −0.8 +7.0 V Vn voltage on all other pins −0.8 +7.0 V Ii input current −10 +10 mA Ptot total power dissipation − 250 mW Tstg storage temperature −40 +125 °C Tamb operating ambient temperature −10 +60 °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1997 Jun 20 PARAMETER VALUE UNIT DIP24 54 K/W SO24 74 K/W thermal resistance from junction to ambient in free air 17 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 TEST CONDITIONS AND PARAMETER SETTINGS FOR THE CHARACTERISTICS Table 18 Test conditions SYMBOL VALUE UNIT Iline 20 mA VSS 0 V f 1000 Hz Ip 0 A IVP 0 A fclk 3.597545 MHz Tamb 25 °C 220 Ω + 820 Ω // 115 nF Zline Rm 150 Ω Rt 150 Ω Table 19 Test settings and control bits. All values, except RFC, are default. Programmable via the I2C-bus; bit codes are given in Chapter “I2C-bus programming”. 1997 Jun 20 SYMBOL VALUE VDCx 100 ZSAx 010 ZSBx 011 ZSPx 0011 GMAx 001111 GRAx 100110 ZOSAx 1010 ZOSBx 0110 ZOSPx 1001 DST 0 DLT 0 RFC 0 HPL 0 PDx 00 RRG 0 RM 0 SM 0 DPI 0 18 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 CHARACTERISTICS All parameters are measured in the test circuit of Fig.7 under the conditions specified in Tables 18 and 19; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC line interface: LN, TX, SLPE and REG Iline line current operating range reduced sending level 17 − 140 mA 12 − 17 mA VSLPE DC voltage at SLPE with or without clock 4.3 4.7 5.1 V VSLPE(min) minimum selectable value VDCx = 000 2.8 3.1 3.4 V VSLPE(max) maximum selectable value VDCx = 111 5.4 5.9 6.4 V VSLPE(step) step resolution − 0.4 − V VSLPE DC voltage at SLPE with or without clock; fast start-up; DST = 1 − 4.7 − V VSLPE(min) minimum selectable value fast start-up; DST = 1; VDCx = 000 − 3.1 − V VSLPE(max) maximum selectable value fast start-up; DST = 1; VDCx = 111 − 5.9 − V VSLPE(step) step resolution fast start-up; DST = 1 − 0.4 − V ∆VSLPE variation with temperature at Tamb = −10 °C to +60 °C with respect to 25 °C − ±20 − mV VLN DC line voltage at LN with or without clock 4.6 5.0 5.4 Iline = 12 mA VLN tDC DC line voltage at LN at low line current DC start-up time 4.83 V V Iline = 120 mA 6.5 7.0 7.5 V with or without clock; Iline = 0.25 mA − 1 − V Iline = 2 mA − 1.9 − V Iline = 4 mA − 3.4 − V Iline = 7 mA − 4.73 5.2 V CVDD = 470 µF; no clock; note 1 − 145 − ms external PNP disconnected; VSLPE = 2 V; VREG = 1.5 V; VDD = VVMC = 2.5 V; ITX = 0 mA − 1.45 − V VSLPE = 3 V; VREG = 2.5 V; VDD = VVMC = 2.5 V; ITX = 1.6 mA − 2.2 − V VSLPE steps from 3.1 V to 5.9 V; note 2 − 65 − ms VSLPE steps from 5.9 V to 3.1 V; note 2 − 65 − ms fast start-up; DST = 1; VSLPE steps from 3.1 V to 5.9 V; note 2 − 0.5 − ms fast start-up; DST = 1; VSLPE steps from 5.9 V to 3.1 V; note 2 − 1 − ms TX: DRIVE OUTPUT FOR EXTERNAL PNP VTX tSW 1997 Jun 20 output voltage at TX switching time DC voltage at SLPE 19 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC SYMBOL PARAMETER PCA1070 CONDITIONS MIN. TYP. MAX. UNIT Supplies: VDD, VMC, VP and SLPE VDD operating supply voltage note 3 2.5 − 6 V relaxed performance; note 4 1.8 − 2.5 V VDD; SUPPLY PIN IDD internal current consumption VDD = 2.5 V − 2.3 − mA power-down; PDx = 01; SCL = 1; SDA = 1 − 30 100 µA standby; PDx = 11; SCL = 1; SDA = 1 − 2 5 µA VDD = 2.9 V; RM = 1; SM = 1 − 4.9 − mA VDD = 2.5 V; RM = 1; SM = 1 − 6.5 − mA VVMC = 2.5 V − 4 10 µA power-down; PDx = 01; VVMC = 2.5 V; SCL = 1; SDA = 1 − 4 10 µA standby; PDx = 11; VVMC = 2.5 V; SCL = 1; SDA = 1 − 2 5 µA VDD: PERIPHERAL SUPPLY Ip current available for peripheral circuitry VMC: SENSE INPUT MICROCONTROLLER SUPPLY VOLTAGE IVMC input current VP: SUPPLY OUTPUT FOR ELECTRET MICROPHONE VP output voltage IVP = 500 µA 1.6 1.9 − V ZVP output impedance f = 300 Hz − 40 − Ω PSRVP power supply rejection f = 300 Hz; note 5 − 65 − dB Tamb = −10 to +60 °C; note 6 1.0 1.2 1.4 V 1.8 2.0 2.2 V Reset functions: VDD, VMC and RMC INTERNAL RESET VDD(sw) switching level of VDD below which internal reset is active RMC: RESET OUTPUT FOR MICROCONTROLLER VVMC(sw) ∆VVMC/∆T 1997 Jun 20 voltage level at pin VMC note 7 where RMC changes state power-down; PDx = 01; note 7 voltage variation with ambient temperature 1.8 2.0 2.2 V standby; PDx = 11; note 7 1.8 2.1 2.4 V Tamb = −10 to +60 °C − 0 − mV/°C power-down; PDx = 01; Tamb = −10 to +60 °C − 0 − mV/°C standby; PDx = 11; Tamb = −10 to +60 °C − +3 − mV/°C 20 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC SYMBOL PARAMETER PCA1070 CONDITIONS MIN. TYP. MAX. UNIT Sending channel: MIC+, MIC−, DTMF, OMIC, LN, SCR, REG and LSI MIC+ AND MIC−: MICROPHONE INPUTS ZMIC input impedance differential 60 100 − kΩ single-ended 30 50 − kΩ note 8 − 72 − dB CMRRMIC common mode rejection ratio VMIC(peak) allowed input signal voltage level (peak value) − − 70 mV GM gain MIC+/MIC− to LN 39.5 41 42.5 dB GM(min) minimum selectable gain GMAx = 000100 28.5 30 31.5 dB GM(max) maximum selectable gain GMAx = 011001 49.5 51 52.5 dB GM(step) step resolution − 1 − dB ∆GM gain variation with frequency − − +0.3/−0.7 dB gain variation with ambient at Tamb = −10 to +60 °C with respect to 25 °C temperature − ±0.2 − dB gain variation with line current at Iline = 100 mA with respect to 20 mA; note 9 − 0 ±0.5 dB AC start-up time CVDD = 470 µF; note 10 − 150 − ms SM = 1 − 100 − dB tACM at f = 300 Hz and 3400 Hz with respect to 1 kHz; note 9 Sending mute/privacy switch ∆GM reduction of GM DTMF: DUAL TONE MULTI-FREQUENCY INPUT RDTMF parallel input resistance SM = 1 100 200 − kΩ CDTMF parallel input capacitance SM = 1 − 45 − pF GDTMF gain from DTMF to LN SM = 1 20 21 22 dB GDTMF(min) minimum selectable gain SM = 1; GMAx = 100101 0 1 2 dB GDTMF(max) maximum selectable gain SM = 1; GMAx = 001111 20 21 22 dB GDTMF(step) step resolution SM = 1 − 1 − dB ∆GDTMF gain variation with frequency SM = 1; at f = 300 Hz and 3400 Hz with respect to 1 kHz; note 9 − − +0.3/−0.7 dB gain variation with ambient SM = 1; at Tamb = −10 to +60 °C temperature with respect to 25 °C − ±0.2 − dB gain variation with line current SM = 1; at Iline = 100 mA with respect to 20 mA; note 9 − 0 ±0.5 dB Confidence tone GCTS gain from DTMF to QR+/QR−; RM = 1; SM = 1; notes 11 and 12 − −25 − dB GCTS(min) minimum selectable gain RM = 1; SM = 1; GRAx = 111001 − −40 − dB GCTS(max) maximum selectable gain RM = 1; SM = 1; GRAx = 100000 − −19 − dB GCTS(step) step resolution RM = 1; SM = 1 − 0.5 to 1 − dB 1997 Jun 20 21 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC SYMBOL PARAMETER PCA1070 CONDITIONS MIN. TYP. MAX. UNIT OMIC: MICROPHONE PREAMPLIFIER OUTPUT ZOMIC output impedance GOMIC gain from MIC+/MIC− to OMIC − 400 − Ω − 20 − dB Zline = ∞ Ω; f = 300 Hz 20 37 − dB Zline = ∞ Ω; f = 1 kHz 20 35 − dB Zline = ∞ Ω; f = 3.4 kHz 20 25 − dB − 200 − Ω dynamic limiter not active; note 13 LN: SENDING CHANNEL OUTPUT; notes 14 and 15 BRL balance return loss ZLN with Zref = 220 Ω + (820 Ω // 115 nF) Selectable values for Zset = Ra + (Rb // C) with C = 1/(2 π × Rb × fp); note 16 Ra non-shunted resistance of Zset Ra(min) minimum selectable value for Ra ZSAx = 001; note 17 − 0 − Ω Ra(max) maximum selectable value for Ra ZSAx = 11x − 600 − Ω Ra(step) step resolution for Ra − 100 − Ω Rb shunted resistance of Zset − 800 − Ω Rb(min) minimum selectable value for Rb ZSBx = 001; notes 17 and 18 − 600 − Ω Rb(max) maximum selectable value for Rb ZSBx = 1x1 − 1000 − Ω Rb(step) step resolution for Rb − 100 − Ω fp pole frequency determining shunt capacitance C − 1915 − Hz fp(min) minimum selectable fp ZSPx = 0000 − 828 − Hz fp(max) maximum selectable fp ZSPx = 0111; note 19 − 5859 − Hz n multiplication factor for fp fp(x + 1) = n × [fp(x)] − 1.322 − vLN(noise) noise output voltage psophometrically weighted (O41 curve) − −76 − dBmp 3.1 3.5 3.9 V Dynamic limiter VLN(p-p) THD threshold of dynamic limiter (peak-to-peak) total harmonic distortion DLT = 1 2.2 2.6 3.0 V low voltage condition; VSLPE = 3.1 V − 2.4 − V low current condition; Iline = 9 mA − 2.6 − V Vi = 12 mV (RMS) + 10 dB − 2.5 5.0 % Dynamic behaviour of limiter; note 20 tatt attack time Vi steps from 12 to 38 mV (RMS) − 1.5 − ms trel release time Vi steps from 38 to 12 mV (RMS) − 90 − ms 1997 Jun 20 22 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC SYMBOL PARAMETER PCA1070 CONDITIONS MIN. TYP. MAX. UNIT SCR: PIN FOR SENDING CURRENT RESISTOR VSCR − 0.28 − V reduced sending gain; GM = 30 dB; GMAx = 000100 − 0.26 − V Iline = 12 mA − 0.22 − V Iline = 7 mA − 0.13 − V voltage at pin SCR Receiving channel: LN, LSI, OREC, QR+ and QR− QR+, QR−: RECEIVING AMPLIFIER OUTPUTS ZQR+, ZQR- output impedance single-ended − 4 − Ω GRS gain from LN to QR+/QR- note 21 −7.5 -6 −4.5 dB GRS(min) minimum selectable gain GRAx = 110011 −20.5 −19 −17.5 dB GRAx = 001011 GRS(max) maximum selectable gain GRS(step) gain step resolution ∆GRS gain variation with frequency ∆GRS 9.5 11.0 12.5 dB − 1 − dB at f = 300 Hz and 3400 Hz with respect to 1 kHz; note 9 − − ±0.5 dB gain variation with temperature at Tamb = −10 to +60 °C with respect to 25 °C − ±0.2 − dB ∆GRS gain variation with line current at Iline = 100 mA with respect to 20 mA; note 9 − 0 ±0.5 dB tACR AC start-up time CVDD = 470 µF; note 10 − 140 − ms vQR(p-p) maximum output voltage swing (peak-to-peak) VDD = 5 V; GRAx = 001011; Rt = ∞ Ω; RFC = 1; VLN = 2 V (RMS) − 2.3 − V HPL = 1; VDD = 5 V; GRAx = 001011; Rt = ∞ Ω; RFC = 1; VLN = 2 V (RMS) − 5.9 − V vQR(rms) output voltage (RMS value); THD = 2% vQR(noise) noise output voltage VQR(offset) DC offset voltage between QR+/QR− HPL = 1; GRAx = 000011; note 22 0.45 − − V HPL = 1; Rt = 450 Ω; GRAx = 000011; note 22 0.84 − − V RFC = 1; Ct = 80 nF; f = 3.4 kHz; GRAx = 000011; note 22 0.9 − − V single-ended; HPL = 1; Zt = 150 Ω + 100 µF at QR−; GRAx = 001001; note 22 0.45 − − V psophometrically weighted (O41 curve) − −82 − dBmp − − ±100 mV − 1000 − Ω − −6 − dB OREC: OUTPUT RECEIVE PREAMPLIFIER ZOREC output impedance GOREC gain from LN to OREC 1997 Jun 20 note 13 23 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC SYMBOL PARAMETER PCA1070 CONDITIONS MIN. TYP. MAX. UNIT Selectable values for Zoss = Rsa (Rsb // Cs); note 23 Rsa non-shunted resistance of Zoss Rsa(min) minimum selectable value Rsa Rsa(max) maximum selectable value for Rsa Rsb shunted resistance of Zoss Rsb(min) minimum selectable value for Rsb Rsb(max) maximum selectable value for Rsb Cs shunt capacitance of Zoss Cs(min) minimum selectable value for Cs Cs(max) maximum selectable value for Cs − 492 − Ω ZOSAx = 0000 − 134 − Ω ZOSAx = 1010; note 24 − 492 − Ω − 1259 − Ω ZOSBx = 0000 − 465 − Ω ZOSBx = 1011; note 24 − 2216 − Ω − 134 − nF ZOSPx = 0001; note 25 − 55 − nF ZOSPx = 1111; note 24 − 259 − nF Zline = 492 Ω + (1259 Ω // 134 nF); f = 300 Hz − 11 15 dB Zline = 492 Ω + (1259 Ω // 134 nF); f = 1 kHz − 5 10 dB Zline = 492 Ω + (1259 Ω // 134 nF); f = 3.4 kHz − 9 15 dB − 0 100 nA 400 − µA Sidetone suppression; note 26 GSTS gain from MIC+/MIC− to QR+/QR− Dial output connection: DOC (open-drain output) IDOC output sink current VDOC = 12 V DPI = 1; VDOC = 0.4 V; VDD = 2.5 V 200 Line current control: LN and SLPE Iline(min) minimum value of DC line LCx = 00001 current that can be read as a bit code via the I2C-bus − 15 − mA Iline(max) maximum value of DC line LCx = 11110 current that can be read as a bit code via the I2C-bus − 91 − mA Iline(step) DC line current step resolution note 27 − ≈2.5 − mA note 28 − − − I2C-bus inputs/outputs: SDA and SCL in accordance with standard 1997 Jun 20 24 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC SYMBOL PARAMETER PCA1070 CONDITIONS MIN. TYP. MAX. UNIT Clock input: CLK 200 − VVMC − VSS mV − − ±0.5 % input series resistance − 800 − kΩ input series capacitance − 4 − pF vCLK(p-p) input signal voltage level (peak-to-peak value) ∆fCLK/fCLK frequency tolerance RCLK CCLK note 29 Notes 1. Time needed to reach at start-up the default DC voltage VSLPE (±10% from its final value): a) Time depends strongly on the value of the capacitor(s) at VDD and VMC; with a lower value of CVDD the DC start-up time decreases. b) The start-up time can be reduced considerably by programming the bit code DST = 1 during the start-up procedure. In practice this is possible as soon as the microcontroller has become operational. 2. Time needed to reach the DC voltage VSLPE within ±10% from its final value) after reprogramming VDCx. 3. The supply voltage VDD is determined by the regulated DC voltage at pin SLPE and by the voltage drop between pin SLPE and VDD; see Chapter “Functional description”. 4. Relaxed performance means: parameters can deviate from their specified values. 5. Rejection between supply pin VDD and VP. Rejection between pin LN and VP can be calculated by adding the attenuation of the first-order low-pass filter (R = 250 Ω, C = 150 µF) between SLPE and VDD. 6. If VDD is above this level, the default values have been loaded into the internal registers. 7. RMC changes from logic 1 to logic 0 when voltage on pin VMC is increasing; RMC changes from logic 0 to logic 1 when voltage on pin VMC is decreasing; see Fig.4. 8. Common mode signal is applied via 2 × 470 Ω external resistors connected to pins MIC+ and MIC−. 9. Not tested, guaranteed by design. 10. Time needed to reach default settings (±3 dB). 11. At low gain settings the confidence tone gain will be slightly higher than the specified value due to a residual signal. 12. GCTA, the confidence tone gain for asymmetrical drive, equals GCTS −6 (in dB). 13. To be left open-circuit in application. 14. The AC set impedance between pin LN and VSS consists of Ra + (Rb // C) in parallel with an artificial inductor Leq and internal resistors Rp and RLSI and internal capacitor Cp. See Chapter “Functional description”. 15. Balance Return Loss indicates the deviation of an impedance with respect to a reference impedance. BRL = 20 log (ZLN + Zref)/(ZLN − Zref) where ZLN ≈ Ra + (Rb // C) is the impedance seen into pin LN Zref = Ra(ref) + (Rb(ref) // Cref) is the reference impedance. 16. Without clock the set impedance is automatically set to Zset = 600 Ω (typical). 17. The combination Ra = 0 and Rb = 0 is not allowed (see Tables 9 and 10, note 1). 18. Value logic 0 can also be programmed. 19. Value fp = 12 kHz can also be programmed. 20. Attack and release times are also valid under low current and voltage conditions. 21. GRA, the receiving channel gain for asymmetrical drive equals GRS −6 (in dB). 22. The maximum possible output swing depends on the DC conditions (the programmed voltage VSLPE and the load on the supply pin VDD) and on the gain setting of the receiving channel. 1997 Jun 20 25 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 23. The internal balance impedance Zoss to match the external load impedance at pin LN (Zline = Zoss) for optimum sidetone suppression; Zoss = Rsa + (Rsb // Cs); without clock the sidetone balance impedance is automatically set to Zoss = 600 Ω (typical). 24. Other values can be found in Tables 14, 15 and 16. 25. Value Cs = 5 nF can also be programmed. 26. Gain sending channel GM = default (typical 41 dB); gain receiving channel Grec = default (typical −6 dB); sidetone gain GSTS minimum sidetone suppression at f = 300 Hz and 3400 Hz is: GM + GR − Gst(max) = 41 − 6 − 15 = 20 dB. GSTA, the sidetone gain for asymmetrical drive equals GSTS −6 (in dB). 27. Indication only; exact values can be found in Table 16. 28. Standard I2C-bus specifications are valid for VDD ≥ 2.5 V. Relaxed specifications for VDD = 1.8 to 2.5 V. 29. Recommended accuracy of input frequency; a higher tolerance will cause parameters to deviate from their specified values; note that all parameters are specified with the reference input clock frequency fclk = 3.579545 MHz. 1997 Jun 20 26 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 TEST AND APPLICATION INFORMATION The test circuit is illustrated in Fig.7. The basic application circuit is illustrated in Fig.8. An interrupter with an N-channel depletion MOS transistor (e.g. BSD254A or BSP124) is shown. It is intended for applications where a low DC line voltage is required. An interrupter with an N-channel enhancement MOS transistor (e.g. BSN304A or BSP130) can be used for applications where a relatively high DC line voltage is allowed. An application circuit for applications where a low DC line voltage and long line interrupts are required, is illustrated in Fig.9 (interrupter with an N-channel depletion MOS transistor). handbook, full pagewidth VDOC + VLN − 100 µF 3.3 nF 20 Ω 100 nF Zline 470 nF 5V 250 Ω S1 Iline 12 to 140 mA 1 150 µF IDOC 2 DOC Vrec LSI LN SLPE REG VDD Ip I2C-BUS MASTER TRANSCEIVER VMC SDA ITX TX SCL CLK PCA1070 DTMF SCR 100 Ω Vref OMIC OREQ VP MIC+ MIC− QR+ 100 nF + TST VDTMF QR− VSS − + Vclk − VMIC IVP + MGE345 − Rt Rm Vm + Vt − Definitions: Gain sending channel GM = 20 log (VLN/VMIC) with S1 in position 1; VDTMF = 0. Gain DTMF amplifier GDTMF = 20 log (VLN/VDTMF) with S1 in position 1; Vm = 0. Gain receiving channel Grec = 20 log (VT/VLN) with S1 in position 2; Vm = 0. Sidetone gain Gst = 20 log (VT/VMIC) with S1 in position 1; VDTMF = 0. Fig.7 Test circuit of the PCA1070. 1997 Jun 20 RMC 27 1997 Jun 20 b/a a/b HS1 28 100 Ω QR− VSS TST RMC DTMF ELECTRET T1 KEYBOARD VSS XTAL1 XTAL2 ROM COL TONE MICROCONTROLLER DTMF CE/T0 EEPROM RESET VDD CLK PXE SCL SDA 150 µF SCL VMC SDA I2C-bus MGE344 Multistandard programmable analog CMOS transmission IC Fig.8 Basic application diagram. 100 nF Vref OMIC OREQ VP MIC+ MIC− QR+ PCA1070 VDD 250 Ω DOC LSI LN SLPE REG 20 Ω dbook, full pagewidth SCR TX 1 MΩ HS2 RINGER OUTPUT STAGE Philips Semiconductors Product specification PCA1070 1997 Jun 20 b/a a/b HS1 29 100 Ω 100 nF T1 QR− VSS TST RMC DTMF KEYBOARD VSS XTAL1 XTAL2 ROM COL TONE MGE343 Multistandard programmable analog CMOS transmission IC Fig.9 Application diagram. VDD MICROCONTROLLER DTMF CE/T0 EEPROM RESET PXE CLK SDA 47 µF SCL I2C-bus SCL VMC SDA 470 µF ELECTRET Vref OMIC OREQ VP MIC+ MIC− QR+ PCA1070 VDD 250 Ω DOC LSI LN SLPE REG 20 Ω dbook, full pagewidth SCR TX 1 MΩ HS2 RINGER OUTPUT STAGE Philips Semiconductors Product specification PCA1070 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 PACKAGE OUTLINES seating plane DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1 ME D A2 L A A1 c e Z b1 w M (e 1) b MH 13 24 pin 1 index E 1 12 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.1 0.51 4.0 1.7 1.3 0.53 0.38 0.32 0.23 32.0 31.4 14.1 13.7 2.54 15.24 3.9 3.4 15.80 15.24 17.15 15.90 0.25 2.2 inches 0.20 0.020 0.16 0.066 0.051 0.021 0.015 0.013 0.009 1.26 1.24 0.56 0.54 0.10 0.60 0.15 0.13 0.62 0.60 0.68 0.63 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT101-1 051G02 MO-015AD 1997 Jun 20 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-23 30 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 13 24 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013AD 1997 Jun 20 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 31 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1997 Jun 20 32 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Jun 20 33 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 NOTES 1997 Jun 20 34 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 NOTES 1997 Jun 20 35 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA54 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 417027/00/03/pp36 Date of release: 1997 Jun 20 Document order number: 9397 750 00949