PHILIPS TEA1062T

INTEGRATED CIRCUITS
DATA SHEET
TEA1062; TEA1062A
Low voltage transmission circuits
with dialler interface
Product specification
Supersedes data of 1996 Dec 04
File under Integrated Circuits, IC03
1997 Sep 03
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
FEATURES
GENERAL DESCRIPTION
• Low DC line voltage; operates down to 1.6 V (excluding
polarity guard)
• Symmetrical high-impedance inputs (64 kΩ) for
dynamic, magnetic or piezoelectric microphones
The TEA1062 and TEA1062A are integrated circuits that
perform all speech and line interface functions required in
fully electronic telephone sets. They perform electronic
switching between dialling and speech. The ICs operate at
line voltage down to 1.6 V DC (with reduced performance)
to facilitate the use of more telephone sets connected in
parallel.
• Asymmetrical high-impedance input (32 kΩ) for electret
microphones
All statements and values refer to all versions unless
otherwise specified.
• Voltage regulator with adjustable static resistance
• Provides a supply for external circuits
• DTMF signal input with confidence tone
• Mute input for pulse or DTMF dialling
– TEA1062: active HIGH (MUTE)
– TEA1062A: active LOW (MUTE)
• Receiving amplifier for dynamic, magnetic or
piezoelectric earpieces
• Large gain setting ranges on microphone and earpiece
amplifiers
• Line loss compensation (line current dependent) for
microphone and earpiece amplifiers
• Gain control curve adaptable to exchange supply
• DC line voltage adjustment facility.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VLN
line voltage
Iline
operating line current
CONDITIONS
Iline = 15 mA
MAX.
UNIT
V
4.0
4.25
normal operation
11
−
140
mA
with reduced performance
1
−
11
mA
−
0.9
1.35
mA
internal supply current
VCC = 2.8 V
VCC
supply voltage for peripherals
Iline = 15 mA
2.7
−
V
3.4
−
V
2.7
−
V
−
3.4
−
V
microphone amplifier
44
−
52
dB
receiving amplifier
20
−
31
dB
−25
−
+75
°C
TEA1062
Ip = 1.2 mA; MUTE = HIGH 2.2
Ip = 0 mA; MUTE = HIGH
TEA1062A
−
Ip = 1.2 mA; MUTE = LOW 2.2
Ip = 0 mA; MUTE = LOW
Tamb
TYP.
3.55
ICC
Gv
MIN.
voltage gain
operating ambient temperature
Line loss compensation
∆Gv
gain control
−
5.8
−
dB
Vexch
exchange supply voltage
36
−
60
V
Rexch
exchange feeding bridge resistance
0.4
−
1
kΩ
1997 Sep 03
2
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
TEA1062
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-1
TEA1062M1
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4 or
SOT38-9
TEA1062A
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-1
TEA1062AM1
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4 or
SOT38-9
TEA1062T
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
TEA1062AT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
BLOCK DIAGRAM
VCC
handbook, full pagewidth
LN
1
13
IR
10
5
4
TEA1062A
MIC
MIC
DTMF
(1)
MUTE
GAR
QR
7
2
6
11
3
dB
GAS1
GAS2
12
SUPPLY AND
REFERENCE
CONTROL
CURRENT
LOW VOLTAGE
CIRCUIT
CURRENT
REFERENCE
9
VEE
14
15
REG AGC
8
STAB
(1) Pin 12 is active HIGH (MUTE) for TEA1062.
Fig.1 Block diagram for TEA1062A.
1997 Sep 03
3
16
SLPE
MBA359 - 1
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
PINNING
SYMBOL
PIN
DESCRIPTION
LN
1
positive line terminal
GAS1
2
gain adjustment; transmitting
amplifier
GAS2
3
gain adjustment; transmitting
amplifier
QR
4
non-inverting output; receiving
amplifier
GAR
5
gain adjustment; receiving
amplifier
handbook, halfpage
LN
1
16 SLPE
GAS1
2
15 AGC
GAS2
3
14 REG
QR
4
13 VCC
TEA1062A
GAR
5
12 MUTE
MIC
6
11 DTMF
current stabilizer
MIC
7
10 IR
9
negative line terminal
STAB
8
IR
10
receiving amplifier input
DTMF
11
dual-tone multi-frequency input
MUTE
12
mute input (see note 1)
MIC−
6
inverting microphone input
MIC+
7
non-inverting microphone input
STAB
8
VEE
VCC
13
positive supply decoupling
REG
14
voltage regulator decoupling
AGC
15
automatic gain control input
SLPE
16
slope (DC resistance) adjustment
VEE
MBA354 - 1
Fig.2 Pin configuration for TEA1062A.
Note
1. Pin 12 is active HIGH (MUTE) for TEA1062.
1997 Sep 03
9
4
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
FUNCTIONAL DESCRIPTION
Supplies VCC, LN, SLPE, REG and STAB
LN
Power for the IC and its peripheral circuits is usually
obtained from the telephone line. The supply voltage is
derived from the line via a dropping resistor and regulated
by the IC. The supply voltage VCC may also be used to
supply external circuits e.g. dialling and control circuits.
handbook, halfpage
L eq
V ref
Decoupling of the supply voltage is performed by a
capacitor between VCC and VEE. The internal voltage
regulator is decoupled by a capacitor between REG and
VEE.
R9
20 Ω
V
The DC current flowing into the set is determined by the
exchange supply voltage Vexch, the feeding bridge
resistance Rexch and the DC resistance of the telephone
line Rline.
R1
REG
VCC
C3
4.7 µF
C1
100 µF
MBA454
Leq = C3 × R9 × Rp.
Rp = 16.2 kΩ.
The circuit has an internal current stabilizer operating at a
level determined by a 3.6 kΩ resistor connected between
STAB and VEE (see Fig.9). When the line current (Iline) is
more than 0.5 mA greater than the sum of the IC supply
current (ICC) and the current drawn by the peripheral
circuitry connected to VCC (Ip) the excess current is
shunted to VEE via LN.
Fig.3 Equivalent impedance circuit.
At line currents below 9 mA the internal reference voltage
is automatically adjusted to a lower value (typically 1.6 V
at 1 mA). This means that more sets can be operated in
parallel with DC line voltages (excluding the polarity guard)
down to an absolute minimum voltage of 1.6 V. At line
currents below 9 mA the circuit has limited sending and
receiving levels. The internal reference voltage can be
adjusted by means of an external resistor (RVA).
This resistor when connected between LN and REG will
decrease the internal reference voltage and when
connected between REG and SLPE will increase the
internal reference voltage.
The regulated voltage on the line terminal (VLN) can be
calculated as:
VLN = Vref + ISLPE × R9
VLN = Vref + {(Iline − ICC − 0.5 × 10−3 A) − Ip} × R9
Vref is an internally generated temperature compensated
reference voltage of 3.7 V and R9 is an external resistor
connected between SLPE and VEE.
In normal use the value of R9 would be 20 Ω.
Current (Ip) available from VCC for peripheral circuits
depends on the external components used. Fig.10 shows
this current for VCC > 2.2 V. If MUTE is LOW (TEA1062) or
MUTE is HIGH (TEA1062A) when the receiving amplifier
is driven, the available current is further reduced. Current
availability can be increased by connecting the supply IC
(TEA1081) in parallel with R1 as shown in Fig.19 and
Fig.20, or by increasing the DC line voltage by means of
an external resistor (RVA) connected between REG and
SLPE (Fig.18).
Changing the value of R9 will also affect microphone gain,
DTMF gain, gain control characteristics, sidetone level,
maximum output swing on LN and the DC characteristics
(especially at the lower voltages).
Under normal conditions, when ISLPE >> ICC + 0.5 mA + Ip,
the static behaviour of the circuit is that of a 3.7 V regulator
diode with an internal resistance equal to that of R9. In the
audio frequency range the dynamic impedance is largely
determined by R1. Fig.3 shows the equivalent impedance
of the circuit.
1997 Sep 03
EE
Rp
5
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
Receiving amplifier IR, QR and GAR
Microphone inputs MIC+ and MIC− and gain pins
GAS1 and GAS2
The receiving amplifier has one input (IR) and a
non-inverting output (QR). Earpiece arrangements are
illustrated in Fig.12. The IR to QR gain is typically 31 dB
(when R4 = 100 kΩ). It can be adjusted between
20 and 31 dB to match the sensitivity of the transducer in
use. The gain is set with the value of R4 which is
connected between GAR and QR. The overall receive
gain, between LN and QR, is calculated by subtracting the
anti-sidetone network attenuation (32 dB) from the
amplifier gain. Two external capacitors, C4 and C7, ensure
stability. C4 is normally 100 pF and C7 is 10 times the
value of C4. The value of C4 may be increased to obtain a
first-order low-pass filter. The cut-off frequency will depend
on the time constant R4 × C4.
The circuit has symmetrical microphone inputs. Its input
impedance is 64 kΩ (2 × 32 kΩ) and its voltage gain is
typically 52 dB (when R7 = 68 kΩ, see Figures 14
and 15). Dynamic, magnetic, piezoelectric or electret (with
built-in FET source followers) can be used. Microphone
arrangements are illustrated in Fig.11.
The gain of the microphone amplifier can be adjusted
between 44 dB and 52 dB to suit the sensitivity of the
transducer in use. The gain is proportional to the value of
R7 which is connected between GAS1 and GAS2.
Stability is ensured by two external capacitors, C6
connected between GAS1 and SLPE and C8 connected
between GAS1 and VEE. The value of C6 is 100 pF but this
may be increased to obtain a first-order low-pass filter.
The value of C8 is 10 times the value of C6. The cut-off
frequency corresponds to the time constant R7 × C6.
The output voltage of the receiving amplifier is specified for
continuous-wave drive. The maximum output voltage will
be higher under speech conditions where the peak to RMS
ratio is higher.
Input MUTE (TEA1062)
Automatic Gain Control input AGC
When MUTE is HIGH the DTMF input is enabled and the
microphone and receiving amplifier inputs are inhibited.
The reverse is true when MUTE is LOW or open-circuit.
MUTE switching causes only negligible clicking on the line
and earpiece output. If the number of parallel sets in use
causes a drop in line current to below 6 mA the speech
amplifiers remain active independent to the DC level
applied to the MUTE input.
Automatic line loss compensation is achieved by
connecting a resistor (R6) between AGC and VEE.
The automatic gain control varies the gain of the
microphone amplifier and the receiving amplifier in
accordance with the DC line current. The control range is
5.8 dB which corresponds to a line length of 5 km for a
0.5 mm diameter twisted-pair copper cable with a DC
resistance of 176 Ω/km and average attenuation of
1.2 dB/km). Resistor R6 should be chosen in accordance
with the exchange supply voltage and its feeding bridge
resistance (see Fig.13 and Table 1). The ratio of start and
stop currents of the AGC curve is independent of the value
of R6. If no automatic line-loss compensation is required
the AGC pin may be left open-circuit. The amplifiers, in this
condition, will give their maximum specified gain.
Input MUTE (TEA1062A)
When MUTE is LOW or open-circuit, the DTMF input is
enabled and the microphone and receiving amplifier inputs
are inhibited. The reverse is true when MUTE is HIGH.
MUTE switching causes only negligible clicking on the line
and earpiece output. If the number of parallel sets in use
causes a drop in line current to below 6 mA the DTMF
amplifier becomes active independent to the DC level
applied to the MUTE input.
Dual-tone multi-frequency input DTMF
When the DTMF input is enabled dialling tones may be
sent on to the line. The voltage gain from DTMF to LN is
typically 25.5 dB (when R7 = 68 kΩ) and varies with R7 in
the same way as the microphone gain. The signalling
tones can be heard in the earpiece at a low level
(confidence tone).
1997 Sep 03
TEA1062; TEA1062A
6
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
Sidetone suppression
EXAMPLE
The anti-sidetone network, R1//Zline, R2, R3, R8, R9 and
Zbal, (see Fig.4) suppresses the transmitted signal in the
earpiece. Maximum compensation is obtained when the
following conditions are fulfilled:

R8 × Z bal 
(1)
R9 × R2 = R1 ×  R3 + ------------------------
R8 + Z bal 

The balance impedance Zbal at which the optimum
suppression is present can be calculated by:
Z line
Z bal
------------------------- = -------------------------Z bal + R8
Z line + R1
Suppose Zline = 210 Ω + (1265 Ω//140 nF) representing a
5 km line of 0.5 mm diameter, copper, twisted-pair cable
matched to 600 Ω (176 Ω/km; 38 nF/km).
When k = 0.64 then R8 = 390 Ω;
Zbal = 130 Ω + (820 Ω//220 nF).
(2)
The anti-sidetone network for the TEA1060 family shown
in Fig.4 attenuates the signal received from the line by
32 dB before it enters the receiving amplifier.
The attenuation is almost constant over the whole
audio-frequency range.
If fixed values are chosen for R1, R2, R3 and R9, then
condition (1) will always be fulfilled when |R8//Zbal| << R3.
To obtain optimum sidetone suppression, condition (2) has
to be fulfilled which results in:
Figure 5 shows a conventional Wheatstone bridge
anti-sidetone circuit that can be used as an alternative.
Both bridge types can be used with either resistive or
complex set impedances. (More information on the
balancing of anti-sidetone bridges can be obtained in our
publication “Applications Handbook for Wired telecom
systems, IC03b”, order number 9397 750 00811.)
R8
Z bal = -------- × Z line = k × Z line
R1
R8
Where k is a scale factor; k = -------R1
The scale factor k, dependent on the value of R8, is
chosen to meet the following criteria:
• compatibility with a standard capacitor from the E6 or
E12 range for Zbal
• Zbal//R8 << R3 fulfilling condition (a) and thus
ensuring correct anti-sidetone bridge operation
• Zbal + R8 >> R9 to avoid influencing the transmit gain.
In practise Zline varies considerably with the line type and
length. The value chosen for Zbal should therefore be for
an average line length thus giving optimum setting for
short or long lines.
1997 Sep 03
7
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
LN
handbook, full pagewidth
R1
Zline
R2
IR
im
VEE
Rt
R3
R9
R8
Zbal
SLPE
MSA500 - 1
Fig.4 Equivalent circuit of TEA1060 family anti-sidetone bridge.
LN
book, full pagewidth
Zbal
R1
Zline
IR
im
VEE
Rt
R9
R8
RA
SLPE
MSA501 - 1
Fig.5 Equivalent circuit of an anti-sidetone network in a Wheatstone bridge configuration.
1997 Sep 03
8
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VLN
positive continuous line voltage
−
12
V
VLN(R)
repetitive line voltage during switch-on
or line interruption
−
13.2
V
VLN(RM)
repetitive peak line voltage for a 1 ms
pulse per 5 s
R9 = 20 Ω; R10 = 13 Ω;
see Fig.18
−
28
V
Iline
line current
R9 = 20 Ω; note 1
−
140
mA
VI
input voltage on all other pins
positive input voltage
−
VCC + 0.7
V
negative input voltage
−
−0.7
V
TEA1062; TEA1062A
−
666
mW
TEA1062M1; TEA1062AM1
−
617
mW
TEA1062T; TEA1062AT
Ptot
R9 = 20 Ω; note 2
total power dissipation
−
454
mW
Tamb
operating ambient temperature
−25
+75
°C
Tstg
storage temperature
−40
+125
°C
Tj
junction temperature
−
125
°C
Notes
1. Mostly dependent on the maximum required Tamb and on the voltage between LN and SLPE (see Figs 6, 7 and 8).
2. Calculated for the maximum ambient temperature specified (Tamb = 75 °C) and a maximum junction temperature of
125 °C.
HANDLING
This device meets class 2 ESD test requirements [Human Body Model (HBM)], in accordance with
“MIL STD 883C - method 3015”.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
TEA1062; TEA1062A
75
K/W
TEA1062M1; TEA1062AM1
81
K/W
TEA1062T; TEA1062AT (note 1)
110
K/W
thermal resistance from junction to ambient in free air
Note
1. Mounted on glass epoxy board 28.5 × 19.1 × 1.5 mm.
1997 Sep 03
9
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
MLC201
MLC200
150
150
handbook, halfpage
handbook, halfpage
I LN
(mA)
I LN
(mA)
130
130
(1)
110
110
(1)
(2)
90
90
(2)
(3)
(3)
70
70
(4)
(4)
50
50
30
30
2
4
6
8
2
10
12
V LN V SLPE (V)
(1) Tamb = 45 °C; Ptot = 1068 mW.
(2) Tamb = 55 °C; Ptot = 934 mW.
(3) Tamb = 65 °C; Ptot = 800 mW.
(4) Tamb = 75 °C; Ptot = 666 mW.
(1)
(2)
(3)
(4)
Fig.6
Fig.7
TEA1062 and TEA1062A safe operating
area.
MLC202
150
handbook, halfpage
I LN
(mA)
130
110
(1)
90
(2)
(3)
70
(4)
50
30
2
(1)
(2)
(3)
(4)
4
6
8
10
12
V LN V SLPE (V)
Tamb = 45 °C; Ptot = 727 mW.
Tamb = 55 °C; Ptot = 636 mW.
Tamb = 65 °C; Ptot = 545 mW.
Tamb = 75 °C; Ptot = 454 mW.
Fig.8
TEA1062T and TEA1062AT safe operating
area.
1997 Sep 03
10
4
6
8
10
12
V LN V SLPE (V)
Tamb = 45 °C; Ptot = 988 mW.
Tamb = 55 °C; Ptot = 864 mW.
Tamb = 65 °C; Ptot = 741 mW.
Tamb = 75 °C; Ptot = 617 mW.
TEA1062M1 and TEA1062AM1 safe
operating area.
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
CHARACTERISTICS
Iline = 11 to 140 mA; VEE = 0 V; f = 800 Hz; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies LN and VCC (pins 1 and 13)
VLN
voltage drop over circuit between LN
and VEE
MIC inputs open-circuit
Iline = 1 mA
−
1.6
−
V
Iline = 4 mA
−
1.9
−
V
Iline = 15 mA
3.55
4.0
4.25
V
Iline = 100 mA
4.9
5.7
6.5
V
Iline = 140 mA
−
−
7.5
V
−
−0.3
−
mV/K
−
3.5
−
V
RVA (REG to SLPE) = 39 kΩ −
4.5
−
V
−
0.9
1.35
mA
Ip = 1.2 mA
2.2
2.7
−
V
Ip = 0 mA
−
3.4
−
V
Ip = 1.2 mA
2.2
2.7
−
V
Ip = 0 mA
−
3.4
−
V
∆VLN/∆T
variation with temperature
Iline = 15 mA
VLN
voltage drop over circuit between LN
and VEE with external resistor RVA
Iline = 15 mA
RVA (LN to REG) = 68 kΩ
ICC
supply current
VCC = 2.8 V
VCC
supply voltage available for peripheral
circuitry
Iline = 15 mA; MUTE = HIGH
TEA1062
VCC
supply voltage available for peripheral
circuitry
TEA1062A
Iline = 15 mA; MUTE = LOW
Microphone inputs MIC− and MIC+ (pins 6 and 7)
Zi
input impedance
differential
between MIC− and MIC+
−
64
−
kΩ
single-ended
MIC− or MIC+ to VEE
−
32
−
kΩ
−
82
−
dB
CMRR
common mode rejection ratio
Gv
voltage gain MIC+ or MIC− to LN
Iline = 15 mA; R7 = 68 kΩ
50.5
52.0
53.5
dB
∆Gvf
gain variation with frequency
referenced to 800 Hz
f = 300 and 3400 Hz
−
±0.2
−
dB
∆GvT
gain variation with temperature
referenced to 25 °C
without R6; Iline = 50 mA;
Tamb = −25 and +75 °C
−
±0.2
−
dB
−
20.7
−
kΩ
DTMF input (pin 11)
|Zi|
input impedance
Gv
voltage gain from DTMF to LN
Iline = 15 mA; R7 = 68 kΩ
24.0
25.5
27.0
dB
∆Gvf
gain variation with frequency
referenced to 800 Hz
f = 300 and 3400 Hz
−
±0.2
−
dB
∆GvT
gain variation with temperature
referenced to 25 °C
Iline = 50 mA;
Tamb = −25 and +75 °C
−
±0.2
−
dB
1997 Sep 03
11
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
SYMBOL
PARAMETER
TEA1062; TEA1062A
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Gain adjustment inputs GAS1 and GAS2 (pins 2 and 3)
∆Gv
−8
−
0
dB
Iline = 4 mA
−
0.8
−
V
Iline = 15 mA
1.7
2.3
−
V
−
−69
−
dBmp
−
21
−
kΩ
−
4
−
Ω
transmitting amplifier gain variation by
adjustment of R7 between
GAS1 and GAS2
Sending amplifier output LN (pin 1)
VLN(rms)
Vno(rms)
output voltage (RMS value)
noise output voltage (RMS value)
THD = 10%
Iline = 15 mA; R7 = 68 kΩ;
200 Ω between MIC− and
MIC+; psophometrically
weighted (P53 curve)
Receiving amplifier input IR (pin 10)
Zi
input impedance
Receiving amplifier output QR (pin 4)
Zo
output impedance
Gv
voltage gain from IR to QR
Iline = 15 mA; RL = 300 Ω
(from pin 9 to pin 4)
29.5
31
32.5
dB
∆Gvf
gain variation with frequency
referenced to 800 Hz
f = 300 and 3400 Hz
−
±0.2
−
dB
∆GvT
gain variation with temperature
referenced to 25 °C
without R6; Iline = 50 mA;
Tamb = −25 and +75 °C
−
±0.2
−
dB
Vo(rms)
output voltage (RMS value)
THD = 2%; sine wave drive;
R4 = 100 kΩ; Iline = 15 mA;
Ip = 0 mA
RL = 150 Ω
0.22
0.33
−
V
RL = 450 Ω
0.3
0.48
−
V
Vo(rms)
output voltage (RMS value)
THD = 10%; R4 = 100 kΩ;
RL = 150 Ω; Iline = 4 mA
−
15
−
mV
Vno(rms)
noise output voltage (RMS value)
Iline = 15 mA; R4 = 100 kΩ;
IR open-circuit
psophometrically weighted
(P53 curve); RL = 300 Ω
−
50
−
µV
−11
−
0
dB
−
VCC
V
Gain adjustment input GAR (pin 5)
∆Gv
receiving amplifier gain variation by
adjustment of R4 between GAR and QR
Mute input (pin 12)
VIH
HIGH level input voltage
1.5
VIL
LOW level input voltage
−
−
0.3
V
IMUTE
input current
−
8
15
µA
1997 Sep 03
12
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
SYMBOL
PARAMETER
TEA1062; TEA1062A
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reduction of gain
∆Gv
Gv
MIC+ or MIC− to LN
TEA1062
MUTE = HIGH
−
70
−
dB
TEA1062A
MUTE = LOW
−
70
−
dB
R4 = 100 kΩ; RL = 300 Ω
voltage gain from DTMF to QR
TEA1062
MUTE = HIGH
−
−17
−
dB
TEA1062A
MUTE = LOW
−
−17
−
dB
−
−5.8
−
dB
Automatic gain control input AGC (pin 15)
∆Gv
controlling the gain from IR to QR
and the gain from MIC+, MIC− to LN
R6 = 110 kΩ
(between AGC and VEE)
Iline = 70 mA
gain control range
IlineH
highest line current for maximum gain
−
23
−
mA
IlineL
lowest line current for minimum gain
−
61
−
mA
R line
I line
R1
handbook, full pagewidth
I SLPE
R exch
I CC
0.5 mA
LN
TEA1062
TEA1062A
VCC
Ip
DC
0.5 mA
AC
C1
Vexch
REG
STAB
SLPE
V
peripheral
circuits
EE
I SLPE
C3
R5
R9
MBA357 - 1
Fig.9 Supply arrangement.
1997 Sep 03
13
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
MSA504
2.4
handbook, halfpage
(1)
Ip
(mA)
(2)
1.6
0.8
0
0
1
2
3
V CC (V)
4
The supply possibilities can be increased by setting the voltage drop over the circuit VLN to a higher value by resistor RVA connected between REG and
SLPE.
VCC > 2.2 V; Iline = 15 mA at VLN = 4 V; R1 = 620 Ω; R9 = 20 Ω.
(1) Ip = 2.1 mA. Is valid when the receiving amplifier is not driven or when MUTE = HIGH (TEA1062), MUTE = LOW (TEA1062A).
(2) Ip = 1.7 mA. Is valid when MUTE = LOW (TEA1062), MUTE = HIGH (TEA1062A) and the receiving amplifier is driven; Vo(rms) = 150 mV,
RL = 150 Ω.
Fig.10 Typical current Ip available from VCC for peripheral circuitry.
1997 Sep 03
14
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
andbook, full pagewidth
13
7
6
MIC
V CC
7
(1)
6
7
MIC
6
MSA505
9
(a)
(b)
(c)
(a) Magnetic or dynamic microphone.
(b) Electret microphone.
(c) Piezoelectric microphone.
(1) Resistor may be connected to reduce the terminating impedance.
Fig.11 Alternative microphone arrangements.
handbook, full pagewidth
V EE
4
9
QR
(1)
4
QR
V EE 9
VEE
4
(2)
9
MSA506
(a)
(b)
(a) Dynamic earpiece.
(b) Magnetic earpiece.
(c) Piezoelectric earpiece.
(1) Resistor may be connected to prevent distortion (inductive load).
(2) Resistor is required to increase the phase margin (capacitive load).
Fig.12 Alternative receiver arrangements.
1997 Sep 03
15
MIC
MIC
V EE
QR
MIC
MIC
(c)
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
handbook, full pagewidth
MSA507 - 1
R6 = ∞
0
∆G v
(dB)
2
4
78.7 kΩ
110 kΩ
140 kΩ
6
0
20
40
60
80
100
120
140
I line (mA)
R9 = 20 Ω.
Fig.13 Variation of gain as a function of line current with R6 as a parameter.
Table 1
Values of resistor R6 for optimum line-loss compensation at various values of exchange supply voltage
(Vexch) and exchange feeding bridge resistance (Rexch); R9 = 20 Ω.
R6 (kΩ)
Vexch (V)
Rexch = 400 Ω
Rexch = 600 Ω
36
100
78.7
−
−
48
140
110
93.1
82
60
−
−
120
102
1997 Sep 03
16
Rexch = 800 Ω
Rexch = 1000 Ω
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
I line
R1
handbook, full pagewidth
13
10
7
Vi
100 µF
6
11
620 Ω
1
IR
100 µF
LN
VCC
MIC
QR
MIC
GAR
TEA1062
DTMF
5
C4
100 pF
GAS1
MUTE
2
10 µF
Vi
R4
100 kΩ
Vo
C7 1 nF
C1
12
RL
600 Ω
4
GAS2
V EE
9
C3
4.7
µF
REG AGC STAB SLPE
14
15
8
16
R6
R5
3.6
kΩ
3
R7
68 kΩ
10 to 140 mA
C8
1 nF
C6
100 pF
R9
20 Ω
MSA508
Voltage gain is defined as Gv = 20 log Vo/Vi.
For measuring gain from MIC+ and MIC− the MUTE input should be LOW or open-circuit.
For measuring the DTMF input, the MUTE input should be HIGH.
Inputs not being tested should be open-circuit.
Fig.14 Test circuit for defining TEA1062 voltage gain of MIC+, MIC− and DTMF inputs.
1997 Sep 03
17
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
I line
R1
handbook, full pagewidth
620 Ω
13
10
7
Vi
100 µF
1
IR
100 µF
LN
VCC
MIC
QR
6
11
MIC
GAR
TEA1062A
DTMF
5
C4
100 pF
GAS1
MUTE
2
10 µF
Vi
R4
100 kΩ
Vo
C7 1 nF
C1
12
RL
600 Ω
4
GAS2
V EE
9
C3
4.7
µF
REG
14
AGC
15
R6
STAB SLPE
16
8
R5
3.6
kΩ
3
R7
68 kΩ
10 to 140 mA
C8
1 nF
C6
100 pF
R9
20 Ω
MBA355
Voltage gain is defined as Gv = 20 log Vo/Vi.
For measuring gain from MIC+ and MIC− the MUTE input should be HIGH.
For measuring the DTMF input, the MUTE input should be LOW or open-circuit.
Inputs not being tested should be open-circuit.
Fig.15 Test circuit for defining TEA1062A voltage gain of MIC+, MIC− and DTMF inputs.
1997 Sep 03
18
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
I line
R1
handbook, full pagewidth
620 Ω
13
10
7
Vi
10 µF
6
11
IR
100 µF
1
LN
VCC
QR
MIC
MIC
TEA1062
DTMF
GAR
C1
100 µF
12
4
GAS1
MUTE
5
C2
R4
100
kΩ
Vo
C4
100 pF
C7 1 nF
2
10 to 140 mA
C8
1 nF
R7
GAS2
V EE
REG
9
AGC
14
3
C6
100 pF
STAB SLPE
15
C3
4.7
µF
8
16
R5
3.6
kΩ
R6
600 Ω
ZL
R9
20 Ω
MSA509
Voltage gain is defined as Gv = 20 log Vo/Vi.
Fig.16 Test circuit for defining TEA1062 voltage gain of the receiving amplifier.
I line
R1
handbook, full pagewidth
13
10
7
Vi
10 µF
6
11
620 Ω
IR
100 µF
1
LN
VCC
QR
MIC
MIC
TEA1062A
DTMF
GAR
C1
100 µF
12
4
GAS1
MUTE
5
C2
R4
100
kΩ
V
EE
9
C3
4.7
µF
REG AGC STAB SLPE
14
15
8
16
R5
3.6
kΩ
R6
Vo
C4
100 pF
C7 1 nF
2
10 to 140 mA
R7
GAS2
600 Ω
ZL
3
C8
1 nF
C6
100 pF
R9
20 Ω
MBA356
Voltage gain is defined as Gv = 20 log Vo/Vi.
Fig.17 Test circuit for defining TEA1062A voltage gain of the receiving amplifier.
1997 Sep 03
19
20
BZW14
(2x)
BZX79 C12
Z bal
R4
R3
3.92
kΩ
C2
R8
C7
1 nF
C4
100
pF
100 nF
C5
390 Ω
R2
130 kΩ
IR
100 pF
C8
1 nF
R VA(R 16 - 14 )
C3
4.7
µF
14
REG
TEA1062A
SLPE
GAS1 GAS2
16
2
3
C6
R7
MIC
MIC
GAR
QR
R9
20 Ω
6
7
5
4
10
1
LN
R1
R6
AGC
15
R5
3.6
kΩ
STAB
8
(1)
9
VEE
MUTE
DTMF
13
VCC
Fig.18 Typical application of TEA1062A, with piezoelectric earpiece and DTMF dialling.
12
11
MBA358 - 1
from dial
and
control circuits
C1
100
µF
Low voltage transmission circuits with
dialler interface
The diode bridge, the Zener diode and R10 limit the current into, and the voltage across, the circuit during line transients.
A different protection arrangement is required for pulse dialling or register recall.
The DC line voltage can be set to a higher value by the resistor RVA (REG to SLPE).
Further application information can be found in our publication “Applications Handbook for Wired telecom systems, IC03b”, order number 9397 750 00811.
(1) Pin 12 is active HIGH (MUTE) for TEA1062.
telephone
line
R10
13 Ω
BAS11
(2x)
handbook, full pagewidth
1997 Sep 03
620 Ω
Philips Semiconductors
Product specification
TEA1062; TEA1062A
APPLICATION INFORMATION
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
R1
handbook, full pagewidth
620 Ω
LN
cradle
contact
TEA1062
VCC
DTMF
VDD
TONE
MUTE
M1
VEE
VSS
PCD3310
DP/FLO
telephone
line
BSN254A
MLC203
(a) DTMF pulse set with CMOS bilingual dialling circuit PCD3310. The dashed line shows an optional flash (register recall by timed loop break).
Fig.19 Typical simplified application of the TEA1062.
R1
handbook, full pagewidth
620 Ω
LN
cradle
contact
TEA1062A
VCC
DTMF
VDD
TONE
MUTE
M1
VEE
VSS
PCD3310T
DP/FLO
telephone
line
BSN254A
MLC204
(a) DTMF pulse set with CMOS bilingual dialling circuit PCD3310T. The dashed line shows an optional flash (register recall by timed loop break).
Fig.20 Typical simplified application of the TEA1062A.
1997 Sep 03
21
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
w M
(e 1)
b
MH
9
16
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.7
0.51
3.7
1.40
1.14
0.53
0.38
0.32
0.23
21.8
21.4
6.48
6.20
2.54
7.62
3.9
3.4
8.25
7.80
9.5
8.3
0.254
2.2
inches
0.19
0.020
0.15
0.055
0.045
0.021
0.015
0.013
0.009
0.86
0.84
0.26
0.24
0.10
0.30
0.15
0.13
0.32
0.31
0.37
0.33
0.01
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT38-1
050G09
MO-001AE
1997 Sep 03
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-10-02
95-01-19
22
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
b2
MH
9
16
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
0.76
inches
0.17
0.020
0.13
0.068
0.051
0.021
0.015
0.049
0.033
0.014
0.009
0.77
0.73
0.26
0.24
0.10
0.30
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.030
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-01-14
SOT38-4
1997 Sep 03
EUROPEAN
PROJECTION
23
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-9
ME
seating plane
D
A2
A
A1
L
b1
e
Z
c
w M
(e1)
b
MH
b2
9
16
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.32
0.38
3.56
1.65
1.40
0.51
0.41
1.14
0.76
0.36
0.20
19.30
18.80
6.45
6.24
2.54
7.62
3.81
2.92
8.23
7.62
9.40
8.38
0.254
0.76
inches
0.17
0.015
0.14
0.065
0.055
0.020
0.016
0.045
0.030
0.014
0.008
0.76
0.74
0.254
0.246
0.10
0.30
0.150
0.115
0.324
0.300
0.37
0.33
0.01
0.030
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
97-07-24
SOT38-9
1997 Sep 03
EUROPEAN
PROJECTION
24
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.050
0.039
0.016
0.028
0.020
0.01
0.01
0.004
0.028
0.012
inches
0.244
0.041
0.228
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07S
MS-012AC
1997 Sep 03
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
25
o
8
0o
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
SOLDERING
BY SOLDER PASTE REFLOW
Plastic dual in-line packages
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
Apply the soldering iron below the seating plane (or not
more than 2 mm above it). If its temperature is below
300 °C, it must not be in contact for more than 10 s; if
between 300 and 400 °C, for not more than 5 s.
Plastic small-outline packages
BY WAVE
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
1997 Sep 03
26
Philips Semiconductors
Product specification
Low voltage transmission circuits with
dialler interface
TEA1062; TEA1062A
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Sep 03
27
Philips Semiconductors – a worldwide company
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Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 247 9145, Fax. +7 095 247 9144
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417027/1200/05/pp28
Date of release: 1997 Sep 03
Document order number:
9397 750 02819