P R O D U C T B R I E F Semiconductor Solutions for H i g h S p e e d Co m m u n i c a t i o n s and Fiber Optic Applications The Titan 19244 is a highly integrated single chip quadport STS-192 SONET/SDH TDM framer and pointer processor device. The Titan 19244 provides section, line, and path overhead processing for quad STS-192/STM-64. The framer itself takes four 10 Gbit/s (16-bit bus at 622 Mbit/s) channels on the line side interface, which is compliant with SFI-4 standard. The framer outputs four STS-192 SONET links on the system side. The system block diagram on the next page depicts a configuration for a quad OC-192 TDM framer and pointer processor application. The Titan 19244 is compliant with SONET/SDH standards ITU G.707, Bellcore GR-253, GR-1377, and ANSI T1.105. Applications ■ SONET/SDH Digital Cross-Connects ■ SONET/SDH Terminal Multiplexers ■ Long Haul and Metro Network ADM ■ Dense Wave Division Multiplexers ■ SONET/SDH Add/Drop Multiplexers ■ Multi-Service Provisioning Platforms Features ■ Quad-port STS-192/STM-64 SONET/SDH framer and pointer processor ■ Terminates and generates section and line overhead layer for STS-192/STM-64 ■ Supports pointer processing at STS-1 granularity for STS-192/STM-64 ■ Supports flexible concatenation of payloads STS-2c, STS-3c, STS-4c, STS-5c, … STS-12c, … STS-48c, … STS-192c ■ Performs frame synchronous scrambling and de-scrambling of STS-192 T i t a n ■ ■ ■ ■ ■ ■ ■ ■ Titan 19244 Drops/Inserts section and line overhead data bytes in the receive/transmit direction onto an external bus on both line side & system side Drops/Inserts Data Communications Channel (DCC) bytes D1-D3, D4-D12 on a serial link Provides hardware assistance for APS via K1 & K2 bytes. A separate APS interrupt port is provided per port for quad STS-192/STM-64 Supports external timing mode Detects Severely Errored Framing (SEF), Loss Of Signal (LOS), Loss Of Frame (LOF), Loss Of Pointer (LOP), and Loss Of Clock (LOC) Monitors Line Alarm Indication Signal (AIS-L), Line Remote Defect Indication (RDI-L), and Line Remote Error Indication (REI-L) Handles section trace identifier (J0) and path trace identifier (J1) processing Calculates, monitors, and counts the Section BIP-8 (B1), Line BIP-8N (B2), and Path BIP-8 (B3) errors ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Supports BER algorithm for Signal Fail (SF) and Signal Degrade (SD) Supports Terminal Loopback and Facility Loopback Supports Path REI error counting and Path RDI monitoring Supports detection of path unequipped and payload label mismatch (Signal Label Mismatch) Provides four 16-bit LVDS parallel buses operating at 622 Mbit/s on the line side for quad STS-192 Compliant with SFI-4 standard on the Line Side Interface Provides four 16-bit LVDS parallel buses at 622 MHz (STS-192 SONET links) on the system side Supports IEEE1149.1 JTAG testing Supports a 32-bit MPC860 Motorola microprocessor interface Meets ITU G.707, GR-253, GR-1377, and ANSI T1.105 1413-pin flip-chip BGA package 1 9 2 4 4 SONET/SDH Framer & Pointer Processor N e v e r s t o p t h i n k i n g . P B R O D U C T R I E F RX_EDCC_DATA RX_EDCC_DVALID RX_LDCC_DATA [3:0] RX_LDCC_DVALID [3:0] RX_SDCC_DVALID [3:0] RX_SDCC_DATA [3:0] LN_DRP_CLK [3:0] 77.76 MHz LN_DRP_FRM_STR [3:0] LN_DRP_DVALID [3:0] LN_DRP_DATA [3:0][7:0] Line Side Transport Overhead Drop Receive Line Side DCC System Side Transport Overhead Add Receive RX_LN_CLK [3:0] 622.08 MHz Receive Pointer Processor & Path Processor Receive Line Side Interface Block RX_LN_DATA [3:0][15:0] RX_LOF [3:0] RX_LIS [3:0] RX_LOC [3:0] Transmit Line Side Interface Block TX_LN_CLKOUT [3:0] 622.08 MHz TX_LN_DATA [3:0][15:0] TX_LN_CLKIN [3:0] 622.08 MHz Receive Pointer Aligner Receive System Side Interface Block Transmit Transmit Framer System Side & Interface Descrambler Block Transmit Framer Mux SYS_ADD_ROW_STR [3:0] SYS_ADD_FRM_STR [3:0] SYS_ADD_CLK [3:0] 77.76 MHz SYS_INSRT_EN [3:0] SYS_ADD_DATA [3:0][7:0] RX_TDM_SYSCLK [3:0] 622.08 MHz RX_TDMDATA[3:0][15:0] RX_SYS_CLKI [3:0] 622.08 MHz SYS_FP [3:0] TX_SYS_CLK [3:0] 622.08 MHz TX_TDMDATA[3:0][15:0] Transmit System Side Transport Overhead Drop SYS_DRP_CLK [3:0] 77.76 MHz SYS_DRP_FRM_STR [3:0] SYS_DRP_DVALID [3:0] SYS_DRP_DATA [3:0][7:0] TDI TDO TMS TRSTB MPR_DTACK_N MPR_R_WN MPR_IRQ_N DATA_MPR [31:0] TCK JTAG Interface 32-bit Microprocessor Interface CLK_PR TX_SDCC_DATA [3:0] TX_SDCC_DVALID [3:0] TX_LDCC_DATA [3:0] TX_LDCC_DVALID [3:0] TX_EDCC_DATA TX_EDCC_DVALID Control and Test Interfaces ADD_MPRIN[19:0] Transmit Line Side DCC OUT_EN LN_ADD_DATA [3:0][7:0] Line Side Transport Overhead Add CS_N LN_ADD_CLK [3:0] 77.76 MHz LN_ADD_FMR_STR [3:0] LN_ADD_ROW_STR [3:0] LN_ADD_EN [3:0] SYSTEM SIDE LINE SIDE Block Diagram Advantages ■ Low power ■ Small footprint ■ High integration ■ STS-768 support ■ SONET/SDH support Standards ■ GR-253 ■ GR-1377 ■ ITU G.707 ■ ANSI T1.105 Specifications ■ 622 MHz LVDS I/Os ■ 1413 ball FCBGA package ■ Full-scan; JTAG; MemBIST ■ 0 °C to 70 °C temperature range ■ <12 W power requirement (typ.) Note: Specifications subject to change without notice. Application Example How to reach us: http://www.infineon.com Infineon Technologies NA Corp. 1730 North First Street San Jose, CA 95112 USA Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München © Infineon Technologies AG 2002. All Rights Reserved. Published by Infineon Technologies AG Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. 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