DLP5500 www.ti.com DLPS013A – APRIL 2010 – REVISED JUNE 2010 ® DLP 0.55 XGA Series 450 DMD Check for Samples: DLP5500 FEATURES 1 • • • • • 0.55-Inch Micromirror Array Diagonal – 1024 × 768 Array of Aluminum, Micrometer-Sized Mirrors (XGA Resolution ) – 10.8-µm Micromirror Pitch – ±12° Micromirror Tilt Angle (Relative to Flat State) – Designed for Corner Illumination Designed for Use With Broadband Visible Light (420 nm–700 nm): – Window Transmission 97% (Single Pass, Through Two Window Surfaces) – Micromirror Reflectivity 88% – Array Diffraction Efficiency 86% – Array Fill Factor 92% 16-Bit, Low Voltage Differential Signaling (LVDS) Double Data Rate (DDR) input data bus 200 MHz Input Data Clock Rate Series 450 Package Characteristics: – Thermal Area 18.0 mm by 12.0 mm enabling high on screen lumens (>2000 lm) – 149 Micro Pin Grid Array Robust electrical connection APPLICATIONS • • • • • 3D Machine Vision 3D Optical Measurement Industrial and Medical Imaging Medical Instrumentation Digital Exposure systems DESCRIPTION The DLP5500 Digital Micromirror Device (DMD) is a digitally controlled MOEMS (micro-opto-electromechanical system) spatial light modulator (SLM). When coupled to an appropriate optical system, the DLP5500 can be used to modulate the amplitude, direction, and/or phase of incoming (illumination) light. Architecturally, the DLP5500 is a latchable, electrical-in/optical-out semiconductor device. This architecture makes the DLP5500 well suited for use in applications such as structured lighting, 3D optical metrology, Industrial & Medical imaging, microscopy, and spectroscopy. The compact physical size of the DLP5500 enables integration into portable equipment. The DLP5500 is one of three components in the DLP 0.55 XGA chip-set (see Figure 1). Proper function and operation of the DLP5500 requires that it be used in conjunction with the other components of the chip-set. The DLPC200 (TI literature number DLPS014) and DLPA200 (TI literature number DLPS015) control and coordinate the data loading and micromirror switching to guarantee reliable operation. Refer to DLP 0.55 XGA chip-set data sheet (TI literature number DLPZ004) for further details. DLPR200F is DLPC200 firmware code provided to enable Video and Structured Lighting Applicaions. To locate the latest version of the DLPR200F, go to www.ti.com and search keyword "DLPR200". Electrically, the DLP5500 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a square grid of 1024 memory cell columns by 768 memory cell rows. The CMOS memory array is written to on a column-by-column basis, over a 16-bit Low Voltage Differential Signaling (LVDS) double data rate (DDR) bus. Row addressing is handled via a serial control bus. The specific CMOS memory access protocol is handled by the DLPC200 Digital Controller. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated DLP5500 DLPS013A – APRIL 2010 – REVISED JUNE 2010 www.ti.com DLPC200 DMD_DAT_A( 1, 3, 5, 7, 9, 11, 13, 15 ) Port 1 Data Interface DLP5500 P/N SCTRL_A P/N Port 2 Data Interface DMD_CLK_A P/N DMD_DAT_B( 1, 3, 5, 7, 9, 11, 13, 15 ) P/N SCTRL_B P/N DMD Interface User Nonvolatile Memory Interface Data & Control Receiver USB Interface Serial Port Interface DMD_CLK_B P/N DMD_PWRDN SCP_DMD_EN User Static Memory Interface CMOS MEMORY ARRAY MICROMIRROR ARRAY SCP_DMD_RST_DI SCP_DMD_RST_DO SCP_DMD_RST_CLK Configuration Interface CFG_MSEL( 3:0 ) CFG_ASDI DLPR200F PROM CFG_ASDO V3P3V VSS DLPR200F CFG_CSO CFG_CLK SCP_DMD_RST_DI SCP_DMD_RST_DO SCP_DMD_RST_CLK SCP_DMD_EN DLPA200 Interface RST_A( 3:0 ) RST_MODE( 1:0 ) RST_SEL( 1:0 ) RST_OE DLPA200 RST_STB MBRST( 15:0 ) RST_RSTz RST_IRQz V1P2V VCC V1P8V V12V V2P5V VBIAS V3P3V VOFFSET VVCCA VRST VCCD_PLL VCCA_PLL Sync Out Interface VSS Illumination Interface VCC VCC2 VCCI VSS Figure 1. Block Diagram of 0.55 XGA Chipset 2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 DLP5500 www.ti.com DLPS013A – APRIL 2010 – REVISED JUNE 2010 Figure 2. Typical Application Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 3 DLP5500 DLPS013A – APRIL 2010 – REVISED JUNE 2010 www.ti.com Optically, the DLP5500 consists of 786,432 highly reflective, digitally switchable, micrometer-sized mirrors (“micromirrors”), organized in a two-dimensional array of 1024 micromirror columns by 768 micromirror rows (Figure 3). Each aluminum micromirror is approximately 10.8 microns in size (refer to “Micromirror Pitch” in Figure 3), and is switchable between two discrete angular positions: –12° and +12°. The angular positions are measured relative to a 0° “flat state”, which is parallel to the array plane (see Figure 4). The tilt direction is perpendicular to the hinge-axis which is positioned diagonally relative to the overall array, with the “On State” landed position directed towards “Row 0, Column 0” corner of the device package (refer to “Micromirror Hinge-Axis Orientation” in Figure 3). In the field of visual displays, the 1024 by 768 “pixel” resolution is referred to as "XGA". Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents. Writing a logic 1 into a memory cell will result in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a memory cell will result in the corresponding micromirror switching to a –12° position. Around the perimeter of the 1024 by 768 array of micromirrors is a uniform band of “border” micromirrors. The border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has been applied to the device. There are 10 border micromirrors on each side of the 1024 by 768 active array. The angular position (–12° or +12°) of the individual micromirrors changes synchronously with a micromirror “clocking pulse” (rather than being synchronous with the CMOS memory cell data update). The micromirror “clocking pulse” is referred to as a Mirror Reset. Application of the Mirror Reset signal results in each micromirror being electro-mechanically “latched” into the angular position dictated by the contents of the corresponding CMOS memory cell. The micromirror "clocking pulse" is input to the DLP5500 via the 16 "RESET" signals provided from the DLPA200 DMD Analog Reset Driver. Operationally, updating the angular position of the micromirror array consists of first updating the contents of the CMOS memory, followed by application of a Mirror Reset to all or a portion of the micromirror array (depending upon the configuration of the system). Mirror Reset pulses are generated by the DLPA200, with application of the pulses being coordinated by the DLPC200 controller. 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 DLP5500 www.ti.com DLPS013A – APRIL 2010 – REVISED JUNE 2010 Figure 3. DMD Micromirror Array, Pitch, and Hinge-Axis Orientation Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 5 DLP5500 www.ti.com Ill Inc um i d in en at t io n DLPS013A – APRIL 2010 – REVISED JUNE 2010 Ill Inc um id in en at t io n Package Pin-A1 Corner A A Two#“OnState” Micromirrors For Reference -Lig nt t Path id e Inc n-Ligh atio min ht P ath Illu tate Flat-State ( “parked” ) Micromirror Position Off -S nt t Path ide Inc n-Ligh atio min Projected-Light Path Illu A Two#“OffState” Micromirrors α±β -α ± β A Silicon Substrate Silicon Substrate “On-State” Micromirror A A “Off-State” Micromirror Figure 4. Micromirror Landed Positions and Light Paths 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 DLP5500 www.ti.com DLPS013A – APRIL 2010 – REVISED JUNE 2010 Related Documents The following documents contain additional information related to the use of the DLP5500 device: Related Documents DOCUMENT TI LITERATURE NUMBER DLP 0.55 XGA Chip-Set data sheet DLPZ004 DLPC200 Digital Controller data sheet DLPS014 DLPA200 DMD Analog Reset Driver DLPS015 s4xx DMD Mechanical & Thermal App note DLPA015 DLPC200 API Reference Manual DLPA024 DLPC200 API Programmer's Guide DLPA014 s4xx DMD Cleaning Application Note DLPA025 s4xx DMD Handling Application Note DLPA019 Orderable Part Number DLP5500FYA Package Type Device Descriptor Device Marking The device marking consists of the fields shown in Figure 5. DLP5500 Device Descriptor GHXXXXX LLLLLLM YYYYYYY *1076XXXXXX TI Internal Numbering Part 2 of Serial Number (7 characters) Part 1 of Serial Number (7 characters) 2-Dimensional Matrix Code (DLP5500 Device Descriptor and Serial No.) Figure 5. DMD Marking (Device Top View) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 7 DLP5500 DLPS013A – APRIL 2010 – REVISED JUNE 2010 www.ti.com Terminal Characteristics PIN See Figure 6 I/O/P TYPE INTERNAL TERMINATION CLOCKED BY Internal Trace Length (mils) (1) DATA RATE D_AN1 G20 Input LVCMOS Differential Terminated DCLK_A 715 LVDS TERMINAL NAME DESCRIPTION Data Inputs D_AP1 H20 Input LVCMOS Differential Terminated DCLK_A 744 LVDS D_AN3 H19 Input LVCMOS Differential Terminated DCLK_A 688 LVDS D_AP3 G19 Input LVCMOS Differential Terminated DCLK_A 703 LVDS D_AN5 F18 Input LVCMOS Differential Terminated DCLK_A 686 LVDS D_AP5 G18 Input LVCMOS Differential Terminated DCLK_A 714 LVDS D_AN7 E18 Input LVCMOS Differential Terminated DCLK_A 689 LVDS D_AP7 D18 Input LVCMOS Differential Terminated DCLK_A 705 LVDS D_AN9 C20 Input LVCMOS Differential Terminated DCLK_A 687 LVDS D_AP9 D20 Input LVCMOS Differential Terminated DCLK_A 715 LVDS D_AN11 B18 Input LVCMOS Differential Terminated DCLK_A 715 LVDS D_AP11 A18 Input LVCMOS Differential Terminated DCLK_A 732 LVDS D_AN13 A20 Input LVCMOS Differential Terminated DCLK_A 686 LVDS D_AP13 B20 Input LVCMOS Differential Terminated DCLK_A 715 LVDS D_AN15 B19 Input LVCMOS Differential Terminated DCLK_A 700 LVDS D_AP15 A19 Input LVCMOS Differential Terminated DCLK_A 719 LVDS D_BN1 K20 Input LVCMOS Differential Terminated DCLK_B 716 LVDS D_BP1 J20 Input LVCMOS Differential Terminated DCLK_B 745 LVDS D_BN3 J19 Input LVCMOS Differential Terminated DCLK_B 686 LVDS D_BP3 K19 Input LVCMOS Differential Terminated DCLK_B 703 LVDS D_BN5 L18 Input LVCMOS Differential Terminated DCLK_B 686 LVDS D_BP5 K18 Input LVCMOS Differential Terminated DCLK_B 714 LVDS D_BN7 M18 Input LVCMOS Differential Terminated DCLK_B 693 LVDS D_BP7 N18 Input LVCMOS Differential Terminated DCLK_B 709 LVDS D_BN9 P20 Input LVCMOS Differential Terminated DCLK_B 687 LVDS D_BP9 N20 Input LVCMOS Differential Terminated DCLK_B 715 LVDS D_BN11 R18 Input LVCMOS Differential Terminated DCLK_B 702 LVDS D_BP11 T18 Input LVCMOS Differential Terminated DCLK_B 719 LVDS D_BN13 T20 Input LVCMOS Differential Terminated DCLK_B 686 LVDS D_BP13 R20 Input LVCMOS Differential Terminated DCLK_B 715 LVDS D_BN15 R19 Input LVCMOS Differential Terminated DCLK_B 680 LVDS D_BP15 T19 Input LVCMOS Differential Terminated DCLK_B 700 LVDS DCLK_AN D19 Input LVCMOS Differential Terminated – 700 – DCLK_AP E19 Input LVCMOS Differential Terminated – 728 – DCLK_BN N19 Input LVCMOS Differential Terminated – 700 – DCLK_BP M19 Input LVCMOS Differential Terminated – 728 – SCTRL_AN F20 Input LVCMOS Differential Terminated DCLK_A 716 LVDS SCTRL_AP E20 Input LVCMOS Differential Terminated DCLK_A 731 LVDS SCTRL_BN L20 Input LVCMOS Differential Terminated DCLK_B 707 LVDS SCTRL_BP M20 Input LVCMOS Differential Terminated DCLK_B 722 LVDS Input data bus A Input data bus B Input data bus A Clock Input data bus B Clock Data Control Inputs Serial Communication & Configuration (1) 8 SCP_CLK A8 Input LVCMOS pull-down – – – SCP_DO A9 Output LVCMOS – SCP_CLK – – SCP_DI A5 Input LVCMOS pull-down SCP_CLK – – SCP_ENZ B7 Input LVCMOS pull-down SCP_CLK – – Internal Trace Length (mils) refers to the Package electrical trace length. Refer to the DLP 0.55 XGA Chip-Set Data Sheet (TI literature number DLPS012) for details regarding signal integrity considerations for end-equipment designs. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 DLP5500 www.ti.com DLPS013A – APRIL 2010 – REVISED JUNE 2010 Terminal Characteristics (continued) TERMINAL NAME PIN See Figure 6 I/O/P TYPE INTERNAL TERMINATION CLOCKED BY Internal Trace Length (mils) (1) DATA RATE PWRDNZ B9 Input LVCMOS pull-down – – – MODE_A A4 Input LVCMOS pull-down – – – MBRST0 C3 Input Analog – – – – MBRST1 D2 Input Analog – – – – MBRST2 D3 Input Analog – – – – MBRST3 E2 Input Analog – – – – MBRST4 G3 Input Analog – – – – MBRST5 E1 Input Analog – – – – MBRST6 G2 Input Analog – – – – MBRST7 G1 Input Analog – – – – MBRST8 N3 Input Analog – – – – MBRST9 M2 Input Analog – – – – MBRST10 M3 Input Analog – – – – MBRST11 L2 Input Analog – – – – MBRST12 J3 Input Analog – – – – MBRST13 L1 Input Analog – – – – MBRST14 J2 Input Analog – – – – MBRST15 J1 Input Analog – – – – VCC B11,B12,B13,B1 6,R12,R13,R16, R17 Power Analog – – – – Power for LVCMOS Logic VCCI A12,A14,A16,T1 2,T14,T16 Power Analog – – – – Power supply for LVDS Interface VCC2 C1,D1,M1,N1 Power Analog – – – – Power for High Voltage CMOS Logic VSS A6,A11,A13,A15, A17,B4,B5,B8,B1 4,B15,B17,C2,C1 8,C19,F1,F2,F19, H1,H2,H3,H18,J1 8,K1,K2,L19,N2, P18,P19,R4,R9, R14,R15,T7,T13, T15,T17 Power Analog – – – Common return for all power inputs Pins should be connected to VSS DESCRIPTION Micormirror Bias Reset Micromirror Bias Reset "MBRST" signals "clock" micromirrors into state of LVCMOS memory cell associated with each mirror. Power – Reserved Signals (Not for use in system) RESERVED_R7 R7 input LVCMOS pull-down – – – RESERVED_R8 R8 input LVCMOS pull-down – – – RESERVED_T8 T8 input LVCMOS pull-down – – – RESERVED_B6 B6 input LVCMOS pull-down – – – NO_CONNECT A3, A7, A10, B2, B3, B10, E3, F3, K3, L3, P1, P2, P3, R1, R2, R3, R5, R6, R10, R11, T1, T2, T3, T4, T5, T6, T9, T10, T11 – – – – – – DO NOT CONNECT Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 9 DLP5500 DLPS013A – APRIL 2010 – REVISED JUNE 2010 www.ti.com Figure 6. Series 450 Package Pins (Device Bottom View) 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 DLP5500 www.ti.com DLPS013A – APRIL 2010 – REVISED JUNE 2010 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under " Absolute Maximum Ratings” may cause permanent damage to the device. The Absolute Maximum Ratings are stress ratings only, and functional performance of the device at these or any other conditions beyond those indicated under “ Recommended Operating Conditions” is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability. PARAMETER CONDITIONS MIN Nom MAX UNIT VCC Voltage applied to VCC (1) (2) –0.5 4 V VCCI Voltage applied to VCCI (1) (2) –0.5 4 V |VID| Maximum differential voltage, Damage can occur to internal resistor if exceeded, See Figure 10 700 Delta supply voltage |VCC – VCCI| (1) (2) (3) mV .3 V VCC2 Voltage applied to VOFFSET –0.5 9 V VMBRST Voltage applied to MBRST[0:15] Input Pins -28 28 V Voltage applied to all other input terminals (1) –0.5 VCC + 0.3 V Current required from a high-level output VOH = 2.4 V –20 mA Current required from a low-level output VOL = 0.4 V 15 mA Device Operating and Non-operating Temperature Operating Temperature Micromirror Array Temperature (4) (5) (6) 10 70 Device Case Temperature - TC1, see Figure 13 10 80 Device Temperature Gradient (7) Non-operating Temperature Local ambient relative humidity (8) Illumination power density (9) 10 –40 80 Operating 95 Non-operating 95 < 420 nm (6) 20 420 to 700 (10) > 700 nm Electrostatic discharge immunity for LVCMOS pins (11) °C % mW/cm2 10 2000 V Elctrostatic discharge immunity for MBRST[0:15] pins 250 (1) (2) (3) All voltages referenced to VSS (ground). Voltages VCC, VCCI, and VCC2 are required for proper DMD operation. Exceeding the recommended allowable absolute voltage difference between VCC and VCCI may result in excess current draw. The difference between VCC and VCCI, | VCC - VCCI|, should be less than .3V. (4) Refer to Thermal Characteristics for Thermal Test Point Locations, Package Thermal Resistance, and Device Temperature Calculation. (5) Micromirror Array can operate from 0 °C to 10 °C at power up for a maximum of 10 minutes without damage (6) The maximum operating conditions for operating temperature and illumination power density for wavelengths < 420 nm shall not be implemented simultaneously. (7) As measured between the case temperature (TC1) and the predicted temperature of the Micromirror array. Refer to Thermal Characteristics for Thermal Test Point Locations, Package Thermal Resistance, and Device Temperature Calculation. (8) Non-condensing (9) Total integrated illumination power density, above or below the indicated wavelength threshold. (10) Limited only by the resulting micromirror array temperature. (11) Tested in accordance with JESD22-A114-B Electrostatic Discharge (ESD) sensitivity testing Human Body Model (HBM). Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 11 DLP5500 DLPS013A – APRIL 2010 – REVISED JUNE 2010 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits. PARAMETER CONDITIONS LVCMOS interface supply voltage (1) (2) VCC VCCI LVCMOS logic supply voltage (1) (2) Mirror electrode and HVCMOS supply voltage VCC2 (1) (2) VMBRST MIN NOM MAX 3.0 3.3 3.6 V 3.0 3.3 3.6 V 8.25 8.5 8.75 V 26.5 V -27 fDCLK_* DCLK_A & DCLK_B clock frequency fSCP_CLK SCP_CLK Frequency 150 Static load applied to each electrical interface area #1 & #2, See (3) Figure 7 Static load applied to the thermal interface area, See (4) Figure 7 Device Operating Temperature (1) (2) (3) (4) (5) (6) Operating Temperature Micromirror Array Temperature (5) (6) 10 UNIT MHz 500 KHz 55 N 111 N 70 °C All voltages referenced to VSS (ground). Voltages VCC, VCCI, and VCC2, are required for proper DMD operation. Load should be uniformly distributed across the entire Electrical Interface area #1 and #2. Load should be uniformly distributed across Thermal Interface Area. Refer to the for size and location of the datum-A surfaces. Refer to Thermal Characteristics for Thermal Test Point Locations, Package Thermal Resistance, and Device Temperature Calculation. In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. Refer to the Thermal Characteristics for further details. Figure 7. System Interface Loads 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 DLP5500 www.ti.com DLPS013A – APRIL 2010 – REVISED JUNE 2010 ELECTRICAL CHARACTERISTICS Over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted) PARAMETERS (Under RECOMMENDED OPERATING CONDITIONS) MIN VOH High-level output voltage (1), See Figure 8 VCC = 3.0 V, IOH = –20 mA VOL Low-level output voltage (1), See Figure 8 VCC = 3.6 V, IOH = 15 mA IOZ High impedance output current (1) VCC = 3.6 V IOH High-level output current (1) Low-level output current (1) IOL NOM MAX UNIT TEST CONDITIONS 2.4 V 0.4 V 10 µA VOH = 2.4 V, VCC ≥ 3.0 V –20 VOH = 1.7 V, VCC ≥ 2.25 V –15 VOL = 0.4 V, VCC ≥ 3.0 V 15 VOL = 0.4 V, VCC ≥ 2.25 V 14 mA mA VIH High-level input voltage (1) 1.7 VCC + .3 V VIL Low-level input voltage (1) -0.3 0.7 V µA (1) IIL Low-level input current VCC = 3.6 V, VI = 0 V –60 IIH High-level input current (1) VCC = 3.6 V, VI = VCC 200 µA ICC Current into VCC terminal VCC = 3.6 V, 750 mA ICCI Current into VOFFSET terminal (2) VCCI = 3.6 V 450 mA ICC2 Current into VCC2 terminal VCC2 = 8.75V ZIN Internal Differential Impedance 95 ZLINE Line Differential Impedance (PWB/Trace) 90 CI Input capacitance CO Output capacitance CIM Input capacitance for MBRST[0:15] pins (1) (2) (1) (1) 25 mA 105 Ohms 110 Ohms f = 1 MHz 10 pF f = 1 MHz 10 pF 210 pF f = 1 MHz 160 100 Applies to LVCMOS pins only. Exceeding the maximum allowable absolute voltage difference between VCC and VCCI may result in excess current draw. (Refer to Absolute Maximum Ratings for details) LOAD CIRCUIT RL From Output Under Test Tester Channel CL = 50 pF CL = 5 pF for Disable Time Figure 8. Measurment Condition for LVCMOS Output Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 13 DLP5500 DLPS013A – APRIL 2010 – REVISED JUNE 2010 www.ti.com SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) LVDS TIMING PARAMETERS See Figure 9 MIN NOM MAX UNIT Tc Clock Cycle DLCK_A or DCLKC_B Tw Pulse Width DCLK_A or DCLK_B 4.0 ns 1.25 ns Ts Setup Time, D_A[0:15] before DCLK_A .35 ns Ts Setup Time, D_B[0:15] before DCLK_B .35 ns Th Hold Time, D_A[0:15] after DCLK_A .35 ns Th Hold Time, D_B[0:15] after DCLK_B Tskew Channel B relative to Channel A .35 ns -1.25 1.25 ns 600 mV LVDS Waveform Requirements See Figure 10 |VID| Input Differential Voltage (absolute difference) VCM Common Mode Voltage VLVDS LVDS Voltage Tr Tr 100 400 1200 mV 0 2000 mV Rise Time (20% to 80%) 100 400 ps Fall Time (80% to 20%) 100 400 ps 50 500 KHz -300 300 ns 2600 ns Serial Control Bus Timing Parameters See Figure 11 and Figure 12 fSCP_CLK SCP Clock Frequency TSCP_SKEW Time between valid SCP_DI and rising edge of SCP_CLK TSCP_DELAY Time between valid SCP_DO and rising edge of SCP_CLK TSCP_ENZ Time between falling edge of SCP_ENZ and the first rising edge of SCP_CLK Tr_SCP Rise time for SCP signals 200 ns TfP Fall time for SCP signals 200 ns 30 ns Tw DCLK_AN DCLK_AP Th Tw Tc Ts Th Ts SCTRL_AN SCTRL_AP Tskew D_AN(15:0) D_AP(15:0) Tw DCLK_BN DCLK_BP Th Tw Tc Th Ts Ts SCTRL_BN SCTRL_BP D_BN(15:0) D_BP(15:0) Figure 9. LVDS Timing Waveforms 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 DLP5500 www.ti.com DLPS013A – APRIL 2010 – REVISED JUNE 2010 VLVDS (v) VLVDSmax = VCM + |½VID| VLVDSmax Tf (20% - 80%) VLVDS = V CM +/- | 1/2 V ID | VID VCM T r (20% - 80%) VLVDS min VLVDS min = 0 Time Figure 10. LVDS Waveform Requirements tr_SCP tf_SCP SCP_CLK SCP_CLK, SCP_DI, SCP_ENZ tSCP_SKEW Input Controller VCC VCC/2 0v SCP_DI tSCP_DELAY SCP_DO tSCP_ENZ SCP_ENZ Figure 11. Serial Communications Bus Timing Parameters Figure 12. Serial Communications Bus Waveform Requirements DMD Power-Up and Power-Down Procedures Repeated failure to adhere to the prescribed power-up and power-down procedures may affect device reliability. The DLP5500 power-up and power-down procedures are defined by the DLPC200 Datasheet (TI Literature number DLPS012) and the .55 XGA Chipset Datasheet (TI Literature number DLPZ004). These procedures must be followed to ensure reliable operation of the device. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 15 DLP5500 DLPS013A – APRIL 2010 – REVISED JUNE 2010 www.ti.com Micromirror Array Physical Characteristics Physical characteristics of the micromirror array are provided in . Additional details are provided in the Package Mechanical Characteristics section at the end of this document. Micromirror Array Physical Characteristics PARAMETER Number of active micromirror columns Number of active micromirror rows Micromirror pitch (1) (1) Micromirror active array height Micromirror active array width Micromirror array border (1) (2) (1) (1) (1) (2) VALUE UNITS 1024 micromirrors 768 micromirrors 10.8 microns 768 micromirrors 8.294 millimeters 1024 micromirrors 11.059 millimeters 10 mirrors/side See Figure 3 The mirrors that form the array border are hard-wired to tilt in the –12° (“Off”) direction once power is applied to the DMD (see Figure 3 and Figure 4). Micromirror Array Optical Characteristics TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-off’s between numerous component and system design parameters. Refer to the following Application Notes for additional details, considerations, and guidelines: • Single-Panel DLP™ Projection System Optics Application Report (TI literature number DLPA002) 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 DLP5500 www.ti.com DLPS013A – APRIL 2010 – REVISED JUNE 2010 Micromirror Array Optical Characteristics PARAMETER CONDITIONS MIN DMD “parked” state (1) (2) (3), see Figure 4 a Micromirror tilt angle b Micromirror tilt angle variation See Figure 4 –1 16 (10) (13) (14) See Figure 3 420 nm to 700 nm, with all micromirrors in the ON state Window refractive index (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) us us 0 44 45 68 46 micromirrors degrees % Corning Eagle 2000 or Corning Eagle XG Window material (1) (2) degrees 10 adjacent micromirrors Orientation of the micromirror axis-of-rotation (12) Micromirror array optical efficiency 1 22 140 Non-adjacent micromirrors Non Operating micromirrors (11) UNIT degrees 12 Micromirror Cross Over Time (9) Micromirror Switching Time MAX 0 DMD “landed” state (1) (4) (5)see Figure 4 (1) (4) (6) (7) (8) NOM at 546.1 nm 1.5090 Measured relative to the plane formed by the overall micromirror array “Parking” the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed by the overall micromirror array). When the micromirror array is “parked”, the tilt angle of each individual micromirror is uncontrolled. Additional variation exists between the micromirror array and the package datums, as shown in the Package Mechanical Characteristics section at the end of this document. When the micromirror array is “landed”, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of “1” will result in a micromirror “landing” in an nominal angular position of “+12 degrees”. A binary value of 0 will result in a micromirror “landing” in an nominal angular position of “-12 degrees”. Represents the “landed” tilt angle variation relative to the Nominal “landed” tilt angle. Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices. For some applications, it is critical to account for the micromirror tilt angle variation in the overall System Optical Design. With some System Optical Designs, the micromirror tilt angle varation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some System Optical Designs, the micromirror tilt angle variation between devices may result in colorimetry variations and/or system contrast varations. Micromirror Cross Over time is primarily a function of the natural response time of the micromirrors. Micromirror switching is controlled and coordinated by the DLPC200 (TI Literature number DLPS014) AND DLPA200 ( TI Literature number DLPS015). Nominal Switching time depends on the system implementation and represents the time for the entire micromirror array to be refreshed. Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the -12 degree position to +12 degree or vice versa. Measured relative to the package datums “B” and “C”, shown in the Package Mechanical Characteristics section at the end of this document. The minimum or maximum DMD optical efficiency observed in a specific application depends on numerous application-specific design variables, such as: (a) Illumination wavelength, bandwidth/line-width, degree of coherence (b) Illumination angle, plus angle tolerance (c) Illumination and projection aperture size, and location in the system optical path (d) IIllumination overfill of the DMD micromirror array (e) Aberrations present in the illumination source and/or path (f) Aberrations present in the projection path (g) Etc. The specified nominal DMD optical efficiency is based on the following use conditions: (a) Visible illumination (420 nm – 700 nm) (b) Input illumination optical axis oriented at 24° relative to the window normal (c) Projection optical axis oriented at 0° relative to the window normal (d) f/3.0 illumination aperture (e) f/2.4 projection aperture Based on these use conditions, the nominal DMD optical efficiency results from the following four components: (a) Micromirror array fill factor: nominally 92% (b) Micromirror array diffraction efficiency: nominally 86% (c) Micromirror surface reflectivity: nominally 88% (d) Window transmission: nominally 97% (single pass, through two surface transitions) (14) Does not account for the effect of micromirror switching duty cycle, which is application dependant. Micromirror switching duty cycle represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 17 DLP5500 DLPS013A – APRIL 2010 – REVISED JUNE 2010 www.ti.com Micromirror Array Optical Characteristics (continued) PARAMETER CONDITIONS Window flatness Per 25 mm Window Artifact Size Within the Window Aperture (15) (16) MIN NOM MAX 4 400 Window aperture See UNIT fringes um (15) (15) Refer to the Package Mechanical Characteristics section at the end of this document for details regarding the size and location of the window aperture. (16) Refers only to non-cleanable artifacts. Refer to DMD S4xx Glass Cleaning Procedure (TI Literature number DLPA025) and DMD S4xx Handling Specifications (TI Literature number DLPA014) for recommend handling and cleaning processes. Thermal Characteristics Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the maximum temperature of any individual micromirror in the active array, the maximum temperature of the window aperture, and the temperature gradient between case temperature and the predicted micromirror array temperature. (see Figure 13). Refer to the RECOMMEND OPERATING CONDITIONS for applicable temperature limits. Package Thermal Resistance The DMD is designed to conduct absorbed and dissipated heat to the back of the Series 450 package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the specified operational temperatures, refer to Figure 13. The total heat load on the DMD is typically driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Package Thermal Resistance Min Active Micromirror Array resistance to TC2 Nom Max Units 0.6 ºC/W Case Temperature The temperature of the DMD case can be measured directly. For consistency, a Thermal Test Point locations TC1 & TC2 are defined, as shown in Figure 13. 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 DLP5500 www.ti.com DLPS013A – APRIL 2010 – REVISED JUNE 2010 Figure 13. Thermal Test Point Location Micromirror Array Temperature Calculuation Micromirror array temperature cannot be measured directly; therefore it must be computed analytically from measurement points ( Figure 13), the package thermal resistance, the electrical power, and the illumination heat load. The relationship between micromirror array temperature and the case temperature are provided by the following equations: TArray = TCeramic + (QArray • RArray-To-Ceramic) QArray = QELE + QILL Where the following elements are defined as: TArray = computed micromirror array temperature (°C) TCeramic = Ceramic temperature (°C) (TC2 Location Figure 13) QArray = Total DMD array power (electrical + absorbed) (measured in Watts) RArray-To-Ceramic = thermal resistance of DMD package from array to TC2 (°C/Watt) (see Package Thermal Resistance) QELE = Nominal electrical power (Watts) QILL = Absorbed illumination energy (Watts) An example calculation is provided below based on a traditional DLP Video projection system. The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating frequencies. The nominal electrical power dissipation to be used in the calculation is 2.0 Watts. Thus, QELE = 2.0 Watts. The absorbed power from the illumination source is variable and depends on the operating state of the mirrors and the intensity of the light source. Based on modeling and measured data from DLP projection system QILL = CL2W• SL. Where CL2W is a Lumens to Watts constant, and can be estimated at 0.00288 Watt/Lumen Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 19 DLP5500 DLPS013A – APRIL 2010 – REVISED JUNE 2010 www.ti.com SL = Screen Lumens nominally measured to be 2000 lumens Qarray = 2.0 + (0.00288 • 2000) = 7.76 watts, Estimated total power on micromirror Array TCeramic = 55.0 °C, assumed system measurement Finally, TArray (micromirror active array temperature) is TArray= 55.0 °C + (7.76 watts • 0.6 °C/watt) = 59.7 °C For additional explanation of DMD Mechanical and Thermal calculations and considerations please refer to DLP Series-450 DMD and System Mounting Concepts (TI Literature number DLPA015). 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 DLP5500 www.ti.com DLPS013A – APRIL 2010 – REVISED JUNE 2010 Table 1. Revision History REVISION SECTION(S) * All A ABSOLUTE MAX RATINGS Related Documents COMMENT Initial release Changed VREF to VCCI Changed Illumination Power Density < 420nm Max spec to 20 mW/cm^2 Clarified Note 6 measurement point Added |VID| to absolute max table. Add VMBRSTto absolute max table Inserted additional releated documents Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLP5500 21 PACKAGE OPTION ADDENDUM www.ti.com 21-Jun-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DLP5500FYA ACTIVE CPGA FYA 149 165 TBD Call TI Call TI Purchase Samples DLP5500FYAT ACTIVE CPGA FYA 149 10 TBD Call TI Call TI Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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