APT4M120K 1200V, 4A, 4.00Ω Max N-Channel MOSFET Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET. A proprietary planar stripe design yields excellent reliability and manufacturability. Low switching loss is achieved with low input capacitance and ultra low Crss "Miller" capacitance. The intrinsic gate resistance and capacitance of the poly-silicon gate structure help control slew rates during switching, resulting in low EMI and reliable paralleling, even when switching at very high frequency. Reliability in flyback, boost, forward, and other circuits is enhanced by the high avalanche energy capability. TO-220 APT4M120K Single die MOSFET D G S TYPICAL APPLICATIONS FEATURES • Fast switching with low EMI/RFI • PFC and other boost converter • Low RDS(on) • Buck converter • Ultra low Crss for improved noise immunity • Two switch forward (asymmetrical bridge) • Low gate charge • Single switch forward • Avalanche energy rated • Flyback • RoHS compliant • Inverters Absolute Maximum Ratings Symbol ID Parameter Unit Ratings Continuous Drain Current @ TC = 25°C 4 Continuous Drain Current @ TC = 100°C 3 A IDM Pulsed Drain Current VGS Gate-Source Voltage ±30 V EAS Single Pulse Avalanche Energy 2 310 mJ IAR Avalanche Current, Repetitive or Non-Repetitive 2 A 1 15 Thermal and Mechanical Characteristics Max Unit W PD Total Power Dissipation @ TC = 25°C 225 RθJC Junction to Case Thermal Resistance 0.56 RθCS Case to Sink Thermal Resistance, Flat, Greased Surface TJ,TSTG Operating and Storage Junction Temperature Range TL Soldering Temperature for 10 Seconds (1.6mm from case) WT Package Weight Torque Mounting Torque ( TO-220 Package), 6-32 or M3 screw Microsemi Website - http://www.microsemi.com 0.11 -55 150 300 °C/W °C 0.22 oz 6.2 g 10 in·lbf 1.1 N·m 12-2006 Typ Rev A Min Characteristic 050-8103 Symbol Static Characteristics TJ = 25°C unless otherwise specified Symbol Parameter Test Conditions Min VBR(DSS) Drain-Source Breakdown Voltage VGS = 0V, ID = 250µA 1200 ∆VBR(DSS)/∆TJ Drain-Source On Resistance VGS(th) Gate-Source Threshold Voltage ∆VGS(th)/∆TJ VGS = 10V, ID = 2A 3 Zero Gate Voltage Drain Current IGSS Gate-Source Leakage Current Dynamic Characteristics VDS = 1200V VGS = 0V Forward Transconductance Ciss Input Capacitance Crss Reverse Transfer Capacitance Coss Output Capacitance 4.00 5 100 500 ±100 TJ = 125°C Min VGS = 0V, VDS = 25V f = 1MHz Effective Output Capacitance, Charge Related Co(er) 5 Effective Output Capacitance, Energy Related Typ 4.5 1385 17 100 Max Unit V V/°C Ω V mV/°C µA nA Unit S pF 40 VGS = 0V, VDS = 0V to 800V 20 Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge td(on) Turn-On Delay Time Resistive Switching Current Rise Time VDD = 800V, ID = 2A tf 1.41 3.32 4 -10 TJ = 25°C Test Conditions VDS = 50V, ID = 2A 4 td(off) Max TJ = 25°C unless otherwise specified Co(cr) tr Typ VGS = ±30V Parameter gfs 3 VGS = VDS, ID = 1mA Threshold Voltage Temperature Coefficient IDSS Symbol Reference to 25°C, ID = 250µA Breakdown Voltage Temperature Coefficient RDS(on) APT4M120K Turn-Off Delay Time 43 7 20 7.4 4.4 24 6.9 VGS = 0 to 10V, ID = 2A, VDS = 600V RG = 4.7Ω 6 , VGG = 15V Current Fall Time nC ns Source-Drain Diode Characteristics Symbol IS ISM Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) 1 Test Conditions MOSFET symbol showing the integral reverse p-n junction diode (body diode) Diode Forward Voltage ISD = 2A, TJ = 25°C, VGS = 0V trr Reverse Recovery Time ISD = 2A, VDD = 100V 3 Qrr Reverse Recovery Charge Peak Recovery dv/dt Typ Max Unit 4 A G VSD dv/dt Min D 15 S diSD/dt = 100A/µs, TJ = 25°C ISD ≤ 2A, di/dt ≤1000A/µs, VDD = 800V, TJ = 125°C 1.0 1150 16 V ns µC 10 V/ns 1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature. 2 Starting at TJ = 25°C, L = 155.0mH, RG = 4.7Ω, IAS = 2A. 050-8103 Rev A 12-2006 3 Pulse test: Pulse Width < 380µs, duty cycle < 2%. 4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS. 5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of VDS less than V(BR)DSS, use this equation: Co(er) = -6.30E-8/VDS^2 + 7.65E-9/VDS + 1.09E-11. 6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452) Microsemi reserves the right to change, without notice, the specifications and information contained herein. 12 V GS = 10V J V 8 6 TJ = 25°C 4 2 3.0 2.5 2.0 5V 1.5 1.0 4.5V 0.5 TJ = 125°C TJ = 150°C 0 30 25 20 15 10 5 0 VDS(ON), DRAIN-TO-SOURCE VOLTAGE (V) 0 VGS = 10V @ 2A VDS> ID(ON) x RDS(ON) MAX. 250µSEC. PULSE TEST @ <0.5 % DUTY CYCLE 14 ID, DRAIN CURRENT (A) 2.0 1.5 1.0 0.5 12 10 TJ = -55°C 8 TJ = 25°C 6 TJ = 125°C 4 2 0 0 25 50 75 100 125 150 0 -55 -25 TJ, JUNCTION TEMPERATURE (°C) Figure 3, RDS(ON) vs Junction Temperature 0 8 7 6 5 4 3 2 1 VGS, GATE-TO-SOURCE VOLTAGE (V) Figure 4, Transfer Characteristics 2,000 5 C, CAPACITANCE (pF) TJ = -55°C TJ = 25°C 3 TJ = 125°C 2 100 Coss 10 1 Crss 16 1.5 1.0 0.5 ID, DRAIN CURRENT (A) Figure 5, Gain vs Drain Current 800 1000 1200 600 400 200 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 6, Capacitance vs Drain-to-Source Voltage 12 VDS = 240V 10 VDS = 600V 8 6 VDS = 960V 4 2 60 50 40 30 20 10 Qg, TOTAL GATE CHARGE (nC) Figure 7, Gate Charge vs Gate-to-Source Voltage 0 0 16 ID = 2A 14 0 1 2.0 14 12 10 8 TJ = 25°C 6 TJ = 150°C 4 2 0 1.2 1.0 0.8 0.6 0.4 0.2 VSD, SOURCE-TO-DRAIN VOLTAGE (V) Figure 8, Reverse Drain Current vs Source-to-Drain Voltage 0 12-2006 0 Rev A 0 VGS, GATE-TO-SOURCE VOLTAGE (V) Ciss 4 ISD, REVERSE DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE 1,000 050-8103 RDS(ON), DRAIN-TO-SOURCE ON RESISTANCE 16 NORMALIZED TO 2.5 30 25 20 15 10 5 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 2, Output Characteristics Figure 1, Output Characteristics 3.0 = 6, 7, 8 & 9V GS TJ = -55°C ID, DRIAN CURRENT (A) ID, DRAIN CURRENT (A) T = 125°C 3.5 10 0 APT4M120K 4.0 APT4M120K 20 20 10 10 I I DM 13µs ID, DRAIN CURRENT (A) 13µs 1 100µs Rds(on) 1ms 10ms 0.1 100µs 1ms 1 100ms DC line Scaling for Different Case & Junction Temperatures: ID = ID(T = 25 C)*(TJ - TC)/125 DC line 0.1 10 100 1200 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 9, Forward Safe Operating Area 10ms TJ = 150°C TC = 25°C 100ms TJ = 125°C TC = 75°C 1 Rds(on) C ° 1 10 100 1200 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 10, Maximum Forward Safe Operating Area TJ (°C) TC (°C) 0.239 0.323 Dissipated Power (Watts) 0.0025 ZEXT ID, DRAIN CURRENT (A) DM 0.124 ZEXT are the external thermal impedances: Case to sink, sink to ambient, etc. Set to zero when modeling only the case to junction. Figure 11, Transient Thermal Impedance Model D = 0.9 0.50 0.40 0.7 0.30 0.5 0.20 0.3 t1 t2 t1 = Pulse Duration SINGLE PULSE 0.10 0 Note: PDM Z JC, THERMAL IMPEDANCE (°C/W) θ 0.60 t Duty Factor D = 1/t2 Peak TJ = PDM x ZθJC + TC 0.1 0.05 10-5 10-4 10-3 10-2 10-1 RECTANGULAR PULSE DURATION (seconds) Figure 12. Maximum Effective Transient Thermal Impedance Junction-to-Case vs Pulse Duration TO-220 (K) Package Outline e3 100% Sn Plated 1.39 (.055) 0.51 (.020) 12.192 (.480) 9.912 (.390) Drain 4.08 (.161) Dia. 3.54 (.139) 3.42 (.135) 2.54 (.100) 10.66 (.420) 9.66 (.380) 5.33 (.210) 4.83 (.190) 6.85 (.270) 5.85 (.230) 050-8103 Rev A 12-2006 3.683 (.145) MAX. 0.50 (.020) 0.41 (.016) 2.92 (.115) 2.04 (.080) 4.82 (.190) 3.56 (.140) 14.73 (.580) 12.70 (.500) 1.01 (.040) 3-Plcs. 0.83 (.033) 2.79 (.110) 2.29 (.090) 5.33 (.210) 4.83 (.190) Gate Drain Source 1.77 (.070) 3-Plcs. 1.15 (.045) Dimensions in Millimeters and (Inches) Microsemi's products are covered by one or more of U.S.patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 and foreign patents. US and Foreign patents pending. All Rights Reserved. 1.0