PHILIPS TDA1306T

INTEGRATED CIRCUITS
DATA SHEET
TDA1306T
Noise shaping filter DAC
Product specification
Supersedes data of September 1994
File under Integrated Circuits, IC01
1998 Jan 06
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
FEATURES
GENERAL DESCRIPTION
General
The TDA1306T is a dual CMOS digital-to-analog
converter with up-sampling filter and noise shaper.
The combination of oversampling up to 4fs, noise shaping
and continuous calibration conversion ensures that only
simple 1st-order analog post-filtering is required.
• Double-speed mode
• Digital volume control
• Soft mute function
• 12 dB attenuation
The TDA1306T supports the I2S-bus data input mode
(fsys = 256fs) with word lengths of up to 20 bits and the
LSB fixed serial data input format (fsys = 384fs) with word
lengths of 16, 18 or 20 bits. Two cascaded IIR filters
increase the sampling rate 4 times.
• Low power dissipation
• Digital de-emphasis
• TDA1305T pin compatible.
The DACs are of the continuous calibration type and
incorporate a special data coding. This ensures a high
signal-to-noise ratio, wide dynamic range and immunity to
process variation and component ageing.
Easy application
• Voltage output
• Only 1st-order analog post-filtering required
• Operational amplifiers and digital filter integrated
Two on-board operational amplifiers convert the
digital-to-analog current to an output voltage.
• Selectable system clock (fsys) 256fs or 384fs
• I2S-bus (fsys = 256fs) or 16, 18 or 20 bits LSB fixed
serial input format (fsys = 384fs)
• Single rail supply.
High performance
• Superior signal-to-noise ratio
• Wide dynamic range
• No zero crossing distortion
• Inherently monotonic
• Continuous calibration digital-to-analog conversion
combined with noise shaping technique.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TDA1306T
1998 Jan 06
NAME
DESCRIPTION
VERSION
SO24
plastic small outline package; 24 leads; body width 7.5 mm.
SOT137−1
2
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
QUICK REFERENCE DATA
All power supply pins VDD and VSS must be connected to the same external supply unit.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDD
digital supply voltage
4.5
5.0
5.5
V
VDDA
analog supply voltage
4.5
5.0
5.5
V
VDDO
operational amplifier
supply voltage
4.5
5.0
5.5
V
IDDD
digital supply current
VDDD = 5 V;
at code 00000H
−
5
8
mA
IDDA
analog supply current
VDDA = 5 V;
at code 00000H
−
3
5
mA
IDDO
operational amplifier
supply current
VDDO = 5 V;
at code 00000H
−
2
4
mA
VFS(rms)
full-scale output voltage
(RMS value)
VDDD = VDDA = VDDO = 5 V;
RL > 5 kΩ
0.935
1.1
1.265
V
RL
output load resistance
5
−
−
kΩ
at 0 dB signal level;
fi = 1 kHz;
−
−70
−
dB
−
0.032
−
%
at −60 dB signal level;
fi = 1 kHz;
−
−42
−32
dB
Analog signals
DAC performance
(THD + N)/S
total harmonic distortion
plus noise-to-signal ratio
−
0.8
2.5
%
S/N
signal-to-noise ratio
no signal; A-weighted
−
−108
−96
dB
BR
input bit rate at data input
fs = 44.1 kHz;
normal speed
−
−
2.822
Mbits/s
fs = 44.1 kHz;
double speed
−
−
5.645
Mbits/s
fsys
system clock frequency
(pin 12)
6.4
−
18.432
MHz
Tamb
operating ambient
temperature
−40
−
+85
°C
1998 Jan 06
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Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
BLOCK DIAGRAM
Fig.1 Block diagram.
1998 Jan 06
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Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
PINNING
SYMBOL PIN
DESCRIPTION
VDDA
1
analog supply voltage (+5 V)
VSSA
2
analog ground
TEST1
3
test input 1; pin should be connected
to ground
BCK
4
bit clock input
WS
5
word select input
DATA
6
data input
CLKS1
7
clock and format selection 1 input
CLKS2
8
clock and format selection 2 input
VSSD
9
digital ground
VDDD
10
digital supply voltage (+5 V)
TEST2
11
test input 2; pin should be connected
to ground
SYSCLK
12
system clock input 256fs or 384fs
APP3
13
application mode 3 input
APPL
14
application mode selection input
APP2
15
application mode 2 input
APP1
16
application mode 1 input
APP0
17
application mode 0 input
VOL
18
left channel output
FILTCL
19
capacitor for left channel 1st order
filter function; should be connected
between pins 19 and 18
FILTCR
20
capacitor for right channel 1st order
filter function; should be connected
between pins 20 and 21
VOR
21
right channel output
Vref
22
internal reference voltage for output
channels; 0.5VDDO (typ.)
VSSO
23
operational amplifier ground
VDDO
24
operational amplifier supply voltage
1998 Jan 06
Fig.2 Pin configuration.
5
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
The TDA1306T supports the following data input modes:
FUNCTIONAL DESCRIPTION
• I2S-bus with data word length of up to 20 bits
(fsys = 256fs)
The TDA1306T CMOS DAC incorporates an up-sampling
filter, a noise shaper, continuous calibrated current
sources and operational amplifiers.
• LSB fixed serial format with data word length of 16, 18
or 20 bits (fsys = 384fs). As this format idles on the MSB
it is necessary to know how many bits are being
transmitted.
System clock and data input format
The TDA1306T accommodates slave mode only.
Consequently, in all applications, the system devices must
provide the system clock. The system frequency is
selectable at pins CLKS1 and CLKS2 (see Table 1).
Table 1
The input formats are illustrated in Fig.9. Left and right
data channel words are time multiplexed.
Data input format and system clock
SYSTEM CLOCK
CLKS1
CLKS2
DATA INPUT FORMAT
NORMAL SPEED
DOUBLE SPEED
256fs
128fs
0
0
I2S-bus
0
1
LSB fixed 16 bits
384fs
192fs
1
0
LSB fixed 18 bits
384fs
192fs
1
1
LSB fixed 20 bits
384fs
192fs
Device operation
When the APPL pin is held HIGH and APP3 is held LOW,
pins APP0, APP1 and APP2 form a microcontroller
interface. When the APPL pin is held LOW, pins APP0,
APP1, APP2 and APP3 form a pseudo-static application
(TDA1305T pin compatible).
PSEUDO-STATIC APPLICATION MODE (APPL = LOGIC 0)
In this mode, the device operation is controlled by
pseudo-static application pins where:
APP0 = attenuation mode control
APP1 = double-speed mode control
APP2 = mute mode control
APP3 = de-emphasis mode control.
In the pseudo-static application mode the TDA1306T is pin
compatible with the TDA1305T slave mode.
The correspondence between TDA1306T pin number,
TDA1306T pin name, TDA1305T pin mnemonic and a
description of the effects is given in Table 2.
1998 Jan 06
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Philips Semiconductors
Product specification
Noise shaping filter DAC
Table 2
TDA1306T
Pseudo-static application mode
PIN
MNEMONIC
PIN NUMBER
TDA1305T
FUNCTION
VALUE
DESCRIPTION
APP0
17
ATSB
0
12 dB attenuation (from full scale) activated
(only if MUSB = logic 1)
1
full scale (only if MUSB = logic 1)
0
double-speed mode
1
normal-speed mode
samples decrease to mute level
APP1
16
DSMB
APP2
15
MUSB
0
1
level according to ATSB
APP3
13
DEEM1
0
de-emphasis OFF (44.1 kHz)
1
de-emphasis ON (44.1 kHz)
MICROCONTROLLER WRITE OPERATION SEQUENCE
MICROCONTROLLER APPLICATION MODE (APPL = LOGIC
1 AND APP3 = LOGIC 0)
The microcontroller write operation follows the following
sequence:
In this mode, the device operation is controlled by a set of
flags in an 8-bit mode control register. The 8-bit mode
control register is written by a microcontroller interface
where:
• APP2 is held LOW by the microcontroller
• Microcontroller data is clocked into the internal shift
register on the LOW-to-HIGH transition on pin APP1
APPL = logic 1
• Data D7 to D0 is latched into the appropriate control
register on the LOW-to-HIGH transition of pin APP2
(APP1 = HIGH)
APP0 = Data
APP1 = Clock
• If more data is clocked into the TDA1306T before the
LOW-to-HIGH transition on pin APP2 then only the last
8 bits are used
APP2 = RAB
APP3 = logic 0.
The correspondence between serial-to-parallel
conversion, mode control flags and a summary of the
effect of the control flags is given in Table 3.
Figures 3 and 4 illustrate the mode set timing.
• If less data is clocked into the TDA1306T unpredictable
operation will result
• If the LOW-to-HIGH transition of pin APP2 occurs when
APP1 = LOW, the command will be disregarded.
Fig.3 Microcontroller timing.
1998 Jan 06
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Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
between APP2 pulses. A minimum pause of 22 µs is
necessary between any two step-up or step-down
commands.
MICROCONTROLLER WRITE OPERATION SEQUENCE (REPEAT
MODE)
The same command can be repeated several times (e.g.
for fade function) by applying APP2 pulses as shown in
Fig.4. It should be noted that APP1 must stay HIGH
Fig.4 Microcontroller timing (repeat mode).
Table 3
Microcontroller mode control register
BIT POSITION
FUNCTION
DESCRIPTION
ACTIVE LEVEL
D7
ATSB
12 dB attenuation
(from full scale)
LOW
D6
DSMB
double speed
LOW
D5
MUSB
mute
LOW
D4
DEEM
de-emphasis
HIGH
1998 Jan 06
D3
FS
full scale
HIGH
D2
INCR
increment
HIGH
D1
DECR
decrement
HIGH
D0
not applicable
reserved
not applicable
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Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
Volume control
VOLUME CONTROL (PSEUDO-STATIC APPLICATION MODE)
A digital level control is incorporated in the TDA1306T
which performs the function of soft mute and attenuation
(pseudo-static application mode) or soft mute, attenuation,
fade, increment and decrement (microcontroller
application mode). The volume control of both channels
can be varied in small step changes determined by the
value of the internal fade counter where:
In the pseudo-static application mode (APPL = logic 0) the
digital audio output level is controlled by APP0
(attenuation) and APP2 (mute) so only the final volume
levels full scale, 12 dB (attenuate) and mute (−infinity dB)
can be selected. The mute function has priority over the
attenuation function. Accordingly, if MUSB is LOW, the
state of ATSB has no effect. An example of volume control
in this application mode is illustrated in Fig.5.
Audio level = counter × maximum level/120.
Where the counter is a 7-bit binary number between 0 and
120. The time taken for mute to vary from 120 to 0 is
1/120fs. For example, when fs = 44.1 kHz, the time taken
is approximately 3 ms.
Fig.5 Volume control (pseudo-static application mode).
1998 Jan 06
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Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
To control the fade counter in a continuous way, the
INCREMENT and DECREMENT commands are available
(fade control Registers D1 and D2). They will increment
and decrement the counter by 1 for each register write
operation. When issuing more than 1 step-up or
step-down command in sequence, the write repeat mode
may be used (see microcontroller application mode). An
example of volume control in this application mode is
illustrated in Fig.6.
VOLUME CONTROL (MICROCONTROLLER APPLICATION MODE)
In the microcontroller application mode (APPL = logic 1,
APP3 = logic 0) the audio output level is controlled by
volume control bits ATSB, MUSB, FS, INCR and DECR.
Mute is activated by sending the MUSB command to the
mode control register via the microcontroller interface. The
audio output level will be reduced to zero in a maximum of
120 steps (depending on the current position of the fade
counter) and taking a maximum of 3 ms. Mute, attenuation
and full scale are synchronized to prevent operation in the
middle of a word.
• The counter is preset to 120 by the full scale command
• The counter is preset to 30 by the attenuate command
when its value is more then 30. If the value of the
counter is less than 30 dB the ATSB command has no
effect.
• The counter is preset to logic 0 by the mute command
MUSB
• Attenuation (−12 dB) is activated by sending the ATSB
command to the fade control register (D7)
• Attenuation and mute are cancelled by sending the
full-scale command to the fade control register
(Register D3).
(1) INCR and DECR in repeat mode.
Fig.6 Volume control (microcontroller application mode).
1998 Jan 06
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Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
There are two recommended application situations within
the microcontroller mode:
Double-speed mode
The double-speed mode is controlled by the DSMB bit at
register D6 (microcontroller application mode) or by
activating the APP1 pin (pseudo-static application mode).
When the control bit is active LOW the device operates in
the double-speed mode.
• The customer wants to use the microcontroller interface
without the volume setting facility. In this event the
operation is as follows:
– Mute ON; by sending the MUSB command
– Mute OFF; by sending the FS command
Oversampling filter and noise shaper
– Attenuation ON; by sending the ATSB command
The digital filter is a four times oversampling filter.
It consists of two sections which each increase the sample
rate by 2. The noise-shaper operates on 4fs and reduces
the in-band noise density.
– Attenuation OFF; by sending the FS command.
It is possible to switch from ‘Attenuation ON’ to ‘Mute
ON’ but not vice-versa.
• Incorporating the volume control feature operates as
follows:
DAC and operational amplifiers
– Mute ON; by sending the MUSB command the
microcontroller has to store the previous volume
setting
In this noise shaping filter DAC a special data code and
bidirectional current sources are used in order to achieve
true low-noise performance. The special data code
guarantees that only small values of current flow to the
output during small signal passages while larger positive
or negative values are generated using the bidirectional
current sources. The noise shaping filter-DAC uses the
continuous calibration conversion technique.
– Mute OFF; by sending succeeding INCR commands
until the previous volume is reached
– Attenuation ON; by sending succeeding DECR
commands until a relative downstep of −12 dB is
reached.
The microcontroller has to store the previous volume
The operational amplifiers and the internal conversion
resistors RCONV1 and RCONV2 convert the DAC current to
an output voltage available at VOL and VOR. Connecting an
external capacitor between FILTCL and VOL, FILTCR and
VOR respectively provides the required 1st-order post
filtering.
– Attenuation OFF; by sending the succeeding INCR
commands until the previous volume is reached
– Volume UP; by sending succeeding INCR
commands
– Volume DOWN; by sending succeeding DECR
commands.
De-emphasis
A digital de-emphasis is implemented in the TDA1306T.
By selecting the DEEM bit at register D4 (microcontroller
application mode) or activating the APP3 pin
(pseudo-static application mode), de-emphasis can be
applied by means of an IIR filter. De-emphasis is
synchronized to prevent operation in the middle of a word.
1998 Jan 06
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Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD
supply voltage
−
7.0
V
Txtal
maximum crystal temperature
−
+150
°C
Tstg
storage temperature
−65
+125
°C
Tamb
operating ambient temperature
Ves
electrostatic handling
note 1
−40
+85
°C
note 2
−2000
+2000
V
note 3
−200
+200
V
Notes
1. All VDD and VSS connections must be made to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 mH series inductor.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
in free air
QUALITY SPECIFICATION
In accordance with “UZW-BO/FQ-0601”.
1998 Jan 06
12
VALUE
UNIT
69
K/W
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
DC CHARACTERISTICS
VDDD = VDDA = VDDO = 5 V; Tamb = 25 °C; all voltages referenced to ground (pins 2, 9 and 23); unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage (pin 10)
note 1
4.5
5.0
5.5
V
VDDA
analog supply voltage (pin 1)
note 1
4.5
5.0
5.5
V
VDDO
operational amplifier supply
voltage (pin 24)
note 1
4.5
5.0
5.5
V
IDDD
digital supply current
fsys = 11.28 MHz
−
5
8
mA
IDDA
analog supply current
at digital silence
−
3
6
mA
IDDO
operational amplifier supply
current
no operational
amplifier load resistor
−
2
4
mA
Ptot
total power dissipation
fsys = 11.28 MHz;
digital silence; no
operational amplifier
load resistor
−
50
90
mW
VIH
HIGH level digital input voltage
(pins 3 to 8 and 11 to 17)
0.7VDDD
−
VDDD + 0.5 V
VIL
LOW level digital input voltage
(pins 3 to 8 and 11 to 17)
−0.5
−
+0.3VDDD
V
Rpd
internal pull-down resistor to
VSSD (pins 3 and 11)
17
−
134
kΩ
|ILI|
input leakage current
−
−
10
µA
Ci
input capacitance
Vref
reference voltage (pin 22)
RCONV
current-to-voltage conversion
resistor
VFS(rms)
full-scale output voltage (RMS
value)
RL
output load resistance
with respect to VSSO
RL > 5 kΩ; note 2
−
−
10
pF
0.45VDDO
0.5VDDO
0.55VDDO
V
2.4
3.0
3.6
kΩ
0.935
1.1
1.265
V
5
−
−
kΩ
Notes
1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit.
2. RL is the AC resistance of the external circuitry connected to the audio outputs of the application circuit.
1998 Jan 06
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Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
AC CHARACTERISTICS (ANALOG)
VDDD = VDDA = VDDO = 5 V; Tamb = 25 °C; all voltages referenced to ground (pins 2, 9 and 23); unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DACs
SVRR
supply voltage ripple
rejection VDDA and VDDO
fripple = 1 kHz;
Vripple = 100 mV (p-p);
C22 = 10 µF
−
40
−
dB
∆Gv
unbalance between the
2 DAC voltage outputs
(pins 18 and 21)
maximum volume
−
−
0.5
dB
αct
crosstalk between the 2 DAC one output digital silence
−
voltage outputs
the other maximum volume
(pins 18 and 21)
−110
−85
dB
(THD + N)/S
total harmonic distortion
plus noise-to-signal ratio
−
−70
−
dB
S/N
signal-to-noise ratio
at 0 dB signal level;
fi = 1 kHz
−
0.032
−
%
at −60 dB signal level;
fi = 1 kHz
−
−42
−32
dB
−
0.8
2.5
%
no signal; A-weighted
−
−108
−96
dB
−
85
−
dB
Operational amplifiers
Gv
open-loop voltage gain
PSRR
power supply rejection ratio
fripple = 3 kHz;
Vripple = 100 mV (p-p);
A-weighted
−
90
−
dB
(THD + N)/S
total harmonic distortion
plus noise-to-signal ratio
RL > 5 kΩ; fi = 1 kHz;
Vo = 2.8 V (p-p)
−
−100
−
dB
fUG
unity gain frequency
open loop
−
4.5
−
MHz
|Zo|
AC output impedance
RL > 5 kΩ
−
1.5
150
Ω
1998 Jan 06
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Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
AC CHARACTERISTICS (DIGITAL)
VDDD = VDDA = VDDO 4.5 to 5.5 V; all voltages referenced to ground (pins 2, 9 and 23); Tamb = −40 to +85 °C; unless
otherwise specified.
SYMBOL
TWX
PARAMETER
clock cycle time
CONDITIONS
MIN.
TYP.
MAX.
UNIT
fsys = 384fs; normal speed
54.2
59.1
104
ns
fsys = 192fs; double speed
54.2
59.1
104
ns
fsys = 256fs; normal speed
81.3
88.6
156
ns
fsys = 128fs; double speed
81.3
88.6
156
ns
tCWL
fsys LOW level pulse width
22
−
−
ns
tCWH
fsys HIGH level pulse width
22
−
−
ns
Serial input data timing (see Fig.8)
fs
fBCK
word select input audio
sample frequency
normal speed
25
44.1
48
kHz
double speed
50
88.2
96
kHz
clock input frequency
(data input rate)
fsys = 384fs; normal speed; note 1
−
−
64fs
kHz
fsys = 192fs; double speed; note 1
−
−
64fs
kHz
fsys = 256fs; normal speed
−
−
64fs
kHz
fsys = 128fs; double speed; note 2
−
−
48fs
kHz
tr
rise time
−
−
20
ns
tf
fall time
−
−
20
ns
tH
bit clock HIGH time
55
−
−
ns
tL
bit clock LOW time
55
−
−
ns
tsu
data set-up time
20
−
−
ns
th
data hold time
10
−
−
ns
tsuWS
word select set-up time
20
−
−
ns
thWS
word select hold time
10
−
−
ns
Microcontroller interface timing (see Fig.9)
tL
input LOW time
2
−
−
µs
tH
Input HIGH time
2
−
−
µs
tsuDC
set-up time DATA to CLOCK
1
−
−
µs
thCD
hold time CLOCK to DATA
1
−
−
µs
tsuCR
set-up time CLOCK to RAB
1
−
−
µs
Notes
1. A clock frequency of up to 96fs is possible in the event of a rising edge of BCK occurring during SYSCLK = LOW.
2. A clock frequency of up to 64fs is possible in the event of a rising edge of BCK occurring during SYSCLK = LOW.
1998 Jan 06
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Philips Semiconductors
Product specification
TDA1306T
Fig.7 Data input formats.
Noise shaping filter DAC
1998 Jan 06
16
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
Fig.8 Timing of input signals.
Fig.9 Microcontroller timing.
1998 Jan 06
17
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
TEST AND APPLICATION INFORMATION
Filter characteristics
Table 4 Digital filter specification (fs = 44.1 kHz)
BAND
ATTENUATION
0 to 19 kHz
< 0.001 dB
19 to 20 kHz
< 0.03 dB
24 kHz
> 25 dB
25 to 35 kHz
> 40 dB
35 to 64 kHz
> 50 dB
64 to 68 kHz
> 31 dB
68 kHz
> 35 dB
69 to 88 kHz
> 40 dB
Table 5
Digital filter phase distortion (fs = 44.1 kHz)
BAND
0 to 16 kHz
1998 Jan 06
PHASE DISTORTION
< ±1°
18
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
PACKAGE OUTLINE
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
inches
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.61
0.60
0.30
0.29
0.050
0.419
0.043
0.055
0.394
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
Z
(1)
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT137-1
075E05
MS-013AD
1998 Jan 06
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
19
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
SOLDERING
Wave soldering
Introduction
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1998 Jan 06
20
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jan 06
21
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
NOTES
1998 Jan 06
22
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1306T
NOTES
1998 Jan 06
23
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© Philips Electronics N.V. 1998
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
547027/1200/02/pp24
Date of release: 1998 Jan 06
Document order number:
9397 750 03168