INTEGRATED CIRCUITS DATA SHEET SAA4700T VPS dataline processor Preliminary specification File under Integrated Circuits, IC02 March 1991 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700T FEATURES GENERAL DESCRIPTION • Adaptive sync slicer with buffered composite sync output VCS The SAA4700T is a bipolar integrated circuit designed for use in dataline receivers and incorporates a dataline slicer and decoder. The slicer extracts the dataline signal from the video signal and regenerates the data clock. It also provides signals for the decoder in order to decode the binary data that is transmitted in line 16 of every first field of the composite video signal (video programming signal and video recording programming by Teletext, VPS and VPT systems). The decoded information out of words 5 and 11 to 14 is accessed via the built-in I2C-bus interface. This information then can be used for programming a video cassette recorder in order to start and stop a recording of a television program at the correct aligned time, regardless of a delay or extension in the transmission time of the required program. • Adaptive data slicer • Data rate clock regenerator • Field selection and line 16 decoding • Startcode and biphase check • Data valid output • Storage of data line information in a 40 bit register bank • I2C-bus transmission QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VP supply voltage (pins 17 and 18) 4.5 5 5.5 V IP total supply current − 18 23 mA Vi CVBS CVBS input signal sync-to-white (peak-to-peak value) 0.5 1 1.4 V Tamb operating ambient temperature 0 − +70 °C ORDERING AND PACKAGE INFORMATION PACKAGE EXTENDED TYPE NUMBER SAA4700T PINS 20 PIN POSITION mini-pack Note 1. SOT163-1; 1996 November 13. March 1991 2 MATERIAL plastic CODE SOT163A (1) Philips Semiconductors Preliminary specification VPS dataline processor SAA4700T CSO handbook, full pagewidth DAV 0.1 µF (test line 16) 5 4.7 nF CVBS AD = LOW 12 13 8 9 2 SYNC SEPARATOR 470 pF SAA4700T 1 nF 6 1 FIELD SELECTOR LINE 16 DECODER line 16 DATA SLICER I2C-BUS CONTROL OUTPUT CONTROLLER 10 5 data 40 BIT DATA REGISTER INPUT CONTROLLER CLOCK REGENERATOR data 40 BIT DATA LATCH 4 7 MULTIPLEXER 6 14 to VP 4.7 nF VCS 15 19 20 PLL WITH 5 MHz VCO AND PHASE DETECTOR 22 nF 8.2 kΩ SDA 8 4.7 kΩ 75 kΩ (2%) SCL TIME BASE REFERENCE VOLTAGES POWER-ON RESET 16 3 clock pulse 4 17 0.1 µF 18 n.c. n.c. n.c. external reset 11 +5 V VP MGH128 Fig.1 Block diagram and test circuit. correct start code is detected (for timing of start code detection see Fig.3) words 5 and 11 to 14 are decoded, checked for biphase errors and stored in a register bank. If no biphase error has occurred, the contents of the register bank are transferred to a second register bank by the data valid control signal. If the system has been addressed, this transfer will be delayed until the next start or stop condition of the I2C-bus has been received. FUNCTIONAL DESCRIPTION Dataline 16 The information in dataline 16 consists of fifteen 8-bit words; the total information content is shown in Table 1; and the organization of transmitted bytes is shown in Table 2. Out of the fifteen possible 8-bit words the SAA4700T extracts words 5 and 11 to 14. The contents of these words can be read via the built-in I2C-bus interface. The circuit is fully transparent, thus each bit is transferred without modification with only the sequence of words being changed. Words 11 to 14 are transmitted first followed by word 5. The last bit of correct information on the dataline remains available until it is read via the I2C-bus. Once the stored information has been read it is considered to be no longer valid and the internal new data flag is reset. Subsequently, if the circuit is addressed, the only VPS data that will be sent back is “FFF to F”. The same conditions apply after power-up when no data can be read out. New data is available after reception of another error-free dataline 16. By evaluating the sliced sync signal the circuit can identify the beginning of dataline 16 in the first field. The dataline decoder stage releases the start code detector. When a March 1991 3 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700T PINNING SYMBOL PIN CONFIGURATION PIN DESCRIPTION CVBS 1 video signal input (CVBS from TV) SYNC 2 sync amplitude input (CVBS from TV) GND1 3 analog ground (0 V) GND2 4 digital ground (0 V) Cblack 5 capacitor for black level CSO 6 composite sync output n.c. 7 not connected AD 8 address set input SCL 9 I2C-bus clock line SDA 10 I2C-bus data line RS 11 TP 12 DAV 13 data available output active LOW n.c. 14 not connected Rosc 15 oscillator resistor for frequency adjustment handbook, halfpage CVBS 1 20 n.c. SYNC 2 19 Cph GND1 3 18 VP2 GND2 4 17 VP1 Cblack 5 16 CP SAA4700T CSO 6 15 Rosc reset input active LOW n.c. 7 14 n.c. test point for line 16 decoder AD 8 13 DAV SCL 9 12 TP SDA 10 11 RS CP 16 test point clock pulse VP1 17 +5 V supply voltage (digital part) VP2 18 +5 V supply voltage (analog part) Cph 19 capacitor of phase detector n.c. 20 not connected MBH797 Fig.2 Pin configuration. External reset CVBS input The circuit provides an internal power-on reset. When using this facility pin 11 should be connected to VP or, if external reset (RESET = LOW) is to be used pin 11 should be prepared by connecting pin 11 via a 10 kΩ pull-up resistor to VP. The CVBS signal is applied to the sync separator (pin 2) via a decoupling capacitor and to the data slicer (pin 1) via an RC high-pass filter. To enable proper storage of the sync value in the decoupling capacitor, the sync generator output resistance should not exceed 1 kΩ. Reset forces the following: Black level • I2C-bus not to acknowledge The capacitor connected to pin 5 stores the black level value for the adaptive sync slicer. • DAV output to go HIGH (pin 13) • I2C-bus transfer register to “FFF” March 1991 4 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700T Composite sync output (CSO) 5 MHz VCO and phase detector A composite sync output signal for customer application is provided (pin 6). The resistor connected between pin 15 and VP2 determines the current into the voltage controlled oscillator. The RC network connected to pin 19 acts as a low-pass filter for the phase detector. DAV output The data available output pin 13 is set LOW after an error free data line 16 is received. DAV returnes to HIGH after the beginning of the next first field. If no valid data is available DAV remains HIGH. Power supply To prevent crosscoupling the circuit is provided with separate ground and supply pins for analog and digital parts (pins 3, 4, 17 and 18). A short duration pulse of 1 µs (Fig.5) is inserted at the beginning of dataline 16; it will ensure that a HIGH-to-LOW transmission occurs which can then be used for triggering. Table 1 Information per word in dataline 16 WORD NUMBER CONTENT 1 run in 2 start code 3 program source identification (binary coded) 4 program source identification (ASCII sequential) 5 sound and VTR control information 6 program/test picture identification 7 internal information exchange 8 9 10 address assignment of signal distribution messages/commands 11 12 13 VTR control / information 14 15 March 1991 reserve 5 Philips Semiconductors Preliminary specification VPS dataline processor Table 2 SAA4700T VTR control information of dataline 16 VTR CONTROL INFORMATION Word number 5 1 Bit number 11 8 XXXXXXXX 12 0 7 8 13 15 16 14 23 24 31 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX AD Minute Label binary Word 5: Day Month Hour (1) Bit1 Bit2 Status 0 0 2-channel 0 1 Mono System status code 1 0 Stereo 1 1 2-channel Pause code Bit3 Bit4 Status 1 0 free 0 1 free Interrupt code Progr. source Special system code 1X00000111111111111111 NC...NC PC...PC 1X00000111111110111111 NC...NC PC...PC 1X00000111111101111111 NC...NC PC...PC Note 1. address range; NC = nation code; PC = program source code; X = 0 or 1 (bit) March 1991 Nation 6 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700T 0.2 µs handbook, full pagewidth clock signal to time base data to controller run in (word 1) start code (word 2) 1 0 0 0 1 1 0 1 1 0 1 1 word 3 0 0 1 1 1 0 1 0 0 1 0 error start code pulse biphase error pulse (ignored in word 2) MEH097 Fig.3 Timing diagram of start code detection. handbook, full pagewidth white level 0.7 V 0.5 V ±5% 1V sync level 12.5 ±1.5 µs 48 µs Fig.4 Timing diagram of dataline 16; modulation depth 71.4%. March 1991 7 MEH098 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700T word 15 word 14 word 13 word 12 word 11 word 10 word 9 word 8 word 6 word 5 word 4 word 3 word 2 CVBS input word 1 12.5 µs word 7 64 µs handbook, full pagewidth 48 µs DAV output 1 µs line 16 start code pulse word 5 latch pulse word 11 latch pulse word 14 latch pulse MEH096 Fig.5 Timing diagram of the data available output and word latch pulses. March 1991 8 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700T LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). Ground pins 3 and 4 as well as supply pins 17 and 18 tied together. SYMBOL PARAMETER MIN. MAX. UNIT VP1 supply voltage (pin 17) −0.5 6.0 V VP2 supply voltage (pin 18) −0.5 6.0 V Tstg storage temperature range −20 125 °C Tamb operating ambient temperature range 0 +70 °C THERMAL RESISTANCE SYMBOL PARAMETER Rth j-a MIN. MAX. − from junction to ambient in free air 130 UNIT K/W CHARACTERISTICS VP1 = VP2 = 5 V; Tamb = 25 °C; CVBS signal according to VPS and VPT standard and measurements taken in Fig.1, unless otherwise specified. SYMBOL PARAMETER VP1, VP2 supply voltages (pins 17 and 18) IP total supply current CONDITIONS MIN. TYP. MAX. UNIT 4.5 5 5.5 V I17 + I18 − 18 23 mA CVBS and sync inputs (pins 1 and 2) Vi CVBS CVBS input signal (peak-to-peak value) sync-to-white note 1; Fig.4 0.5 1 1.4 V Vi data data input signal (peak-to-peak value, pin 1) line 16; Fig.4 250 500 700 mV Vi sync sync input signal (peak-to-peak value, pin 2) 100 − 600 mV RS source resistance − − 1 kΩ − − 0.4 V Composite sync output (pin 6) VOL output voltage LOW VOH output voltage HIGH 2.4 − − V IOL output current LOW − − 200 µA IOH output current HIGH − − −500 µA td sync separator delay time − 0.3 − µs − − 0.4 V note 2 DAV output (pin 13) VOL output voltage LOW VOH output voltage HIGH 2.4 − − V IOL output current LOW − − 500 µA IOH output current HIGH − 0.01 1 µA March 1991 9 Philips Semiconductors Preliminary specification VPS dataline processor SYMBOL SAA4700T PARAMETER CONDITIONS MIN. TYP. MAX. UNIT SCL and SDA (pins 9 and 10) VIL input voltage LOW − − 1.5 V VIH input voltage HIGH 3 − − V II input current − − ±10 µA CI input capacitance − − 10 pF VO ACK output voltage during acknowledge on pin 10 − − 0.4 V tr rise time − − 1 µs tf fall time − − 0.3 µs tp L pulse duration LOW 4.7 − − µs tp H pulse duration HIGH 4.0 − − µs SCL clock frequency − − 100 kHz 0.9VP IOL = 3 mA AD set input (pin 8) note 2 VIL input voltage LOW address 23H 0 − 0.4 V VIH input voltage HIGH address 21H 2.4 − VP V RESET input (pin 11) note 2 VIL input voltage LOW reset active − − 0.4 V VIH input voltage HIGH reset non-active 2.4 − − V IIL input current LOW − − −10 µA IIH input current HIGH − 0.01 1 µA Notes 1. With standard sync and data amplitude of 68% to 75% black-white. 2. If the open collector output DAV is used, a pull-up resistor to VP1 is necessary. March 1991 10 Philips Semiconductors Preliminary specification VPS dataline processor handbook, full pagewidth SAA4700T +5 V VP 22 nF 4.7 nF 8.2 kΩ 75 kΩ (2%) 0.1 µF DAV n.c. n.c. 20 19 18 17 16 15 14 13 12 11 7 8 9 10 SCL SDA SAA4700T 1 2 1 nF 4.7 kΩ 3 4 5 6 0.1 µF 4.7 nF 470 pF n.c. CSO CVBS MEH136 Fig.6 Application circuit. I2C-BUS FORMAT S SLAVE ADDRESS A DATA A DATA A DATA A DATA A DATA S = start condition SLAVE ADDRESS = 0010 0001 or 0010 0011 for set input AD = HIGH respectively LOW on pin 8 (the circuit is only a slave transmitter) A = acknowledge, generated by the slave or the master DATA = five data bytes, see words in Table 1 P = stop condition respectively non-acknowledge by the microcontroller P Remarks to I2C-bus transmission • the MSB of each word is transmitted first • there is no restriction on the number of words to be transmitted, but if more than five words are requested, the following content will be “FF” continuously. • Normally every dataline transmission has to be ended with STOP condition by non-acknowledge of the controller. March 1991 11 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700T PACKAGE OUTLINE SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC March 1991 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 12 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700T SOLDERING Wave soldering Introduction Wave soldering techniques can be used for all SO packages if the following conditions are observed: There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SO packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. March 1991 13 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. March 1991 14