74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Rev. 3 — 8 June 2016
Product data sheet
1. General description
The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in
compliance with JEDEC standard no 7A.
2. Features and benefits
Low power consumption
VCO-Inhibit control for ON/OFF keying and for low standby power consumption
Center frequency up to 17 MHz (typical) at VCC = 4.5 V
Choice of three phase comparators:
PC1: EXCLUSIVE-OR
PC2: Edge-triggered J-K flip-flop
PC3: Edge-triggered RS flip-flop
Excellent Voltage Controlled Oscillator (VCO) linearity
Low frequency drift with supply voltage and temperature variations
Operating power supply voltage range:
VCO section 3.0 V to 6.0 V
Digital section 2.0 V to 6.0 V
Zero voltage offset due to operational amplifier buffering
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Applications
FM modulation and demodulation
Frequency synthesis and multiplication
Frequency discrimination
Tone decoding
Data synchronization and conditioning
Voltage-to-frequency conversion
Motor-speed control
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
4. Ordering information
Table 1.
Ordering information
Type number
74HC4046AD
Package
Name
Description
Version
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
SSOP16
plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
74HCT4046AD
74HC4046ADB
74HCT4046ADB
74HC4046APW
5. Block diagram
&
&$
&%
9&2B287
&203B,1
6,*B,1
$
3+$6(
&203$5$725
5 5
9&2
3+$6(
&203$5$725
5 3&B287 3&B287 5
3&3B287 5
5
3+$6(
&203$5$725
,1+
'(0B287
3&B287 &
9&2B,1
56
DDD
Fig 1.
Block diagram
74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
6. Functional diagram
&203B,1
6,*B,1
Fig 2.
3&B287
3&B287
3&B287
3&3B287
3&B287
3&B287
&203B,1
3&B287
3&3B287
6,*B,1
&$
&$
&%
&%
5
5
9&2B,1
,1+
9&2B287
9&2
'(0B287
5
5
9&2B,1
,1+
DDD
Logic symbol
Fig 3.
$
'(0B287
9&2B287
DDD
IEC logic symbol
&
&$
&%
9&2B287 &203B,1
6,*B,1
3&B287 5 9UHI
9&2
5
6'
4
5 3&B287 4
5'
5
'(0B287 C
'
4
83
3
&3
56
9&&
4
3&B287
5'
1
C
'
4
5'
,1+
5
4
&3
'2:1
5
*1'
3&3B287
&
9&2B,1
DDD
Fig 4.
Logic diagram
74HC_HCT4046A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
7. Pinning information
7.1 Pinning
+&$
+&7$
3&3B287 9&&
3&B287 3&B287
&203B,1 6,*B,1
9&2B287 3&B287
,1+ 5
&$ 5
&% '(0B287
*1' 9&2B,1
DDD
Fig 5.
Pin configuration
7.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
PCP_OUT
1
phase comparator pulse output
PC1_OUT
2
phase comparator 1 output
COMP_IN
3
comparator input
VCO_OUT
4
VCO output
INH
5
inhibit input
C1A
6
capacitor C1 connection A
C1B
7
capacitor C1 connection B
GND
8
ground (0 V)
VCO_IN
9
VCO input
DEM_OUT
10
demodulator output
R1
11
resistor R1 connection
R2
12
resistor R2 connection
PC2_OUT
13
phase comparator 2 output
SIG_IN
14
signal input
PC3_OUT
15
phase comparator 3 output
VCC
16
supply voltage
74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
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4 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
8. Functional description
The 74HC4046A; 74HCT4046A is a phase-locked-loop circuit that comprises a linear
voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and
PC3). It has a common signal input amplifier and a common comparator input (see
Figure 1). The signal input can be directly coupled to a large voltage signal, or indirectly
coupled (with a series capacitor) to a small voltage signal. A self-bias input circuit keeps
small voltage signals within the linear region of the input amplifiers. With a passive
low-pass filter, the 74HC4046A; 74HCT4046A forms a second-order loop PLL. The
excellent VCO linearity is achieved by the use of linear op amp techniques.
8.1 VCO
The VCO requires one external capacitor C1 (between pins C1A and C1B) and one
external resistor R1 (between pins R1 and GND). Alternatively, it requires two external
resistors R1 and R2 (between pins R1 and GND, and R2 and GND). Resistor R1 and
capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to
have a frequency offset if necessary (see Figure 4).
The high input impedance of the VCO simplifies the design of the low-pass filters by giving
the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is provided at pin DEM_OUT. In
contrast to conventional techniques, where the DEM_OUT voltage is one threshold
voltage lower than the VCO input voltage, the DEM_OUT voltage equals the VCO input. If
DEM_OUT is used, a series resistor (Rs) should be connected from pin DEM_OUT to
GND; if unused, DEM_OUT should be left open. The VCO output (pin VCO_OUT) can be
connected directly to the comparator input (pin COMP_IN), or connected via a frequency
divider. When the VCO input DC level is held constant, the VCO output signal has a duty
cycle of 50 % (maximum expected deviation 1 %). A LOW-level at the inhibit input
(pin INH) enables the VCO and demodulator, while a HIGH-level turns both off to
minimize standby power consumption.
The only difference between the 74HC4046A and 74HCT4046A is the input level
specification of the INH input. This input disables the VCO section. The sections of the
comparator are identical, so that there is no difference in the SIG_IN or COMP_IN inputs
between the 74HC4046A and 74HCT4046A.
8.2 Phase comparators
The input signal can be coupled to the self-biasing amplifier at pin SIG_IN, when the
signal swing is between the standard HC family input logic levels. Capacitive coupling is
required for signals with smaller swings.
74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 50
74HC4046A; 74HCT4046A
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Phase-locked loop with VCO
8.2.1 Phase Comparator 1 (PC1)
This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies
(fi) must have a 50 % duty cycle to obtain the maximum locking range. The transfer
characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is:
V CC
V DEM_OUT = ---------- SIG_IN – COMP_IN
where:
VDEM_OUT is the demodulator output at pin DEM_OUT
VDEM_OUT = VPC1_OUT (via low-pass filter)
V CC
The phase comparator gain is: K p = ---------- V r
PC1 is fed to the VCO input via the low-pass filter and seen at the demodulator output at
pin DEM_OUT (VDEM_OUT). The average output voltage from PC1 is the result of the
phase differences of signals (SIG_IN) and the comparator input (COMP_IN). These phase
differences are shown in Figure 6. The average of VDEM_OUT is equal to 0.5VCC when
there is no signal or noise at SIG_IN. Using this input, the VCO oscillates at the center
frequency (f0). Typical waveforms for the PC1 loop locked at f0 are shown in Figure 7.
The frequency capture range (2fc) is defined as the frequency range of input signals on
which the PLL locks when it was initially out-of-lock. The frequency lock range (2fL) is the
frequency range of the input signals on which the loop stays locked when it was initially in
lock. The capture range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass filter characteristics and can be
made as large as the lock range. This configuration remains locked even with very noisy
input signals. Typical behavior of this type of phase comparator is that it can lock to input
frequencies close to the harmonics of the VCO center frequency.
74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
9&&
9'(0B287
$9
9&&
'(0B287
DDD
V CC
V DEM_OUT = V PC1_OUT = ---------- SIG_IN – COMP_IN
DEM_OUT = SIG_IN – COMP_IN
Fig 6.
Phase comparator 1; average output voltage as a function of input phase
difference
6,*B,1
&203B,1
9&2B287
3&B287
9&&
9&2B,1
*1'
DDD
Fig 7.
74HC_HCT4046A
Product data sheet
Typical waveforms for PLL using phase comparator 1; loop-locked at f0
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Rev. 3 — 8 June 2016
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74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
8.2.2 Phase Comparator 2 (PC2)
PC2 is a positive edge-triggered phase and frequency detector. When the PLL uses this
comparator, positive signal transitions control the loop and the duty cycles of SIG_IN and
COMP_IN are not important. PC2 comprises two D-type flip-flops, control gating and a
3-state output stage. The circuit functions as an up-down counter (see Figure 4) where
SIG_IN causes an up-count and COMP_IN a down count. The transfer function of PC2,
assuming ripple (fr = fi) is suppressed, is:
V CC
V DEM_OUT = ---------- SIG_IN – COMP_IN
4
where:
VDEM_OUT is the demodulator output at pin DEM_OUT
VDEM_OUT = VPC2_OUT (via low-pass filter)
V CC
The phase comparator gain is: K p = ---------- V r
4
VDEM_OUT is the resultant of the initial phase differences of SIG_IN and COMP_IN as
shown in Figure 8. Typical waveforms for the PC2 loop locked at fo are shown in Figure 9.
When the SIG_IN and COMP_IN frequencies are equal but the phase of SIG_IN leads
that of COMP_IN, the p-type output driver at PC2_OUT is held ‘ON’. The time that it is
held ÓN’ corresponds to the phase difference (DEM_OUT). When the phase of SIG_IN
lags that of COMP_IN, the n-type driver is held ‘ON’.
When the SIG_IN frequency is higher than the COMP_IN frequency, the p-type output
driver is held ‘ON’ for most of the input signal cycle time. For the remainder of the cycle
time, both n- and p-type drivers are ‘OFF’ (3-state). If the SIG_IN frequency is lower than
the COMP_IN frequency, then it is the n-type driver that is held ‘ON’ for most of the cycle.
The voltage at capacitor (C2) of the low-pass filter, connected to PC2_OUT, varies until
the phase and frequency of the signal and comparator inputs are equal. At this stable
point, the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO_IN
input is in a high-impedance state. In this condition, the signal at the phase comparator
pulse output (PCP_OUT) is a HIGH level and can be used for indicating a locked
condition.
Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full
frequency range of the VCO. The power dissipation due to the low-pass filter is reduced
because both n- and p-type output drivers are ‘OFF’ for most of the signal input cycle. The
PLL lock range for this type of phase comparator is equal to the capture range and is
independent of the low-pass filter. With no signal present at SIG_IN the VCO adjust, via
PC2, to its lowest frequency.
74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
9&&
9'(0B287
$9
9&&
'(0B287
DDD
V CC
V DEM_OUT = V PC2_OUT = ---------- SIG_IN – COMP_IN
DEM_OUT = SIG_IN – COMP_IN
Fig 8.
Phase comparator 2; average output voltage as a function of input phase
difference
6,*B,1
&203B,1
9&2B287
9&&
3&B287
KLJKLPSHGDQFH2))VWDWH
*1'
9&2B,1
3&3B287
DDD
Fig 9.
74HC_HCT4046A
Product data sheet
Typical waveforms for PLL using phase comparator 2; loop-locked at f0
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Rev. 3 — 8 June 2016
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74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
8.2.3 Phase Comparator 3 (PC3)
PC3 is a positive edge-triggered sequential phase detector using an RS-type flip-flop.
When the PLL is using this comparator, positive signal transitions control the loop and the
duty factors of SIG_IN and COMP_IN are not important. The transfer characteristic of
PC3, assuming ripple (fr = fi) is suppressed, is:
V CC
V DEM_OUT = ---------- SIG_IN – COMP_IN
2
where:
VDEM_OUT is the demodulator output at pin DEM_OUT
VDEM_OUT = VPC3_OUT (via low-pass filter)
V CC
The phase comparator gain is: K p = ---------- V r
2
PC3 is fed to the VCO via the low-pass filter and seen at the demodulator output at
pin DEM_OUT. The average output from PC3 is the resultant of the phase differences of
SIG_IN and COMP_IN, see Figure 10. Typical waveforms for the PC3 loop locked at
fo are shown in Figure 11.
The phase-to-output response characteristic of PC3 (Figure 10) differs from PC2 in that
the phase angle between SIG_IN and COMP_IN varies between 0 and 360 It is 180 at
the center frequency. Also PC3 gives a greater voltage swing than PC2 for input phase
differences. As a result, the ripple content of the VCO input signal is higher. The PLL lock
range for this type of phase comparator and the capture range are dependent on the
low-pass filter. With no signal present at SIG_IN, the VCO adjusts to its lowest frequency
via PC3.
74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
10 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
9&&
9'(0B287
$9
9&&
'(0B287
DDD
V CC
V DEM_OUT = V PC3_OUT = ---------- SIG_IN – COMP_IN
DEM_OUT = SIG_IN – COMP_IN
Fig 10. Phase comparator 3; average output voltage as a function of input phase
difference
6,*B,1
&203B,1
9&2B287
3&B287
9&&
9&2B,1
*1'
DDD
Fig 11. Typical waveforms for PLL using phase comparator 3; loop-locked at f0
74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 50
74HC4046A; 74HCT4046A
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Phase-locked loop with VCO
9. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
0.5
+7
Unit
V
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
-
20
mA
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
-
20
mA
IO
output current
0.5 V < VO < VCC + 0.5 V
-
25
mA
ICC
supply current
-
+50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
-
500
mW
Tamb = 40 C to +125 C
[1]
SO16 and (T)SSOP16
[1]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
10. Recommended operating conditions
Table 4.
Recommended operating conditions
Symbol Parameter
VCC
Conditions
74HC4046A
Typ
Max
Min
Typ
Max
3.0
5.0
6.0
4.5
5.0
5.5
V
2.0
5.0
6.0
4.5
5.0
5.5
V
0
-
VCC
0
-
VCC
V
0
-
VCC
0
-
VCC
V
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
ns/V
input voltage
VO
output voltage
t/V
input transition rise and
fall rate
pin INH
VCC = 6.0 V
Tamb
ambient temperature
74HC_HCT4046A
Product data sheet
Unit
Min
supply voltage
when VCO is not used
VI
74HCT4046A
-
-
83
-
-
-
40
+25
+125
40
+25
+125
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Rev. 3 — 8 June 2016
C
© NXP Semiconductors N.V. 2016. All rights reserved.
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Phase-locked loop with VCO
11. Static characteristics
11.1 Static characteristics 74HC4046A
Table 5.
Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
1.5
1.2
-
V
VCC = 4.5 V
3.15
2.4
-
V
VCC = 6.0 V
4.2
3.2
-
V
VCC = 2.0 V
-
0.8
0.5
V
VCC = 4.5 V
-
2.1
1.35
V
VCC = 6.0 V
-
2.8
1.8
V
1.9
2.0
-
V
4.4
4.5
-
V
Phase comparator section; Tamb = 25 C
VIH
VIL
VOH
HIGH-level
input voltage
LOW-level
input voltage
pins SIG_IN, COMP_IN; DC coupled
pins SIG_IN, COMP_IN; DC coupled
HIGH-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
VOL
II
IOZ
RI
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
V
IO = 4 mA; VCC = 4.5 V
3.98
4.32
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48
5.81
-
V
LOW-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
input leakage
current
-
0
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
V
IO = 4 mA; VCC = 4.5 V
-
0.15
0.26
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
V
VCC = 2.0 V
-
-
3
A
VCC = 3.0 V
-
-
7
A
VCC = 4.5 V
-
-
18
A
VCC = 6.0 V
-
-
30
A
-
-
0.5
A
VCC = 3.0 V
-
800
-
k
VCC = 4.5 V
-
250
-
k
VCC = 6.0 V
-
150
-
k
pins SIG_IN, COMP_IN; VI = VCC or GND
OFF-state
pin PC2_OUT; VI = VIH or VIL; VO = VCC or GND
output current
VCC = 6.0 V
input
resistance
74HC_HCT4046A
Product data sheet
pins SIG_IN, COMP_IN; VI at self-bias operating point;
VI = 0.5 V; see Figure 12, 13 and 14
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Rev. 3 — 8 June 2016
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74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
Table 5.
Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCO section; Tamb = 25 C
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
pin INH
VCC = 3.0 V
2.1
1.7
-
V
VCC = 4.5 V
3.15
2.4
-
V
VCC = 6.0 V
4.2
3.2
-
V
VCC = 3.0 V
-
1.3
0.9
V
VCC = 4.5 V
-
2.1
1.35
V
VCC = 6.0 V
-
2.8
1.8
V
pin INH
HIGH-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 3.0 V
2.9
3.0
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
V
IO = 4 mA; VCC = 4.5 V
3.98
4.32
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48
5.81
-
V
-
0
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
V
IO = 4 mA; VCC = 4.5 V
-
0.15
0.26
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
V
LOW-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 3.0 V
pins C1A, C1B; VI = VIH or VIL
II
input leakage
current
IO = 4 mA; VCC = 4.5 V
-
-
0.40
V
IO = 5.2 mA; VCC = 6.0 V
-
-
0.40
V
pins INH, VCO_IN; VI = VCC or GND
-
-
0.1
A
3
-
300
k
3
-
300
k
40
-
no
limit
pF
VCC = 3.0 V
1.1
-
1.9
V
VCC = 4.5 V
1.1
-
3.4
V
VCC = 6.0 V
1.1
-
4.9
V
VCC = 6.0 V
R1
resistor 1
VCC = 3.0 V to 6.0 V
[1]
R2
resistor 2
VCC = 3.0 V to 6.0 V
[1]
C1
capacitor 1
VCC = 3.0 V to 6.0 V
VVCO_IN voltage on pin over the range specified for R1; for linearity
VCO_IN
see Figure 22 and 23
74HC_HCT4046A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
14 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
Table 5.
Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
50
-
300
k
VCC = 3.0 V
-
30
-
mV
VCC = 4.5 V
-
20
-
mV
VCC = 6.0 V
-
10
-
mV
-
25
-
-
-
8.0
A
-
3.5
-
pF
VCC = 2.0 V
1.5
-
-
V
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 2.0 V
-
-
0.5
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
1.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
Demodulator section; Tamb = 25 C
Rs
series
resistance
at Rs > 300 k, the leakage current can influence VDEM_OUT
Voffset
offset voltage
VCO_IN to VDEM_OUT; VI = VVCO_IN = 0.5VCC; values taken
over Rs range; see Figure 15
Rdyn
dynamic
resistance
VCC = 3.0 V to 6.0 V
DEM_OUT; VDEM_OUT = 0.5VCC
VCC = 3.0 V to 6.0 V
General; Tamb = 25 C
ICC
supply current VCO disabled; pins COMP_IN, INH and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
CI
input
capacitance
VCC = 6.0 V
pin INH
Phase comparator section; Tamb = 40 C to +85 C
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
pins SIG_IN, COMP_IN; DC coupled
pins SIG_IN, COMP_IN; DC coupled
HIGH-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 4 mA; VCC = 4.5 V
3.84
-
-
V
IO = 5.2 mA; VCC = 6.0 V
5.34
-
-
V
-
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
IO = 4 mA; VCC = 4.5 V
-
-
0.33
V
IO = 5.2 mA; VCC = 6.0 V
-
-
0.33
V
LOW-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
74HC_HCT4046A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
15 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
Table 5.
Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
II
pins SIG_IN, COMP_IN; VI = VCC or GND
IOZ
input leakage
current
Min
Typ
Max
VCC = 2.0 V
-
-
4
A
VCC = 3.0 V
-
-
9
A
VCC = 4.5 V
-
-
23
A
VCC = 6.0 V
-
-
38
A
-
-
5
A
VCC = 3.0 V
2.1
-
-
V
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 3.0 V
-
-
0.9
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
2.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
IO = 4 mA; VCC = 4.5 V
3.84
-
-
V
IO = 5.2 mA; VCC = 6.0 V
5.34
-
-
V
-
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
OFF-state
pin PC2_OUT; VI = VIH or VIL; VO = VCC or GND
output current
VCC = 6.0 V
Unit
VCO section; Tamb = 40 C to +85 C
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
pin INH
pin INH
HIGH-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 3.0 V
LOW-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 3.0 V
IO = 4 mA; VCC = 4.5 V
-
-
0.33
V
IO = 5.2 mA; VCC = 6.0 V
-
-
0.33
V
IO = 4 mA; VCC = 4.5 V
-
-
0.47
V
IO = 5.2 mA; VCC = 6.0 V
-
-
0.47
V
-
-
1
A
-
-
80.0
A
pins C1A, C1B; VI = VIH or VIL
II
input leakage
current
pins INH, VCO_IN; VI = VCC or GND
VCC = 6.0 V
General; Tamb = 40 C to +85 C
ICC
supply current VCO disabled; pins COMP_IN, INH and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC = 6.0 V
74HC_HCT4046A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
16 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
Table 5.
Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Phase comparator section; Tamb = 40 C to +125 C
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
pins SIG_IN, COMP_IN; DC coupled
VCC = 2.0 V
1.5
-
-
V
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 2.0 V
-
-
0.5
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
pins SIG_IN, COMP_IN; DC coupled
HIGH-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
1.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
IO = 4 mA; VCC = 4.5 V
3.7
-
-
V
IO = 5.2 mA; VCC = 6.0 V
5.2
-
-
V
-
-
0.1
V
-
-
0.1
V
LOW-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
II
IOZ
input leakage
current
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
IO = 4 mA; VCC = 4.5 V
-
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
-
0.4
V
VCC = 2.0 V
-
-
5
A
VCC = 3.0 V
-
-
11
A
VCC = 4.5 V
-
-
27
A
VCC = 6.0 V
-
-
45
A
-
-
10
A
pins SIG_IN, COMP_IN; VI = VCC or GND
OFF-state
pin PC2_OUT; VI = VIH or VIL; VO = VCC or GND
output current
VCC = 6.0 V
VCO section; Tamb = 40 C to +125 C
VIH
VIL
HIGH-level
input voltage
LOW-level
input voltage
74HC_HCT4046A
Product data sheet
pin INH
VCC = 3.0 V
2.1
-
-
V
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 3.0 V
-
-
0.9
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
pin INH
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
17 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
Table 5.
Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOH
Conditions
Min
Typ
Max
2.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
IO = 4 mA; VCC = 4.5 V
3.7
-
-
V
IO = 5.2 mA; VCC = 6.0 V
5.2
-
-
V
-
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
IO = 4 mA; VCC = 4.5 V
-
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
-
0.4
V
IO = 4 mA; VCC = 4.5 V
-
-
0.54
V
IO = 5.2 mA; VCC = 6.0 V
-
-
0.54
V
-
-
1
A
-
-
HIGH-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 3.0 V
LOW-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 3.0 V
VOL
Unit
pins C1A, C1B; VI = VIH or VIL
input leakage
current
II
pins INH, VCO_IN; VI = VCC or GND
VCC = 6.0 V
General; Tamb = 40 C to +125 C
supply current VCO disabled; pins COMP_IN, INH and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
ICC
VCC = 6.0 V
[1]
160.0 A
The parallel value of R1 and R2 should be more than 2.7 k. Optimum performance is achieved when R1 and/ or R2 are/is > 10 k.
74HC_HCT4046A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
18 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
11.2 Static characteristics 74HCT4046A
Table 6.
Static characteristics 74HCT4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
3.15
2.4
-
V
-
2.1
1.35
V
4.4
4.5
-
V
3.98
4.32
-
V
Phase comparator section; Tamb = 25 C
VIH
VIL
VOH
HIGH-level
input voltage
pins SIG_IN, COMP_IN; DC coupled
LOW-level
input voltage
pins SIG_IN, COMP_IN; DC coupled
VCC = 4.5 V
VCC = 4.5 V
HIGH-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 A; VCC = 4.5 V
VOL
LOW-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
II
IOZ
RI
input leakage
current
0
0.1
V
-
0.15
0.26
V
-
-
30
A
-
-
0.5
A
-
250
-
k
2.0
1.6
-
V
-
1.2
0.8
V
4.4
4.5
-
V
3.98
4.32
-
V
-
0
0.1
V
-
0.15
0.26
V
-
-
0.40
V
-
-
0.1
A
pins SIG_IN, COMP_IN; VI = VCC or GND
VCC = 5.5 V
OFF-state
pin PC2_OUT; VI = VIH or VIL; VO = VCC or GND
output current
VCC = 5.5 V
input
resistance
-
pins SIG_IN, COMP_IN; VI at self-bias operating point;
VI = 0.5 V; see Figure 12, 13 and 14
VCC = 4.5 V
VCO section; Tamb = 25 C
VIH
VIL
VOH
HIGH-level
input voltage
pin INH
LOW-level
input voltage
pin INH
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
HIGH-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
VOL
LOW-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
pins C1A, C1B; VI = VIH or VIL
IO = 4 mA; VCC = 4.5 V
II
input leakage
current
pins INH, VCO_IN; VCC = 5.5 V; VI = VCC or GND
R1
resistor 1
VCC = 4.5 V
[1]
3
-
300
k
R2
resistor 2
VCC = 4.5 V
[1]
3
-
300
k
C1
capacitor 1
VCC = 4.5 V
40
-
no
limit
pF
1.1
-
3.4
V
VVCO_IN voltage on pin over the range specified for R1;
VCO_IN
for linearity see Figure 22 and 23
VCC = 4.5 V
74HC_HCT4046A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
19 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
Table 6.
Static characteristics 74HCT4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
50
-
300
k
-
20
-
mV
-
25
-
-
-
8.0
A
-
100
360
A
-
3.5
-
pF
3.15
-
-
V
-
-
1.35
V
4.4
-
-
V
3.84
-
-
V
-
-
0.1
V
-
-
0.33
V
-
-
38
A
-
-
5
A
Demodulator section; Tamb = 25 C
Rs
series
resistance
at Rs > 300 k, the leakage current can influence VDEM_OUT
Voffset
offset voltage
VCO_IN to VDEM_OUT; VI = VVCO_IN = 0.5VCC; values taken
over Rs range; see Figure 15
VCC = 4.5 V
VCC = 4.5 V
Rdyn
dynamic
resistance
DEM_OUT; VDEM_OUT = 0.5VCC
VCC = 4.5 V
General; Tamb = 25 C
ICC
supply current VCO disabled; pins COMP_IN, INH and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC = 6 V
ICC
additional
pin INH; VI = VCC 2.1 V; pins COMP_IN and SIG_IN at VCC;
supply current pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC = 4.5 V to 5.5 V
CI
input
capacitance
pin INH
Phase comparator section; Tamb = 40 C to +85 C
VIH
VIL
VOH
HIGH-level
input voltage
pins SIG_IN, COMP_IN; DC coupled
LOW-level
input voltage
pins SIG_IN, COMP_IN; DC coupled
VCC = 4.5 V
VCC = 4.5 V
HIGH-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
VOL
LOW-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
II
IOZ
input leakage
current
pins SIG_IN, COMP_IN; VI = VCC or GND
VCC = 5.5 V
OFF-state
pin PC2_OUT; VI = VIH or VIL; VO = VCC or GND
output current
VCC = 5.5 V
74HC_HCT4046A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
20 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
Table 6.
Static characteristics 74HCT4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
2.0
-
-
V
-
-
0.8
V
VCO section; Tamb = 40 C to +85 C
VIH
HIGH-level
input voltage
pin INH
VIL
LOW-level
input voltage
pin INH
VOH
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
HIGH-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
VOL
LOW-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
4.4
-
-
V
3.84
-
-
V
-
-
0.1
V
-
-
0.33
V
-
-
0.47
V
-
-
1
A
-
-
80.0
A
-
-
450
A
3.15
-
-
V
-
-
1.35
V
pins C1A, C1B; VI = VIH or VIL
IO = 4 mA; VCC = 4.5 V
II
input leakage
current
pins INH, VCO_IN; VI = VCC or GND
VCC = 5.5 V
General; Tamb = 40 C to +85 C
ICC
supply current VCO disabled; pins COMP_IN, INH and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC = 6 V
ICC
additional
pin INH; VI = VCC 2.1 V; pins COMP_IN and SIG_IN at VCC;
supply current pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC = 4.5 V to 5.5 V
Phase comparator section; Tamb = 40 C to +125 C
VIH
HIGH-level
input voltage
pins SIG_IN, COMP_IN; DC coupled
VIL
LOW-level
input voltage
pins SIG_IN, COMP_IN; DC coupled
VOH
VCC = 4.5 V
VCC = 4.5 V
HIGH-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
VOL
LOW-level
pins PCP_OUT, PCn_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
II
IOZ
input leakage
current
Product data sheet
-
-
V
-
-
V
-
-
0.1
V
-
-
0.4
V
-
-
45
A
-
-
10
A
pins SIG_IN, COMP_IN; VI = VCC or GND
VCC = 5.5 V
OFF-state
pin PC2_OUT; VI = VIH or VIL; VO = VCC or GND
output current
VCC = 5.5 V
74HC_HCT4046A
4.4
3.7
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
21 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
Table 6.
Static characteristics 74HCT4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
2.0
-
-
V
-
-
0.8
V
VCO section; Tamb = 40 C to +125 C
VIH
HIGH-level
input voltage
pin INH
VIL
LOW-level
input voltage
pin INH
VOH
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
HIGH-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
LOW-level
pin VCO_OUT; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
VOL
IO = 4 mA; VCC = 4.5 V
4.4
-
-
V
3.7
-
-
V
-
-
0.1
V
-
-
0.4
V
-
-
0.54
V
-
-
1
A
-
-
-
-
pins C1A, C1B; VI = VIH or VIL
IO = 4 mA; VCC = 4.5 V
input leakage
current
II
pins INH, VCO_IN; VI = VCC or GND
VCC = 5.5 V
General; Tamb = 40 C to +125 C
supply current VCO disabled; pins COMP_IN, INH and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
ICC
VCC = 6 V
ICC
additional
pin INH; VI = VCC 2.1 V; pins COMP_IN and SIG_IN at VCC;
supply current pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC = 4.5 V to 5.5 V
[1]
160.0 A
490
A
The parallel value of R1 and R2 should be more than 2.7 k. Optimum performance is achieved when R1 and/ or R2 are/is > 10 k.
74HC_HCT4046A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
22 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
11.3 Graphs
DDD
,,
5,
Nȍ
9,
9&& 9
9
VHOIELDVRSHUDWLQJSRLQW
9
9,
DDD
Fig 12. Typical input resistance curve at SIG_IN and
COMP_IN
DDD
9&&
9&&
9&&
Fig 13. Input resistance at SIG_IN, COMP_IN with
VI = 0.5 V at self-bias point
DDD
9&& 9
9,9
9RIIVHW
P9
,,
$
9
9&& 9
9
9
9
9
9
9&&
9
9&&
9,9
9&&
9&&
9&&
9&&
99&2B,19
___ Rs = 50 k
- - - Rs = 300 k
Fig 14. Input current at SIG_IN, COMP_IN with
VI = 0.5 V at self-bias point
74HC_HCT4046A
Product data sheet
Fig 15. Offset voltage at demodulator output as a
function of VCO_IN and Rs
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
23 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
12. Dynamic characteristics
12.1 Dynamic characteristics 74HC4046A
Table 7.
Dynamic characteristics 74HC4046A[1]
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
-
63
200
ns
VCC = 4.5 V
-
23
40
ns
-
18
34
ns
VCC = 2.0 V
-
96
340
ns
VCC = 4.5 V
-
35
68
ns
-
28
58
ns
VCC = 2.0 V
-
77
270
ns
VCC = 4.5 V
-
28
54
ns
-
22
46
ns
VCC = 2.0 V
-
83
280
ns
VCC = 4.5 V
-
30
56
ns
-
24
48
ns
VCC = 2.0 V
-
99
325
ns
VCC = 4.5 V
-
36
65
ns
-
29
55
ns
VCC = 2.0 V
-
19
75
ns
VCC = 4.5 V
-
7
15
ns
VCC = 6.0 V
-
6
13
ns
VCC = 2.0 V
-
9
-
mV
VCC = 3.0 V
-
11
-
mV
VCC = 4.5 V
-
15
-
mV
VCC = 6.0 V
-
33
-
mV
Phase comparator section; Tamb = 25 C
tpd
propagation
delay
pins SIG_IN, COMP_IN to PC1_OUT; see Figure 16
[1]
VCC = 6.0 V
pins SIG_IN, COMP_IN to PCP_OUT; see Figure 16
[1]
VCC = 6.0 V
pins SIG_IN, COMP_IN to PC3_OUT; see Figure 16
[1]
VCC = 6.0 V
ten
enable time
pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17
[1]
VCC = 6.0 V
tdis
disable time
pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17
[1]
VCC = 6.0 V
tt
Vi(p-p)
transition time
peak-to-peak
input voltage
74HC_HCT4046A
Product data sheet
[1]
see Figure 16
pins SIGN_IN, COMP_IN; AC coupled; fi = 1 MHz
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74HC4046A; 74HCT4046A
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Phase-locked loop with VCO
Table 7.
Dynamic characteristics 74HC4046A[1] …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 3.0 V
7.0
10.0
-
MHz
VCC = 4.5 V
11.0
17.0
-
MHz
VCC = 5.0 V
-
19.0
-
MHz
VCC = 6.0 V
13.0
21.0
-
MHz
VCC = 3.0 V
-
1.0
-
%
VCC = 4.5 V
-
0.4
-
%
VCC = 6.0 V
-
0.3
-
%
-
50
-
%
-
24
-
pF
VCC = 2.0 V
-
-
250
ns
VCC = 4.5 V
-
-
50
ns
-
-
43
ns
VCC = 2.0 V
-
-
425
ns
VCC = 4.5 V
-
-
85
ns
-
-
72
ns
VCC = 2.0 V
-
-
340
ns
VCC = 4.5 V
-
-
68
ns
-
-
58
ns
VCC = 2.0 V
-
-
350
ns
VCC = 4.5 V
-
-
70
ns
-
-
60
ns
VCC = 2.0 V
-
-
405
ns
VCC = 4.5 V
-
-
81
ns
VCC = 6.0 V
-
-
69
ns
VCO section; Tamb = 25 C
f0
f/f
center
frequency
relative
frequency
variation
duty cycle
VVCO_IN = 0.5VCC; duty cycle = 50 %; R1 = 3 k;
R2 = ; C1 = 40 pF; see Figure 20 and Figure 21
R1 = 100 k; R2 = ; C1 = 100 pF;
see Figure 22 and Figure 23
pin VCO_OUT; VCC = 3.0 V to 6.0 V
General; Tamb = 25 C
CPD
[3]
power
dissipation
capacitance
Phase comparator section; Tamb = 40 C to +85 C
tpd
propagation
delay
pins SIG_IN, COMP_IN to PC1_OUT; see Figure 16
[1]
VCC = 6.0 V
pins SIG_IN, COMP_IN to PCP_OUT; see Figure 16
[1]
VCC = 6.0 V
pins SIG_IN, COMP_IN to PC3_OUT; see Figure 16
[1]
VCC = 6.0 V
ten
enable time
pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17
[1]
VCC = 6.0 V
tdis
disable time
74HC_HCT4046A
Product data sheet
pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17
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Phase-locked loop with VCO
Table 7.
Dynamic characteristics 74HC4046A[1] …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol
tt
Parameter
transition time
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
-
-
95
ns
VCC = 4.5 V
-
-
19
ns
VCC = 6.0 V
-
-
16
ns
VCC = 3.0 V
-
0.20
-
%/K
VCC = 4.5 V
-
0.15
-
%/K
VCC = 6.0 V
-
0.14
-
%/K
VCC = 2.0 V
-
-
300
ns
VCC = 4.5 V
-
-
60
ns
-
-
51
ns
VCC = 2.0 V
-
-
510
ns
VCC = 4.5 V
-
-
102
ns
-
-
87
ns
VCC = 2.0 V
-
-
405
ns
VCC = 4.5 V
-
-
81
ns
-
-
69
ns
VCC = 2.0 V
-
-
420
ns
VCC = 4.5 V
-
-
84
ns
-
-
71
ns
VCC = 2.0 V
-
-
490
ns
VCC = 4.5 V
-
-
98
ns
VCC = 6.0 V
-
-
83
ns
[1]
see Figure 16
VCO section; Tamb = 40 C to +85 C
f/T
frequency
variation with
temperature
VVCO_IN = 0.5VCC; R1 = 100 k; R2 = k;
C1 = 100 pF; see Figure 18 and Figure 19
Phase comparator section; Tamb = 40 C to +125 C
tpd
propagation
delay
pins SIG_IN, COMP_IN to PC1_OUT; see Figure 16
[1]
VCC = 6.0 V
pins SIG_IN, COMP_IN to PCP_OUT; see Figure 16
[1]
VCC = 6.0 V
pins SIG_IN, COMP_IN to PC3_OUT; see Figure 16
[1]
VCC = 6.0 V
ten
enable time
pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17
[1]
VCC = 6.0 V
tdis
disable time
74HC_HCT4046A
Product data sheet
pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17
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Phase-locked loop with VCO
Table 7.
Dynamic characteristics 74HC4046A[1] …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol
tt
Parameter
transition time
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
-
-
110
ns
VCC = 4.5 V
-
-
22
ns
VCC = 6.0 V
-
-
19
ns
[1]
see Figure 16
[1]
tpd is the same as tPLH and tPHL. tdis is the same as tPLZ and tPHZ. ten is the same as tPZL and tPZH. tt is the same as tTLH and tTHL.
[2]
Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator
sections, see Figure 24, Figure 25 and Figure 26
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = total load switching outputs;
(CL VCC2 fo) = sum of outputs.
12.2 Dynamic characteristics 74HCT4046A
Table 8.
Dynamic characteristics 74HCT4046A[1]
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Phase comparator section; Tamb = 25 C
tpd
propagation
delay
pins SIG_IN, COMP_IN to PC1_OUT; VCC = 4.5 V;
see Figure 16
[1]
-
23
40
ns
pins SIG_IN, COMP_IN to PCP_OUT; VCC = 4.5 V;
see Figure 16
[1]
-
35
68
ns
pins SIG_IN, COMP_IN to PC3_OUT; VCC = 4.5 V;
see Figure 16
[1]
-
28
54
ns
ten
enable time
pins SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V;
see Figure 17
[1]
-
30
56
ns
tdis
disable time
pins SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V;
see Figure 17
[1]
-
36
65
ns
tt
transition time
VCC = 4.5 V; see Figure 16
[1]
-
7
15
ns
Vi(p-p)
peak-to-peak
input voltage
pins SIGN_IN, COMP_IN; AC coupled; VCC = 4.5 V;
fi = 1 MHz
-
15
-
mV
VCO section; Tamb = 25 C
f0
center
frequency
VVCO_IN = 0.5VCC; duty cycle = 50 %; R1 = 3 k;
R2 = ; C1 = 40 pF; see Figure 20 and Figure 21
VCC = 4.5 V
11.0
17.0
-
MHz
VCC = 5.0 V
-
19.0
-
MHz
f/f
relative
frequency
variation
R1 = 100 k; R2 = ; C1 = 100 pF; VCC = 4.5 V;
see Figure 22 and Figure 23
-
0.4
-
%
duty cycle
pin VCO_OUT; VCC = 4.5 V
-
50
-
%
74HC_HCT4046A
Product data sheet
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Phase-locked loop with VCO
Table 8.
Dynamic characteristics 74HCT4046A[1] …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[2][3]
-
24
-
pF
pins SIG_IN, COMP_IN to PC1_OUT; VCC = 4.5 V;
see Figure 16
[1]
-
-
50
ns
pins SIG_IN, COMP_IN to PCP_OUT; VCC = 4.5 V;
see Figure 16
[1]
-
-
85
ns
pins SIG_IN, COMP_IN to PC3_OUT; VCC = 4.5 V;
see Figure 16
[1]
-
-
68
ns
General; Tamb = 25 C
power
dissipation
capacitance
CPD
Phase comparator section; Tamb = 40 C to +85 C
propagation
delay
tpd
ten
enable time
pins SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V;
see Figure 17
[1]
-
-
70
ns
tdis
disable time
pins SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V;
see Figure 17
[1]
-
-
81
ns
tt
transition time
VCC = 4.5 V; see Figure 16
[1]
-
-
19
ns
0.15
-
-
VCO section; Tamb = 40 C to +85 C
f/T
frequency
variation with
temperature
VVCO_IN = 0.5VCC; R1 = 100 k; R2 = k;
C1 = 100 pF; VCC = 4.5 V; see Figure 18b
%/K
Phase comparator section; Tamb = 40 C to +125 C
propagation
delay
tpd
pins SIG_IN, COMP_IN to PC1_OUT; VCC = 4.5 V;
see Figure 16
[1]
-
-
60
ns
pins SIG_IN, COMP_IN to PCP_OUT; VCC = 4.5 V;
see Figure 16
[1]
-
-
102
ns
pins SIG_IN, COMP_IN to PC3_OUT; VCC = 4.5 V;
see Figure 16
[1]
-
-
81
ns
ten
enable time
pins SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V;
see Figure 17
[1]
-
-
84
ns
tdis
disable time
pins SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V;
see Figure 17
[1]
-
-
98
ns
tt
transition time
VCC = 4.5 V; see Figure 16
[1]
-
-
22
ns
[1]
tpd is the same as tPLH and tPHL. tdis is the same as tPLZ and tPHZ. ten is the same as tPZL and tPZH. tt is the same as tTLH and tTHL.
[2]
Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator
sections, see Figure 24, Figure 25 and Figure 26
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = total load switching outputs;
(CL VCC2 fo) = sum of outputs.
74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
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Phase-locked loop with VCO
12.3 Waveforms and graphs
,13876
6,*B,1
&203B,1
90
2873876
W3+/
3&B287
3&B287
3&3B287
W3/+
90
W7+/
W7/+
DDD
VM = 0.5VCC; VI = GND to VCC.
Fig 16. Waveforms showing input (SIG_IN, COMP_IN) to output (PC1_OUT, PC3_OUT, PCP_OUT) propagation
delays and the output transition times
90
6,*B,1
,13876
90
&203B,1
W3=+
W3+=
287387
W3=/
W3/=
90
3&B287
DDD
VM = 0.5VCC; VI = GND to VCC.
Fig 17. Waveforms showing the enable and disable times for PC2_OUT
74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
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74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
I
I
I
9&& 9
9
9
9&& 9
9
9
$
9
9
9
9
9
9
9
9
D
7DPE&
E
7DPE&
9
9
9
9
9&& 9
F
7DPE&
DDD
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
In (b), the frequency stability for R1 = R2 = 10 k at 5 V is also given (curve A). The total VCO bias current sets this curve, and
is not simply the addition of the two 10 k stability curves. C1 = 100 pF; VVCO_IN = 0.5VCC; This curve is set as follows:
___ Without offset R2 = k: (a) R1 = 3 k; (b) R1 = 10 k; (c) R1 = 300 k.
- - - With offset R1 = k: (a) R2 = 3 k; (b) R2 = 10 k; (c) R2 = 300 k.
Fig 18. Frequency stability of the VCO as a function of ambient temperature
74HC_HCT4046A
Product data sheet
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Phase-locked loop with VCO
I
I
I
9&& 9
9
9
9&& 9
9
9
D
7DPE&
9
9
9&& 9
7DPE&
E
F
7DPE&
DDD
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
___ With offset; R1 = k: (a) R2 = 3 k; (b) R2 = 10 k; (c) R2 = 300 k.
Fig 19. Frequency stability of the VCO as a function of ambient temperature
74HC_HCT4046A
Product data sheet
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74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
I9&2
0+]
9&& 9
I9&2
0+]
9
9&& 9
9
9
9
99&2B,19
D
99&2B,19
E
DDD
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
(a) R1 = 3 k; C1 = 40 pF (b) R1 = 3 k; C1 = 100 nF
Fig 20. Graphs showing VCO frequency as a function of the VCO input voltage
74HC_HCT4046A
Product data sheet
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74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
9&& 9
I9&2
0+]
9
I9&2
0+]
9&& 9
9
9
9
99&2B,19
D
99&2B,19
E
DDD
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
(a) R1 = 300 k; C1 = 40 pF (b) R1 = 300 k; C1 = 100 nF
Fig 21. Graphs showing VCO frequency as a function of the VCO input voltage
74HC_HCT4046A
Product data sheet
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74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
9&& 9
I9&2
& )
9
9
I
I
9&& 9
& S)
I
I
9
9
& S)
I
9
9
9
PLQ
9&&
PD[
99&2B,1
5Nȍ
DDD
DDD
V = 0.5 V over the VCC range.
R2 = ; V = 0.5 V
f1 + f2
f‘ 0 = -------------2
f‘ 0 – f 0
linearity = ---------------- 100 %
f‘ 0
Fig 22. Definition of VCO frequency linearity
Fig 23. Frequency linearity as a function of R1, C1
DDD
DDD
35
:
35
:
9&&
9&&
9
9
9
9
9
9
5Nȍ
5Nȍ
R2 = ; CL = 50 pF; VVCO_IN = 0.5VCC; Tamb = 25 C
R1 = ; CL = 50 pF; VVCO_IN = GND; Tamb = 25 C
___ C1 = 40 pF; - - - C1 = 1 F
___ C1 = 40 pF; - - - C1 = 1 F
Fig 24. Power dissipation as a function of R1
74HC_HCT4046A
Product data sheet
Fig 25. Power dissipation as a function of R2
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74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
DDD
3'(0
:
9&&
9
9
9
56Nȍ
R1 = R2 = ; VVCO_IN = 0.5VCC; Tamb = 25 C
Fig 26. Typical power dissipation of demodulator sections as a function of Rs
74HC_HCT4046A
Product data sheet
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Phase-locked loop with VCO
13. Application information
This information is a guide for the approximation of values of external components to be
used with the 74HC4046A; 74HCT4046A in a phase-locked-loop system.
References should be made to Figure 30, Figure 31 and Figure 32 as indicated in
Table 10.
Values of the selected components should be within the ranges shown in Table 9.
Table 9.
Survey of components
Component
Value
R1
between 3 k and 300 k
R2
between 3 k and 300 k
R1 + R2
parallel value > 2.7 k
C1
> 40 pF
Table 10.
Design considerations for VCO section
Subject
Phase
comparator
Design consideration
VCO frequency
without extra
offset
PC1, PC2 or PC3
VCO frequency characteristic. With R2 = and R1 within the range 3 k < R1 <
300 k, the characteristics of the VCO operation is as shown in Figure 27a. (Due to
R1, C1 time constant a small offset remains when R2 = ).
PC1
Selection of R1 and C1. Given f0, determine the values of R1 and C1 using
Figure 30.
PC2 or PC3
Given fmax and f0, determine the values of R1 and C1 using Figure 30; use Figure 32
to obtain 2fL and then use it to calculate fmin.
VCO frequency
PC1, PC2 or PC3
with extra offset
VCO frequency characteristic with R1 and R2 within the ranges 3 k < R1 < 300 k,
3 k < R2 < 300 k. The characteristics of the VCO operation are as shown in
Figure 27b.
PC1, PC2 or PC3
Selection of R1, R2 and C1. Given f0 and fL determine the value of product R1C1 by
using Figure 32. Calculate foff from the equation foff = f0 1.6fL. Obtain the values of
C1 and R2 by using Figure 31. Calculate the value of R1 from the value of C1 and
the product R1C1.
PLL conditions
no signal at pin
SIG_IN
74HC_HCT4046A
Product data sheet
PC1
VCO adjusts to f0 with DEM_OUT = 90 and VVCO_IN = 0.5VCC, see Figure 6
PC2
VCO adjusts to f0 with DEM_OUT = 360 and VVCO_IN = minimum, see Figure 8
PC3
VCO adjusts to f0 with DEM_OUT = 360 and VVCO_IN = minimum, see Figure 10
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74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
I9&2
IPD[
I/
I
IPLQ
9
9&&
9&&9
GXHWR
5&
9&&
9&2B,1
DDD
a. Operating without offset; f0 = center frequency; 2fL = frequency lock range.
I9&2
IPD[
I
I/
IPLQ
IRII
GXHWR
5&
GXHWR
5&
9
9&&
9&&9
9&&
9&2B,1
DDD
b. Operating with offset; f0 = center frequency; 2fL = frequency lock range.
Fig 27. Frequency characteristic of VCO
74HC_HCT4046A
Product data sheet
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74HC4046A; 74HCT4046A
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Phase-locked loop with VCO
Table 11.
General design considerations
Subject
Phase comparator
Design consideration
PLL frequency capture range
PC1, PC2 or PC3
Loop filter component selection, see Figure 28 and 29
PLL locks on harmonics at
center frequency
PC1 or PC3
yes
PC2
no
Noise rejection at signal input
PC1
high
PC2 or PC3
low
AC ripple content when PLL is
locked
PC1
fr = 2fi; large ripple content at DEM_OUT = 90
PC2
fr = fi; small ripple content at DEM_OUT = 0
PC3
fr = fi; large ripple content at DEM_OUT = 180
)MȦ
5
LQSXW
&
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R3 500 .
A small capture range (2fc) is obtained if
(a) = R3 x C2
1
2f c = --- 2f L
(b) amplitude characteristics
(c) pole-zero diagram
Fig 28. Simple loop filter for PLL without offset
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R3 + R4 500 .
(a) 1 = R3 x C2; 2 = R4 x C2; 3 = (R3 + R4) x C2
(b) amplitude characteristics
(c) pole-zero diagram
Fig 29. Simple loop filter for PLL with offset
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74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
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To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.
Interpolation for various values of R1 can be easily calculated because a constant R1C1 product produces almost the same
VCO output frequency.
R2 = ; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 C.
Fig 30. Typical value of VCO center frequency (f0) as a function of C1
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Interpolation for various values of R2 can be easily calculated because a constant R2C1 product produces almost the same
VCO output frequency.
R1 = ; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 C.
Fig 31. Typical value of frequency offset as a function of C1
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74HC4046A; 74HCT4046A
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Phase-locked loop with VCO
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VVCO_IN = 0.9 V to (VCC 0.9) V; R2 = .
2f L
V VCO_IN range
VCO gain: K v = --------------------------------------- 2 r s V
Fig 32. Typical frequency lock range (2fL) as a function of the product R1C1
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13.1 PLL design example
The frequency synthesizer used in the design example shown in Figure 33 has the
following parameters:
Output frequency: 2 MHz to 3 MHz
Frequency steps: 100 kHz
Settling time: 1 ms
Overshoot: < 20 %
The open loop gain is:
H(s) G(s) = K p K f K o K n
where:
Kp = phase comparator gain
Kf = low-pass filter transfer gain
Ko = Kv/s VCO gain
Kn = 1⁄n divider ratio
The programmable counter ratio Kn can be found as follows:
f OUT
2 MHz
N min = ----------- = -------------------- = 20
f step
100 kHz
f OUT
3 MHz
N max = ----------- = --------------------- = 30
f step
100 kHz
The values of R1, R2 and C1; R2 = 10 k (adjustable) set the VCO.
The values can be determined using the information in Table 10 and Table 11.
With f0 = 2.5 MHz and fL = 500 kHz, the following values (VCC = 5.0 V) are given:
R1 = 10 k
R2 = 10 k
C1 = 500 pF
The VCO gain is:
2f L 2
1 MHz
6
K v = ------------------------------------------ = ----------------- 2 2 10 r s V
V CC – 0.9 – 0.9
3.2
The gain of the phase comparator is:
V CC
K p = ------------ = 0.4 V r
4
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The transfer gain of the filter is calculated as follows:
1 + 2 s
K f = ----------------------------------1 + 1 + 2 s
Where:
1 = R3 C2
2 = R4 C2
The characteristic equation is: 1 + H(s) G(s) = 0
It results in:
Kp Kv Kn
2 1 + Kp Kv Kn 2
S + ---------------------------------------------------- S + ------------------------------- = 0
1 + 2
1 + 2
The natural frequency n defined as:
n =
Kp Kv Kn
------------------------------ 1 + 2
1 + Kp Kv Kn 2
1
and the damping value () given as: = --------- --------------------------------------------------- 1 + 2
2 n
In Figure 34, the output frequency response to a step of input frequency is shown.
The overshoot and settling time percentages are now used to determine n.
Figure 34 shows that the damping ratio = 0.45 produces an overshoot of less than 20 %
and settle to within 5 % at nt = 5. The required settling time is 1 ms. It results in:
5
5
3
n = --- = ------------- = 5 10 r s
t
0.001
Rewriting the equation for natural frequency results in:
Kp Kv Kn
1 + 2 = ------------------------------2
n
The maximum overshoot occurs at Nmax:
6
0.4 2 10
- = 0.0011 s
1 + 2 = -----------------------------2
5000 30
When C2 = 470 nF, then:
1 + 2 2 n – 1
R4 = ------------------------------------------------------------- = 315
K p K v K n C2
1
R3 can be calculated: R3 = ------- – R4 = 2 k
C2
74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74HC4046A; 74HCT4046A
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Phase-locked loop with VCO
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The output frequency is proportional to the VCO control voltage. As a result, the PLL frequency
response can be observed with an oscilloscope by monitoring pin VCO_IN of the VCO. The average
frequency response, as calculated by the Laplace method, is found experimentally by smoothing this
voltage at pin VCO_IN using a simple RC filter. The filter has a long time constant when compared
with the phase detector sampling rate but short when compared with the PLL response time.
Fig 35. Frequency compared to the time response
74HC_HCT4046A
Product data sheet
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Phase-locked loop with VCO
14. Package outline
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74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
44 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
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74HC_HCT4046A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
45 of 50
74HC4046A; 74HCT4046A
NXP Semiconductors
Phase-locked loop with VCO
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74HC_HCT4046A
Product data sheet
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Rev. 3 — 8 June 2016
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Phase-locked loop with VCO
15. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductors
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
PLL
Phase-Locked Loop
VCO
Voltage Controlled Oscillator
16. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT4046A v.3
20160608
Product data sheet
-
74HC_HCT4046A_CNV v.2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
74HC_HCT4046A_CNV v.2 19971125
Product specification
-
74HC_HCT4046A v.1
74HC_HCT4046A v.1
Objective specification
-
-
74HC_HCT4046A
Product data sheet
19930901
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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Phase-locked loop with VCO
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT4046A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Product data sheet
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Phase-locked loop with VCO
19. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.2.1
8.2.2
8.2.3
9
10
11
11.1
11.2
11.3
12
12.1
12.2
12.3
13
13.1
14
15
16
17
17.1
17.2
17.3
17.4
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Phase comparators. . . . . . . . . . . . . . . . . . . . . . 5
Phase Comparator 1 (PC1) . . . . . . . . . . . . . . . 6
Phase Comparator 2 (PC2) . . . . . . . . . . . . . . . 8
Phase Comparator 3 (PC3) . . . . . . . . . . . . . . 10
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12
Recommended operating conditions. . . . . . . 12
Static characteristics. . . . . . . . . . . . . . . . . . . . 13
Static characteristics 74HC4046A . . . . . . . . . 13
Static characteristics 74HCT4046A . . . . . . . . 19
Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Dynamic characteristics . . . . . . . . . . . . . . . . . 24
Dynamic characteristics 74HC4046A . . . . . . . 24
Dynamic characteristics 74HCT4046A . . . . . . 27
Waveforms and graphs. . . . . . . . . . . . . . . . . . 29
Application information. . . . . . . . . . . . . . . . . . 36
PLL design example . . . . . . . . . . . . . . . . . . . . 41
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 44
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 47
Legal information. . . . . . . . . . . . . . . . . . . . . . . 48
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 48
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Contact information. . . . . . . . . . . . . . . . . . . . . 49
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 8 June 2016
Document identifier: 74HC_HCT4046A