BLF8G20LS-400PV;
BLF8G20LS-400PGV
Power LDMOS transistor
Rev. 1 — 25 June 2013
Product data sheet
1. Product profile
1.1 General description
400 W LDMOS power transistor with improved video bandwidth for base station
applications at frequencies from 1805 MHz to 1995 MHz.
Table 1.
Typical performance
Typical RF performance at Tcase = 25 C in a common source class-AB production test circuit, tested
on straight lead device.
Test signal
2-carrier W-CDMA
[1]
f
IDq
VDS
PL(AV)
Gp
D
ACPR5M
(MHz)
(mA)
(V)
(W)
(dB)
(%)
(dBc)
1805 to 1995
3400
28
95
19
28
33 [1]
Test signal: 3GPP test model 1; 64 DPCH; PAR = 7.5 dB at 0.01 % probability on CCDF;
carrier spacing = 5 MHz; f1 = 1807.5 MHz; f2 = 1812.5 MHz; f3 = 1872.5 MHz; f4 = 1877.5 MHz.
1.2 Features and benefits
Decoupling leads to enable improved Video BandWidth (VBW) (120 MHz typical)
High efficiency
Low Rth providing excellent thermal stability
Designed for broadband operation
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent pre-distortability
Internally matched for ease of use
Integrated ESD protection
Design optimized for gull-wing
Excellent ruggedness
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for base stations and multi carrier applications in the 1805 MHz to
1995 MHz frequency range
BLF8G20LS-400P(G)V
NXP Semiconductors
Power LDMOS transistor
2. Pinning information
Table 2.
Pinning
Pin
Description
Simplified outline
Graphic symbol
BLF8G20LS-400PV (SOT1242B)
1
drain1
2
drain2
3
gate1
4
gate2
[1]
5
source
6
decoupling1
7
decoupling2
8
n.c.
9
n.c.
DDD
BLF8G20LS-400PGV (SOT1242C)
1
drain1
2
drain2
3
gate1
4
gate2
5
source
6
decoupling1
7
decoupling2
8
n.c.
9
n.c.
[1]
[1]
DDD
Connected to flange.
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name Description
Version
BLF8G20LS-400PV
-
earless flanged ceramic package; 8 leads
SOT1242B
BLF8G20LS-400PGV -
earless flanged ceramic package; 8 leads
SOT1242C
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
Rev. 1 — 25 June 2013
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Power LDMOS transistor
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDS
Min
Max
Unit
drain-source voltage
-
65
V
VGS
gate-source voltage
0.5
+13
V
Tstg
storage temperature
65
+150
C
-
225
C
[1]
junction temperature
Tj
[1]
Conditions
Continuous use at maximum temperature will affect the reliability.
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-c)
thermal resistance from junction to case
Tcase = 80 C; PL = 80 W
0.23
K/W
6. Characteristics
Table 6.
DC characteristics
Tj = 25 C; per section unless otherwise specified.
Symbol Parameter
Conditions
Min Typ
V(BR)DSS drain-source breakdown voltage VGS = 0 V; ID = 3.0 mA
Max Unit
65
-
-
V
VGS(th)
gate-source threshold voltage
VDS = 10 V; ID = 300 mA
1.5
1.9
2.3
V
IDSS
drain leakage current
VGS = 0 V; VDS = 28 V
-
-
3.0
A
IDSX
drain cut-off current
VGS = VGS(th) + 3.75 V;
VDS = 10 V
51.5
-
A
IGSS
gate leakage current
VGS = 11 V; VDS = 0 V
-
-
300
nA
gfs
forward transconductance
VDS = 10 V; ID = 15 A
-
20.6
-
S
RDS(on)
drain-source on-state resistance VGS = VGS(th) + 3.75 V;
ID = 10.5 A
-
0.055 -
Table 7.
RF characteristics
Test signal: 2-carrier W-CDMA; PAR = 7.5 dB at 0.01 % probability on the CCDF; 3GPP test
model 1; 1-64 DPCH; f1 = 1807.5 MHz; f2 = 1812.5 MHz; f3 = 1872.5 MHz; f4 = 1877.5 MHz;
RF performance at VDS = 28 V; IDq = 3400 mA; Tcase = 25 C; unless otherwise specified; in a
class-AB production test circuit, tested on straight lead device.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Gp
power gain
PL(AV) = 95 W
17.8
19
dB
RLin
input return loss
PL(AV) = 95 W
-
12 6
dB
D
drain efficiency
PL(AV) = 95 W
24
28
%
ACPR5M
adjacent channel power ratio (5 MHz)
PL(AV) = 95 W
-
33 28
BLF8G20LS-400PV_LS-400PGV
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 — 25 June 2013
-
dBc
© NXP B.V. 2013. All rights reserved.
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Power LDMOS transistor
7. Test information
7.1 Ruggedness in class-AB operation
The BLF8G20LS-400PV and BLF8G20LS-400PGV are capable of withstanding a load
mismatch corresponding to VSWR = 10 : 1 through all phases under the following
conditions: VDS = 28 V; IDq = 3300 mA; 2-carrier W-CDMA signal; PL = 200 W;
fc = 1800 MHz; 5 MHz spacing, 46 % clipping.
7.2 Impedance information
Table 8.
Typical impedance for the top-half of the push-pull package
Measured load-pull data; IDq = 1800 mA; VDS = 28 V; Tcase = 25 C, water cooled.
f
ZS[1]
ZL[1]
(MHz)
()
()
BLF8G20LS-400PV (straight lead)
1800
4.1 j4.66
4.1 j4.5
1840
5.2 j3.6
4.4 j4.4
1880
4.6 j1.45
4.85 j4.25
1930
2.8 j0.3
4.5 j4.3
1960
2.1 j0.5
5.5 j3.5
1990
1.56 j0.6
5.5 j3.4
BLF8G20LS-400PGV (gull-wing)
1800
3.7 j7.6
4.2 j6.8
1840
4.34 j6.1
4.4 j6.7
1880
4.75 j5.2
4 j6.4
1930
3.17 j3.4
4.6 j6.5
1960
2 j3.05
5.8 j5.5
1990
2.5 j2.6
5.8 j5.7
[1]
ZS and ZL defined in Figure 1.
drain
ZL
gate
ZS
001aaf059
Fig 1.
Definition of transistor impedance
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
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Power LDMOS transistor
7.3 VBW in class-AB operation
The BLF8G20LS-400PV and BLF8G20LS-400PGV have a video bandwidth of 120 MHz
(typical) when measured in a class-AB test circuit operating in the 1800 MHz to 1880 MHz
frequency band for VDS = 28 V and IDq = 3.3 A, where the VBW is defined as the location
of the resonance in the base-band impedance measurement obtained using a
low-frequency probe.
The VBW measurement based on the 2-tone IMD test as a function of carrier spacing is
shown below.
DDD
,0'
G%F
,0'
,0'
,0'
FDUULHUVSDFLQJ0+]
(1) IMD low
(2) IMD high
Fig 2.
VBW capacity in a class-AB test circuit
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
Rev. 1 — 25 June 2013
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Power LDMOS transistor
7.4 Test circuit
PP
PP
&
& &
&
&
&
&
&
5
&
&
&
PP
5
&
5
&
LQSXW
&
5
RXWSXW
&
5
&
&
&
&
&
&
&
&
DDD
Printed-Circuit Board (PCB): Rogers 4350B; r = 3.66; thickness = 0.762 mm;
thickness copper plating = 35 m.
See Table 9 for a list of components.
Fig 3.
Component layout
Table 9.
List of components
See Figure 3 for component layout.
Component
Description
Value
Remarks
C1, C5, C16, C20
multilayer ceramic chip capacitor
10 F, 50 V
Murata, SMD 2220
C2, C6, C15, C19
multilayer ceramic chip capacitor
4.7 F, 50 V
Murata
C3, C7, C14, C18
multilayer ceramic chip capacitor
1 nF
ATC100B
C4, C8, C9, C10, C13,
C17, C21
multilayer ceramic chip capacitor
24 pF
ATC100B
ATC100B
C11, C12
multilayer ceramic chip capacitor
100 pF
C22, C23
electrolytic capacitor
2200 F, 63 V
R1, R2
resistor
10
SMD 1206
R3, R5
resistor
5.1
SMD 1206
R4
resistor
33
SMD 1206
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
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Power LDMOS transistor
7.5 Graphical data
7.5.1 CW
DDD
*S
G%
DDD
Ș'
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(1) f = 1805 MHz
(2) f = 1840 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
(3) f = 1880 MHz
Fig 4.
Power gain as a function of average output
power; typical values
Fig 5.
Drain efficiency as a function of average
output power; typical values
DDD
5/LQ
G%
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
Fig 6.
Input return loss as a function of average output power; typical values
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
Rev. 1 — 25 June 2013
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Power LDMOS transistor
7.5.2 Pulsed CW
DDD
DDD
*S
G%
Ș'
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(1) f = 1805 MHz
(2) f = 1840 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
(3) f = 1880 MHz
Fig 7.
Power gain as a function of average output
power; typical values
Fig 8.
Drain efficiency as a function of average
output power; typical values
DDD
5/LQ
G%
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
Fig 9.
Input return loss as a function of average output power; typical values
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
Rev. 1 — 25 June 2013
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Power LDMOS transistor
7.5.3 IS-95
DDD
DDD
*S
G%
Ș'
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(1) f = 1805 MHz
(2) f = 1840 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
(3) f = 1880 MHz
Fig 10. Power gain as a function of average output
power; typical values
DDD
Fig 11. Drain efficiency as a function of average
output power; typical values
DDD
3/0
G%
3$5
G%
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(1) f = 1805 MHz
(2) f = 1840 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
(3) f = 1880 MHz
Fig 12. Peak-to-average power ratio as a function of
average output power; typical values
Fig 13. Peak output power as a function of average
output power; typical values
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
Rev. 1 — 25 June 2013
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Power LDMOS transistor
DDD
5/LQ
G%
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
Fig 14. Input return loss as a function of average output power; typical values
7.5.4 1-Carrier W-CDMA
DDD
*S
G%
DDD
Ș'
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(1) f = 1805 MHz
(2) f = 1840 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
(3) f = 1880 MHz
Fig 15. Power gain as a function of average output
power; typical values
Fig 16. Drain efficiency as a function of average
output power; typical values
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
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DDD
DDD
3/0
G%
3$5
G%
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(1) f = 1805 MHz
(2) f = 1840 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
(3) f = 1880 MHz
Fig 17. Peak-to-average power ratio as a function of
average output power; typical values
Fig 18. Peak output power as a function of average
output power; typical values
DDD
5/LQ
G%
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
Fig 19. Input return loss as a function of average output power; typical values
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
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DDD
$&350
G%F
DDD
$&350
$&35
G%F
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(1) f = 1805 MHz
(2) f = 1840 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
(3) f = 1880 MHz
Fig 20. Adjacent channel power ratio (5 MHz) as a
function of average output power; typical
values
Fig 21. Adjacent channel power ratio (10 MHz) as a
function of average output power; typical
values
7.5.5 2-Carrier W-CDMA
DDD
*S
G%
DDD
Ș'
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(1) f = 1805 MHz
(2) f = 1840 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
(3) f = 1880 MHz
Fig 22. Power gain as a function of average output
power; typical values
Fig 23. Drain efficiency as a function of average
output power; typical values
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
Rev. 1 — 25 June 2013
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Power LDMOS transistor
DDD
DDD
3/0
G%
3$5
G%
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(1) f = 1805 MHz
(2) f = 1840 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
(3) f = 1880 MHz
Fig 24. Peak-to-average power ratio as a function of
average output power; typical values
Fig 25. Peak output power as a function of average
output power; typical values
DDD
5/LQ
G%
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
Fig 26. Input return loss as a function of average output power; typical values
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
Rev. 1 — 25 June 2013
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Power LDMOS transistor
DDD
$&350
G%F
DDD
$&350
G%F
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
3/$9G%P
VDS = 28 V; IDq = 3400 mA.
(1) f = 1805 MHz
(1) f = 1805 MHz
(2) f = 1840 MHz
(2) f = 1840 MHz
(3) f = 1880 MHz
(3) f = 1880 MHz
Fig 27. Adjacent channel power ratio (5 MHz) as a
function of average output power; typical
values
Fig 28. Adjacent channel power ratio (10 MHz) as a
function of average output power; typical
values
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
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8. Package outline
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Fig 29. Package outline SOT1242B
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
Rev. 1 — 25 June 2013
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BLF8G20LS-400P(G)V
NXP Semiconductors
Power LDMOS transistor
(DUOHVVIODQJHGFHUDPLFSDFNDJHOHDGV
627&
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Fig 30. Package outline SOT1242C
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
Rev. 1 — 25 June 2013
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9. Handling information
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
10. Abbreviations
Table 10.
Abbreviations
Acronym
Description
3GPP
3rd Generation Partnership Project
CCDF
Complementary Cumulative Distribution Function
CW
Continuous Wave
DPCH
Dedicated Physical Channel
ESD
ElectroStatic Discharge
IMD
InterModulation Distortion
IS-95
Interim Standard 95
LDMOS
Laterally Diffused Metal Oxide Semiconductor
PAR
Peak-to-Average Ratio
SMD
Surface Mounted Device
VSWR
Voltage Standing Wave Ratio
W-CDMA
Wideband Code Division Multiple Access
11. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BLF8G20LS-400PV_LS-400PGV v.2
20130625
Product data sheet
-
BLF8G20LS-400PV
_LS-400PGV v.1
Modifications
BLF8G20LS-400PV_LS-400PGV v.1
•
The status of this document has been changed to Product data sheet
20130606
Preliminary data sheet
BLF8G20LS-400PV_LS-400PGV
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Product data sheet
Rev. 1 — 25 June 2013
-
-
© NXP B.V. 2013. All rights reserved.
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12. Legal information
12.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
12.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
BLF8G20LS-400PV_LS-400PGV
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 — 25 June 2013
© NXP B.V. 2013. All rights reserved.
18 of 20
BLF8G20LS-400P(G)V
NXP Semiconductors
Power LDMOS transistor
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
BLF8G20LS-400PV_LS-400PGV
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 — 25 June 2013
© NXP B.V. 2013. All rights reserved.
19 of 20
NXP Semiconductors
BLF8G20LS-400P(G)V
Power LDMOS transistor
14. Contents
1
1.1
1.2
1.3
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
8
9
10
11
12
12.1
12.2
12.3
12.4
13
14
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . 3
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Test information . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ruggedness in class-AB operation . . . . . . . . . 4
Impedance information . . . . . . . . . . . . . . . . . . . 4
VBW in class-AB operation . . . . . . . . . . . . . . . 5
Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Graphical data . . . . . . . . . . . . . . . . . . . . . . . . . 7
CW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pulsed CW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
IS-95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . 10
2-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Handling information. . . . . . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 June 2013
Document identifier: BLF8G20LS-400PV_LS-400PGV