PHILIPS UAA3580HN

INTEGRATED CIRCUITS
DATA SHEET
UAA3580
Wideband code division multiple
access frequency division duplex
zero IF receiver
Objective specification
Supersedes data of 2002 Oct 16
2002 Oct 30
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
CONTENTS
UAA3580
17
PACKAGE OUTLINE
18
SOLDERING
18.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
6
BLOCK DIAGRAM
7
PINNING INFORMATION
19
DATA SHEET STATUS
7.1
7.2
Pinning
Pin description
20
DEFINITIONS
8
FUNCTIONAL DESCRIPTION
21
DISCLAIMERS
8.1
8.2
8.3
8.4
8.5
8.6
8.7
RF receiver front-end and RF VCO
Channel filter and AGC
RF VCO
RF LO section
RF fractional-N synthesizer PLL
Clock PLL
Control
9
OPERATING MODES
9.1
9.2
9.3
9.4
Basic operating mode
AGC gain look-up table
RF PLL synthesizer
Clock PLL synthesizer
10
PROGRAMMING
10.1
10.2
10.3
Serial programming bus
Data format
Register contents
11
LIMITING VALUES
12
THERMAL CHARACTERISTICS
13
DC CHARACTERISTICS
14
AC CHARACTERISTICS
15
SERIAL BUS TIMING CHARACTERISTICS
16
APPLICATION INFORMATION
2002 Oct 30
18.2
18.3
18.4
18.5
2
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
1
FEATURES
3
• Low noise wide dynamic range for zero IF receivers
GENERAL DESCRIPTION
The UAA3580 is a BiCMOS integrated circuit receiver
intended for the Third Generation Partnership Project
(3GPP) specification for the Universal Mobile
Telecommunication System (UMTS).
• 79 dB gain control range; in steps of 1 dB
• Channel filters
• 96 dB voltage gain
The circuit is specially designed for the Frequency Division
Duplex (FDD) mode of the Wide Code Division Multiple
Access (WCDMA) that operates in the 2110 to 2170 MHz
band.
• Fully integrated fractional-N synthesizer with AFC
control capability
• Fully integrated RF VCO with integrated supply voltage
regulator
The UAA3580 contains the whole analog receive chain
from Radio Frequency (RF) Low Noise Amplifier (LNA) to
baseband IQ outputs including a channel filter, a complete
RF Phase-Locked Loop (PLL) with a fully integrated
Voltage Controlled Oscillator (VCO), and a clock PLL that
generates a programmable UMTS system clock from an
external 26 MHz reference signal.
• Fully differential design to minimize crosstalk
• Supply voltage from 2.4 to 3.3 V
• 3-wire serial interface bus
• HVQFN24 package.
2
UAA3580
APPLICATIONS
• WCDM-FDD receiver for GSM hand-portable equipment
• Dual mode GSM/GPRS/EDGE/UMTS handset.
4
QUICK REFERENCE DATA
SYMBOL
PARAMETER
TYP.
MAX.
UNIT
2.6
−
3.3
digital supply voltage
1.6
−
2.8
V
ambient temperature
−30
−
+70
°C
VCCA
analog supply voltage
VDDD
Tamb
5
MIN.
V
ORDERING INFORMATION
TYPE
NUMBER
UAA3580HN
2002 Oct 30
PACKAGE
VERSION
NAME
HVQFN24
DESCRIPTION
plastic, heatsink very thin quad flat package; no leads
24 terminals; body 4 × 4 × 0.90 mm
3
SOT616-1
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
6
UAA3580
BLOCK DIAGRAM
handbook, full pagewidth
REFIN
VCCA(SYN)
CPCLKO
VCCA(CP)
RFCPO
19
UAA3580HN
RF
SIGMA DELTA
FRACTIONAL-N
20
RF
SIGMA DELTA
FRACTIONAL-N
DIVIDE-BY-2
21
22
VCO
23
VCOGND
VCCA(RF)
RFGND
RFIP
RFIN
IFGND
RXCEN
VCCA(IF)
24
17
16
REXT
UMTSCLKO
VDDD
RF VCO
15
SERIAL INTERFACE
CAPVCOREG
18
VCO
REGULATOR
DIVIDE-BY-2
14
13
EN
CLK
DATA
1
2
MIXER
3
12
11
QN
QP
4
5
6
LNA
MIXER
10
9
7
IN
IP
8
FCA236
Fig.1 Block diagram.
2002 Oct 30
4
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
12 QN
11 QP
IP
9
10 IN
VCCA(IF)
handbook, full pagewidth
8
Pinning
RXCEN
7.1
PINNING INFORMATION
7
7
UAA3580
13 DATA
IFGND 6
14 CLK
RFIN 5
15 EN
RFIP 4
UAA3580HN
RFGND 3
16 VDDD
VCCA(RF) 2
17 UMTSCLKO
REFIN 19
VCCA(SYN) 20
CPCLKO 21
VCCA(CP) 22
RFCPO 23
18 REXT
CAPVCOREG 24
VCOGND 1
Fig.2 Pin configuration.
2002 Oct 30
5
FCA237
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
7.2
UAA3580
Pin description
Table 1
HVQFN24 package
SYMBOL
PIN
DESCRIPTION
VCOGND
1
RF VCO ground
VCCA(RF)
2
analog supply voltage for the RF receiver
RFGND
3
RF receiver ground
RFIP
4
RF positive input
RFIN
5
RF negative input
IFGND
6
IF section ground
RXCEN
7
receiver chip enable input
VCCA(IF)
8
analog supply voltage for the IF section
IP
9
differential receive baseband positive in-phase output
IN
10
differential receive baseband negative in-phase output
QP
11
differential receive baseband positive in-quadrature output
QN
12
differential receive baseband negative in-quadrature output
DATA
13
serial bus data input
CLK
14
serial bus clock input
EN
15
serial bus enable input
VDDD
16
digital supply voltage
UMTSCLKO
17
UMTS system clock output
REXT
18
external charge pump biasing resistor connection
REFIN
19
reference clock input
VCCA(SYN)
20
analog supply voltage for the synthesizer
CPCLKO
21
charge pump clock output
VCCA(CP)
22
analog supply voltage for the charge pump section
RFCPO
23
RF charge pump output
CAPVCOREG
24
die pad
2002 Oct 30
decoupling capacitor for the VCO regulator
ground
6
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
8
8.5
FUNCTIONAL DESCRIPTION
The PLL is based on Sigma-Delta (Σ∆) fractional-N
synthesis that enables the required channel frequency,
including Automatic Frequency Control (AFC) from a free
running external 26 MHz GSM reference frequency, to be
obtained. Very low close in-phase noise is achieved which
allows a wider PLL loop bandwidth and a shorter settling
time. The programmable main dividers are controlled by a
second-order (Σ∆) modulus controller. They divide the RF
VCO signals down to frequencies of 26 MHz (in
programmable 12 Hz steps). Their phase is then
compared in a digital Phase/Frequency Detector (PFD) to
the 26 MHz reference clock signal. The phase error
information is fed back to the RF VCO via the charge pump
circuit that ‘sources’ into or ‘sinks’ current from the loop
filter capacitor, thus changing the VCO frequency so that
the loop is finally brought into phase-lock.
RF receiver front-end and RF VCO
The front-end receiver converts the aerial RF signal from
WCMDA (2.11 to 2.17 GHz) band down to a Zero
Intermediate Frequency (ZIF). The first stage is a
differential low noise amplifier matched to 50 Ω using an
external balun. The LNA is followed by an IQ down-mixer
which consists of two mixers in parallel but driven by
quadrature out-of-phase LO signals. The In phase (I) and
Quadrature phase (Q) ZIF signals are then low-pass
filtered, to provide protection from high frequency offset
interference, and fed into the channel filter.
8.2
Channel filter and AGC
The front-end zero IF I and Q outputs are applied to the
integrated low-pass channel filter with a provision for
4 × 8 dB gain steps in front of the filter. The filter is a
self-calibrated fifth-order low-pass filter with a cut-off
frequency around 2.4 MHz. Once filtered the zero IF
I and Q outputs are further amplified with provision for
47 × 1 dB steps and DC offset compensation. The zero IF
output buffer provides close rail-to-rail output signal.
8.3
The RF synthesizer division range enables an external
reference frequency of 13 to 26 MHz to be used.
8.6
RF VCO
8.7
Control
The control of the chip is done via the 3-wire serial bus and
pin RXCEN. At power-up the clock PLL section is
automatically enabled, the other sections are enabled
when the RXCEN signal is set HIGH (also via the 3-wire
bus). The power-up signal is detected on pin VDDD when
the voltage rises. The VDDD pin, if the supply voltage is
maintained, enables the programming parameters to be
retained in memory.
RF LO section
The RF LO section covering the 4.22 to 4.34 GHz band is
driven by the internal RF VCO module. It includes the LO
buffering for the RF PLL and a divide-by-two circuit to
generate the quadrature LO signals to drive the RX IQ
down-mixer.
2002 Oct 30
Clock PLL
The clock PLL is based on SD fractional-N synthesis that
allows the UMTS system clock, including AFC from a
non-corrected external 26 MHz GSM reference frequency,
to be obtained. The PLL comprises a fully integrated RC
VCO. The PLL output is a low harmonic content waveform,
the frequency of which can be programmed to
15.36, 30.72 or 61.44 MHz. The default value is
30.72 MHz.
The RF VCO is fully integrated and self-calibrated on
manufacturing tolerances. It consists of 16 different
frequency ranges that are selected internally, depending
on the frequency programmation. It covers the necessary
bandwidth of 4.22 to 4.34 GHz and is tuned via the RF
charge pump and external loop filter. An internal supply
voltage regulator using the pin CAPVCOREG as external
decoupling capacitor supplies the RF VCO and minimizes
parasitic coupling and pushing. The regulator and the RF
VCO are turned on by the RXCEN signal.
8.4
RF fractional-N synthesizer PLL
A high performance RF fractional-N synthesizer PLL is
included on-chip which enables the frequency of the RF
VCO to be synthesized. The frequency is set via the 3-wire
serial programming bus.
The receiver consists of an RF receiver front-end, an
RF VCO, a channel filter, Automatic Gain Control (AGC),
a RF fractional-N synthesizer PLL, a clock PLL, a
Power-up reset circuit and a 3-wire serial programming
bus.
8.1
UAA3580
7
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
9
OPERATING MODES
9.1
UAA3580
Table 2
Basic operating modes
MODE
The circuit can be powered up into different operating
modes, depending on the control bits RXON and SYNON,
via the 3-wire bus. This defines three main modes called
IDLE, SYN and RX mode.
The voltage level applied to pin RXCEN must be set HIGH
to enable the device. The VCO and the PLL sections are
enabled in SYN mode. In the RX mode every section is
enabled (receive part, VCO and PLL sections).
Table 3
Selection of operating mode
SYNON
RXON
IDLE
0
0
SYN
1
0
RX
1
1
9.2
AGC gain look-up table
The AGC gain is set via the AGC[8:0] bits; see Table 3.
AGC gain look-up table
AGC8
AGC7
AGC6
AGC5
AGC4
AGC3
AGC2
AGC1
AGC0
ATTENUATION FROM
MAXIMUM GAIN (dB)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
1
1
0
1
14
15
16
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
0
0
1
17
18
1
0
1
1
1
0
1
0
0
19
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
20
21
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
1
1
0
1
22
23
24
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
25
26
27
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
28
29
2002 Oct 30
8
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
AGC8
AGC7
AGC6
AGC5
AGC4
AGC3
AGC2
AGC1
AGC0
ATTENUATION FROM
MAXIMUM GAIN (dB)
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
30
31
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
32
33
34
35
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
0
1
36
37
38
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
1
1
0
1
1
0
1
0
55
56
57
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
58
59
60
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
61
62
63
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
0
64
65
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
66
67
68
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
69
70
2002 Oct 30
9
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
AGC8
AGC7
AGC6
AGC5
AGC4
AGC3
AGC2
AGC1
AGC0
ATTENUATION FROM
MAXIMUM GAIN (dB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
1
1
0
1
0
71
72
73
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
1
74
75
76
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
77
78
79
The AGC[8:0] code required to program the AGC attenuation (AGCatt) can be calculated from the following formulas:
AGC[8:0] = (511 − AGCatt)B if 0 < AGCatt < 11
AGC[8:0] = (391 − AGCatt)B if 12 < AGCatt < 19
AGC[8:0] = (271 − AGCatt)B if 20 < AGCatt < 27
AGC[8:0] = (151 − AGCatt)B if 28 < AGCatt < 35
AGC[8:0] = (95 − AGCatt)B if 36 < AGCatt < 43
AGC[8:0] = (151 − AGCatt)B if 44 < AGCatt < 51
AGC[8:0] = (95 − AGCatt)B if 52 < AGCatt < 59
AGC[8:0] = (135 − AGCatt)B if 60 < AGCatt < 67
AGC[8:0] = (79 − AGCatt)B if 68 < AGCatt < 79
Where (X)B is the binary code of the integer X.
2002 Oct 30
10
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
9.3
Table 4
RF PLL synthesizer
The RF fractional-N synthesizer is set via the 3-wire bus
with the FRAC and CH chains. CH sets the integer divider
ratio and FRAC the fractional divider ratio. They both
provide the LO frequency in accordance with the following
equation:
N RX
f RFLO = f ref ×  ---------+ K frac(RX)
 2
Where K frac(RX)
1
1
= ------- ×  K + ---
22  RX 2
2
1
0
CLKPLL synthesizer
enabled (default)
0
1
0
CLKPLL synthesizer
disabled; note 1
1
0
0
CLKPLL synthesizer
disabled; note 2
X(4)
X(4)
1
CLKPLL synthesizer
disabled; note 3
2. Power-down achieved via the 3-wire bus, reset by
RXCEN.
3. Power-down achieved via the 3-wire bus, no effect by
RXCEN in this mode. This mode will be reset if VDDD
is not maintained.
4. X = don’t care.
Clock PLL synthesizer
9.4.3
AFC MODE
CLOCK PLL OUTPUT DIVIDER
The clock PLL output divider ratio is set in accordance with
Table 5.
Table 5
AFC represents the integer value of AFC[11:0] and fref is
the external reference frequency applied to pin REFIN.
CLOCK PLL MODES
Clock mode; note 1
CLKoff
CLK1
CLK0
1
X
X
UMTSCLKO output
disabled
0
0
0
clock divider ratio set to
default
0
0
1
clock divider ratio set to 2
0
1
0
clock divider ratio set to 4
0
1
1
clock divider ratio set to 8
Note
The clock PLL synthesizer is controlled by bits CLKon and
CLKoff. At power-up the clock PLL synthesizer is
automatically on when pin RXCEN is set HIGH. The
control, done with CLKon, will be reset at the rising edge
of RXCEN. For application which do not require the UMTS
clock system, the clock PLL can be powered-down with bit
CLKoff set to logic 1.
2002 Oct 30
1
1. Hard power-down of the clock PLL done with RXCEN.
The clock PLL is based on the SD fractional-N synthesizer
that allows to derive the UMTS system clock including AFC
from a non-corrected external 26 MHz only GMS
reference. The clock PLL frequency with the AFC
correction word is given by the following equation:
9 + K AFC
f CLKPLL = f ref ×  -----------------------


2
231 AFC
Where K AFC = ---------- + -----------512 2 21
9.4.2
DESCRIPTION
Notes
Example: to obtain a fRFLO frequency of 2.14 GHz with an
error less than ∆fPLL NRX must be set to 164 and Kfrac(RX)
to 1290555 if the reference frequency is 26 MHz. It should
be noted that some particular frequencies can be obtained
in two ways; NRX = x and Kfrac(RX) = 0.25 provides the
same frequency as NRX = x − 1 and Kfrac(RX) = 0.75
9.4.1
Clock mode
RXCEN CLKon CLKoff
Where KRX is the integer value of FRAC[21:0], NRX is the
integer value of CH[8:0] and fref is the external frequency
reference applied to pin REFIN.
9.4
UAA3580
1. X = don’t care.
11
DESCRIPTION
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
10 PROGRAMMING
10.2
10.1
Data is entered with the most significant bit first. The
leading bits make up the data field, while the trailing four
bits are an address field. The address bits are decoded on
the rising edge of EN. This produces an internal load pulse
to store the data in the address latch.
Serial programming bus
A simple 3-wire unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, CLK and EN.
The data sent to the device is loaded in bursts framed
by EN. Programming clock edges are ignored until EN
goes active LOW. The programmed information is loaded
into the addressed latch when EN goes HIGH (inactive).
This is allowed when CLK is in either state without causing
any consequences to the data register. Only the last
21 bits serially clocked into the device are retained within
the programming register. Additional leading bits are
ignored, and no check is made on the number of clock
pulses.
Data format
To ensure that data is correctly loaded on first power-up,
EN should be held LOW and only taken HIGH after having
programmed an appropriate register. To avoid erroneous
divider ratios, the pulse is inhibited during the period when
data is read by the frequency dividers. This condition is
guaranteed by respecting a minimum EN pulse width after
data transfer.
The fully static CMOS design uses virtually no current
when the bus is inactive. It can always capture new
programming data even during Power-down of the
synthesizer.
10.3
Register contents
Table 6
Register bit allocation
CONTROL BITS
20
19
18
17
16
15
14
13
12
11
10
ADDRESS
9
8
7
6
5
4
3
2
1
0
for test purposes only; all bits must be set to zero for normal operation; this is a forbidden address
0
0
0
0
for test purposes only; all bits must be set to zero for normal operation; this is a forbidden address
0
0
0
1
FRAC[15:0]
CH[8:0]
0
0
0
0
0
Table 7
FR[21:16]
0
AGC[8:0]
1
AFC[11:0]
CKO[1:0]
SYNON 0
1
0
0
1
SYNON 0
1
0
1
1
RXON
0
1
1
0
CLKoff
CLKon
0
1
1
1
Description of symbols used in Table 6
SYMBOL
BITS
DESCRIPTION
SYNON
1
3-wire bus
RXON
1
3-wire bus
AGC
9
automatic gain control
CH
6
integer division ratio for the RF PLL
FRAC
22
fractional division ratio for the RF PLL
AFC
12
automatic frequency control for the clock PLL
CLKoff
1
clock PLL disabled
CKO
2
integer division ratio for the clock PLL
2002 Oct 30
12
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
Table 8
UAA3580
Register preset condition
CONTROL
ADDRESS
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
1
1
0
0
0
0
0
0
1
1
1
11 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
−0.3
−
+2.8
V
VCCA
analog supply voltage
−0.3
−
+3.3
V
Ptot
total power dissipation
−
−
300
mW
Tamb
ambient temperature
−30
−
+80
°C
Tstg
storage temperature
−40
−
+150
°C
12 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
2002 Oct 30
PARAMETER
thermal resistance from
junction to ambient
CONDITIONS
VALUE
UNIT
in free air; on a 4 layer PCB and
with soldered exposed die pad
36
K/W
13
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
13 DC CHARACTERISTICS
VCCA = 2.6 V; VCCA(CP) = 2.6 V;Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCCA
analog supply voltage
VDDD
digital supply voltage
ICCA(tot)
total analog supply current
on pins VCCA(RF), VCCA(IF),
VCCA(CP) and VCCA(SYN)
2.6
2.8
3.3
V
1.6
1.8
2.8
V
receive mode; note 1
−
52
63
mA
receive mode; note 2
−
45
54
mA
synthesizer mode; note 3
−
25
30
mA
standby mode; note 4
−
12
15
mA
sleep mode; note 5
−
10
50
µA
ICCA(RF)
analog supply current for the RF
VCO section
−
19
−
mA
ICCA(IF)
analog supply current for the RX
section
−
16
−
mA
ICCA(SYN)
analog supply current for the
synthesizer
−
15
−
mA
ICCA(CP)
analog supply current for the
charge pump
−
0.9
−
mA
IDDD
digital supply current
−
1.1
−
mA
1.15
1.25
1.35
V
−
2
−
V
−
0.8
−
V
−
360
−
mV
Baseband IQ section; pins IN, IP, QP and QN
VO(IQ)(CM)
IQ common mode output voltage
0.5(VIN + VIP) or
0.5(VQP + VQN); note 6
RF VCO section; pin CAPVCOREG
VO(CAPVCOREG) output voltage
CLKPLL section; pin UMTSCLKO
VO(UMTSCLKO)
output voltage
Reference voltage; pin REXT
VREXT
reference voltage for the charge
pump
Rext = 1.8 kΩ
Control section; pins DATA, CLK, EN and RXON
VIH
HIGH-level input voltage
0.9
−
−
V
VIL
LOW-level input voltage
−
−
0.3
V
Notes
1. Receive mode: All circuits are active.
2. Receive mode: All circuits are active with the clock PLL off (CLKoff = 1).
3. Synthesizer mode: RF PLL and clock PLL are active.
4. Standby mode: Clock PLL is active.
5. Sleep mode: RXCEN set LOW, DATA, CLK and EN are in high-impedance.
6. Receive mode: DC voltage supplied from the IC.
2002 Oct 30
14
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
14 AC CHARACTERISTICS
VCCA = 2.6 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RF receiver inputs; pins RFIN and RFIP
fi(RF)
RF input frequency
2.11
−
2.17
GHz
Ri
input resistance
−
170
−
Ω
Ci
input capacitance
−
1
−
pF
s11
input power matching
with external balun
−
−10
−
dB
F
noise figure
in receive mode with
maximum gain
−
3.2
4
dB
CP1
1 dB compression point
in receive mode with
maximum gain
−23
−20
−
dBm
IP3
input referred 3rd-order
intercept point
in receive mode with
maximum gain;
interference 20 MHz
away from channel
bandwidth
−18
−15
−
dBm
IP2
input referred 2nd-order
intercept point
in receive mode with
37
maximum gain;
interferers 190 MHz away
from channel bandwidth
42
−
dBm
ϕn
phase noise
at 15 MHz offset
−
−
−135
dBc/Hz
Baseband IQ section; pins IP, IN, QP and QN
Gv(max)
maximum voltage gain
92
96
100
dB
Gv(min)
minimum voltage gain
12
17
22
dB
AGCtot
total AGC range
−
79
−
dB
Gstep(AGC)
AGC gain step
−
1
−
dB
AGCtot(lin)
total AGC linearity
−0.5
−
+0.5
dB
∆Gv(IQ)
voltage gain mismatch
between the I and Q paths
−
−
0.5
dB
∆Φ
quadrature phase error
between the I and Q paths
peak error
−
−
5
deg
Vo(max)
maximum output voltage per
pin
RL(diff) = 10 kΩ;
THD < 3%
0.75
−
−
V
Io(max)
maximum output current per
pin
Vo(p-p) = 1.75 V at 1 MHz; 650
RL(diff) = 10 kΩ;
CL(diff) = 20 pF
−
−
µA
Voffset(diff)
differential output offset
voltage
−20
−
+20
mV
HP−3dB
−3 dB high-pass corner
frequency
2nd-order high-pass
frequency
10
15
20
kHz
LP−3dB
−3 dB low-pass corner
frequency
5th-order low-pass
frequency
2.25
2.4
2.55
MHz
∆d(g)
group delay variation
100 kHz < fo < 2 MHz
−
260
−
ns
2002 Oct 30
15
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
SYMBOL
αLPF
PARAMETER
LPF attenuation
UAA3580
CONDITIONS
fi = 5 MHz
MIN.
39
TYP.
MAX.
UNIT
42
−
dB
fi = 10 MHz
72
75
−
dB
fi = 15 to 60 MHz
91
94
−
dB
RF synthesizer; pin RFCPO
fRFLO
synthesizer frequency
2.11
−
2.17
GHz
fcomp(RF)
RF comparison frequency
−
26
−
MHz
∆fPLL
frequency resolution
fcomp = 13 to 26 MHz
0.05
−
−
ppm
fcomp = 26 MHz
−
−
6.2
Hz
Φn
close-in-phase noise
at 2 kHz offset
−
−85
−80
dBc/Hz
Isink
sink current
Rext = 1.8 kΩ; THD = 1%
170
200
230
µA
Isource
source current
Rext = 1.8 kΩ; THD = 1%
170
200
230
µA
Vo(CP)
charge pump output voltage
charge pump current
within specified range
0.4
−
VCCA − 0.4
V
KΦ
PFD gain
Rext = 1.8 kΩ; THD = 1%
27
32
37
µA/rad
Ileak(CP)
charge pump leakage current over full charge pump
in off state
voltage range
−1
−
+1
µA
N RX
1
1
Fractional-N synthesizer; f RFLO = f ref ×  ---------+ K frac(RX) where K frac(RX) = ------- ×  K + ---
22  RX 2
 2
2
N
integer divider ratio
130
−
507
Kfrac
fractional divider ratio
0.25
−
0.75
−
4.34
Integrated RF VCO; pin RFCPO
fRF
RF frequency
VRFCPO = 0 to 3.3 V
4.22
GHz
GVCO
VCO gain
VRFCPO = 1.3 V
50
70
90
MHz/V
Vtune
tuning voltage
0.4
−
VCCA − 0.4
V
∆fVCC
pushing
−
−
tbf
MHz/V
tcal(VCO)
VCO calibration time
after RXON = LO ≥ HI
−
−
35
µs
VCPCLKO = 0 to 3.3 V
-
122.88
-
MHz
−
13
−
MHz
fref = 26 MHz
0.477
−
−
ppm
−
±30
−
ppm
CLKPLL synthesizer; pin CPCLKO
fCLKPLL
synthesizer frequency
fcomp
comparison frequency
∆fPLL
frequency resolution
AFCcor
AFC correction range
Isink
sink current
Rext = 1.8 kΩ; THD = 1%
170
200
230
µA
Isource
source current
Rext = 1.8 kΩ; THD = 1%
170
200
230
µA
Vo(CP)
charge pump output voltage
charge pump current
within specified range
0.4
−
VCCA − 0.4
V
KΦ
PFD gain
Rext = 1.8 kΩ; THD = 1%
27
32
37
µA/rad
Ileak(CP)
charge pump leakage current over full charge pump
in off state
voltage range
−1
−
+1
µA
2002 Oct 30
16
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
SYMBOL
PARAMETER
UAA3580
CONDITIONS
MIN.
TYP.
MAX.
UNIT
N + K AFC
231 AFC
Fractional-N synthesizer; f CLKPLL = f ref ×  ------------------------ where K AFC = ---------- + -----------

2
512 2 21
N
integer divider ratio
−
9
−
KAFC
fractional divider ratio
0.4512
−
0.4532
Integrated CLKPLL VCO; pin CPCLKO
fVCO
CLKPLL frequency
VCPCLKO = 0 to 3.3 V
100
−
140
MHz
GVCO
VCO gain
VCPCLKO = 1.3 V
12
15
23
MHz/V
Vtune
tuning voltage
0.4
−
VCCA − 0.4
V
MHz
Output CLKPLL buffer; pin UMTSCLKO
fUMTSCLKO
frequency range
15.36
30.72
61.44
N
divider ratio
2
4
8
Φn
close-in-phase noise
at 2 kHz offset for
30.72 MHz
−
−
−90
dBc/Hz
phase noise
at 3.84 MHz offset for
30.72 MHz
−
−
−110
dBc/Hz
output voltage (peak-to-peak
value)
RL = 10 kΩ
1
−
−
V
13
−
26
MHz
Vo(p-p)
Low noise crystal amplifier; pin REFIN
fREF
reference frequency
Vi(REF)(rms)
input voltage (RMS value)
50
−
400
mV
Ri(REF)
input resistance
fREF = 26 MHz
−
tbf
−
kΩ
Ci(REF)
input capacitance
fREF = 26 MHz
−
tbf
−
pF
2002 Oct 30
17
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
15 SERIAL BUS TIMING CHARACTERISTICS
VCCA = 2.6 V; VCCA(CP) = 2.6 V; VDDD = 1.6 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial clock; pin CLK
ti(r)
input rise time
−
−
20
ti(f)
input fall time
−
−
20
ns
Tcyc
clock period
67
−
−
ns
td(START)
delay to rising clock edge
200
−
−
ns
td(END)
delay from last falling clock edge
100
−
−
ns
tW
minimum inactive pulse width
400
−
−
ns
tsu;EN
enable set-up time to next clock
200
−
−
ns
ns
Enable; pin EN
Register serial input data; pin DATA
tsu;DATA
input data to clock set-up time
25
−
−
ns
th;DATA
input data to clock hold time
25
−
−
ns
handbook, full pagewidth
tsu;DAT
th;DAT
ti(f)
Tcyc
ti(r)
td(END)
tsu;EN
CLK
DATA
MSB
LSB
ADDRESS
EN
tW
td(START)
MGU575
Fig.3 Serial bus timing diagram.
2002 Oct 30
18
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ceramic duplexer
8
isolator
7
6
5
9
4
10
LC MATCH
3
UAA3592
11
VDDD
CAPVCOREG
VCCA(SYN)
VCOTUNE
VCCA(CP)
CPGND
8
7
6
14
5
4
UAA3581
EN
CLK
DATA
16
3
17
2
18
1
23
VCCA(RF)
RFON
RFOP
LC MATCH AND
BIAS CHOKES
RFGND
VCCA(IF)
24
IFGND
GSMCLKO
UMTSCLKO
REFIN
EN
22
differential to
single-ended
FCA238
Objective specification
handbook, full pagewidth
21
SAW
UAA3580
Fig.4 Application diagram.
20
QN
19
DATA
9
15
12
QN
11
10
QP
13
REFGND
UMTSCLKO
11
IN
6
10
Vreg
VDDD
14
12
13
IP
5
9
EN
TCEN
15
8
1
16
VCCA(SYN)
REFIN
VCCA(CP)
4
7
15
REXT
16
UAA3580
QP
IFGND
14
ICTL
19
3
IN
RFIN
20
17
IP
RFIP
21
2
VCCA(IF)
RFGND
22
18
RXCEN
VCCA(RF)
23
1
CLK
24
VCOGND
CPCLKO
RFCPO
19
CAPVCOREG
13
Vdet
12
2
Philips Semiconductors
BATTERY
Wideband code division multiple access
frequency division duplex zero IF receiver
16 APPLICATION INFORMATION
2002 Oct 30
antenna
or switch
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
17 PACKAGE OUTLINE
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
A
B
D
SOT616-1
terminal 1
index area
A
A1
E
c
detail X
e1
C
1/2 e
e
12
y
y1 C
v M C A B
w M C
b
7
L
13
6
e
e2
Eh
1/2 e
1
18
terminal 1
index area
24
19
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
2.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT616-1
---
MO-220
---
2002 Oct 30
20
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-22
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
If wave soldering is used the following conditions must be
observed for optimal results:
18 SOLDERING
18.1
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
18.2
UAA3580
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
18.3
18.4
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Oct 30
Manual soldering
21
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
18.5
UAA3580
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, HBGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Oct 30
22
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
19 DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
20 DEFINITIONS
21 DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Oct 30
23
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA74
© Koninklijke Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403506/02/pp24
Date of release: 2002
Oct 30
Document order number:
9397 750 10632