ATMEL AT16646G-20YC

AT16646
Features
•
•
•
•
•
•
Fastest Propagation Speeds in the Industry TPD (F grade) = 2.5 ns, TPD (G grade) = 2.0 ns
Maximum derating for capacitive loads 1.5ns/100 pF (F grade) and 1.1ns/100 pF
(G grade)
Very low ground bounce < 0.6 V @ VCC =5.00 V, Ta=25°C
Typical output skew ≤0.25ns

Bus Hold circuitry to retain last active state during Tri-State
Available in SSOP and TSSOP packages
Description
Atmel’s AT16646 devices are 16-bit high speed, low power Tri-statable D type
registers, ideal for use in systems requiring both transparent and registered mode
functions. They are organized as two separate 8-bit bus transceivers. Data flow is
bi-directional, and can be controlled for multiplexed transmission between A bus and
B bus either directly or from the D registers by use of the direction control pin (xDir),
output enable (xOE), and select lines (xSAB and xSBA). Storage of data on the A bus
and B bus is controlled by the output pins. They have very low ground bounce and
excellent input noise rejection, giving the user stable signals in a high speed
environment. The Bus Hold feature eliminates the need for pull-up or pull-down
resistors and retains the last active state during a Tri-State event.
Functional Block Diagram
AT16646F
AT16646G
Pin Configurations
SSOP/TSSOP
1DIR
Pin Names
xDir, xOE
xCLKAB,xCLKBA
xSAB, xSBA
xAχ
Descriptions
Output Enable Inputs
Clock Pulse Inputs
Output Data Source Select Inputs
Data Register A Inputs
Data Register B Outputs
1SAB
1A1
VCC
1A4
GND
1A7
2A1
2A3
2A4
2A6
2A7
GND
xBχ
Data Register B Inputs
Data Register A Outputs
AT16646
Fast Logic
16-Bit
Tri-State
Register
2CLKAB
1CLKAB
GND
1A2
1A3
1A5
1A6
1A8
2A2
GND
2A5
VCC
2A8
2SAB
2DIR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
56
54
52
50
48
46
44
42
40
38
36
34
32
30
55
1CLKBA
53
GND
51
1B2
49
1B3
47
1B5
45
1B6
43
1B8
41
2B2
39
GND
37
2B5
35
VCC
33
2B8
31
2SBA
29
2OE
1OE
1SBA
1B1
VCC
1B4
GND
1B7
2B1
2B3
2B4
2B6
2B7
GND
2CLKBA
Top View
0757B
5-21
Function Table(1)
Data I/O(2)
Inputs
xOE
H
H
L
L
L
L
Notes:
xDir
X
X
L
L
H
H
xCLKAB
H or L
↑
X
X
X
H or L
xCLKBA
H or L
↑
X
H or L
X
X
xSAB
X
X
X
X
L
H
xSBA
X
X
L
H
X
X
xAχ
Input
xBχ
Input
Output
Input
Input
Output
Operation or Function
Isolation
Store A and B Data
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
1. H = High voltage level, L = Low voltage level, X = Don’t care, ↑ = Low-to-High transition
2. The data output functions may be enabled or disabled by various signals at the xOE or xDir inputs. Data input functions
are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Absolute Maximum Ratings*
Operating Temperature........................ 0°C to +70°C
Storage Temperature ...................... -65°C to +150°C
Voltage on any Pin
with Respect to Ground................. -2.0 V to +7.0 V(1)
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions beyond those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Notes:
Maximum Operating Voltage.............................. 6.0V
5.0 Volt DC Characteristics
1. Minimum voltage is -0.6 V dc which may
undershoot to -2.0 V for pulses of less than 20 ns.
Maximum output pin voltage is VCC +0.75 V dc
which may overshoot to +7.0 V for pulses of less
than 20 ns.
Applicable over recommended operating range from Ta = 0°C to +70°C, VCC = +5.0V +/- 5% (unless otherwise noted)
Symbol
Note:
5-22
Parameter
Test Conditions
∆ICC
Quiescent Power Supply
Current
VCC = Max, VIN = 3.4 V
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current (I/O Pins)
IIL
Input Low Current (I/O Pins)
IOZ
Output Leakage Current
Min
Typ
Max
Units
0.8
1.2
mA
2.0
V
0.8
V
VIN = VCC
±15
µA
VIN = GND
±15
µA
±10
µA
VOH(1)
Output High Voltage
F Grade only
VCC = 4.75 V
IOH = -10 mA
2.7
V
VOH(2)
Output High Voltage
G Grade only
VCC = 4.75 V
IOH = -12 mA
2.7
V
V OL
Output Low Voltage (F Grade)
IOL = 10 mA
0.55
V
V OL
Output Low Voltage (G Grade)
IOL = 12 mA
0.55
V
1. F grade: At VCC (max), the value of VOH(max) = 3.75 V and at VCC(min), VOH(max) = 3.25 V
2. G grade: At VCC (max), the value of VOH(max) = 3.75 V and at VCC(min), VOH(max) = 3.35 V
AT16646
AT16646
AC Characteristics
AT16646F
Applicable over recommended operating range from Ta = 0°C to +70°C, VCC = 5.0V +/- 5% (unless otherwise noted)
Symbol
Parameter
Test Conditions(1)
tPHL
tPLH
Propagation Delay
tPZH
tPZL
tPHZ
Min
Typ
Max
Units
CL = 50 pF
2.5
ns
Output Enable Time
CL = 50 pF
7.4
ns
Output Disable Time
CL = 50 pF
6.4
ns
tSK(1)
Output Skew
CL = 50 pF
0.5
ns
∆tPHL(1)
∆tPLH
Propagation Delay vs Output Loading
1.5
ns/100 pF
tsu
Set-up Time Bus to Clock
CL = 50 pF
2.0
ns
tH
Hold Time Bus to Clock
CL = 50 pF
2.0
ns
tPLZ
Note:
1.3
1. This parameter is guaranteed but not 100% tested.
AT16646G
Applicable over recommended operating range from Ta = 0°C to +70°C, VCC = 5.0V +/- 5% (unless otherwise noted)
Symbol
Parameter
Test Conditions(1)
tPHL
tPLH
Propagation Delay
tPZH
tPZL
tPHZ
Min
Typ
Max
Units
CL = 50 pF
2.0
ns
Output Enable Time
CL = 50 pF
7.4
ns
Output Disable Time
CL = 50 pF
5.8
ns
tSK(1)
Output Skew
CL = 50 pF
0.5
ns
∆tPHL(1)
∆tPLH
Propagation Delay vs Output Loading
1.1
ns/100 pF
tsu
Set-up Time Bus to Clock
CL = 50 pF
2.0
ns
tH
Hold Time Bus to Clock
CL = 50 pF
2.0
ns
tPLZ
Note:
1. This parameter is guaranteed but not 100% tested.
Test Circuits(1,2)
Switch Position
VCC
7.0V
500Ω
VIN
VOUT
Pulse
Generator
D.U.T.
50 pF
500Ω
RT
CL
Note:
0.9
1. Pulse Generator: Rate ≤ 1.0 MHz, tF ≤ 2.5 ns,
tR ≤ 2.5 ns.
2. AC tests are done with a single bit switching, and
timings need to be derated when multiple outputs are
switching in the same direction simultaneously. This
derating should not exceed 0.5 ns for 16 inputs switching
simultaneously.
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
Definitions:
CL = Load capacitance; Includes jig and probe capacitance.
RT = Termination resistance; Should be equal to ZOUT of the
Pulse Generator.
5-23
IOL Pull Down Current
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
120
IOL, mA
80
40
0
-40
IOL
Output, V
Output, V
160
Time
Ground Bounce for
High to Low Transitions(1)
Supply Bounce for
Low to High Transitions(2)
4.5
3.5
gnd - measured on
output with input
held constant
3.0
2.5
3
output
Volts
2.0
Volts
3.5
1.5
2.5
output
2
1
VOLP
0.5
0.0
0
VOLV
-0.5
VOHV
1.5
1.0
0.5
vcc measured on
output with
input held
constant
VOHP
4
Time
Time
Typical Values
Note:
5-24
Parameter
Value
Units
V OLP
0.4
V
V OLV
-0.26
V
V OHV
V CC - 0.13
V
V OHP
V CC + 0.6
V
1. When multiple outputs are switched at the same time, rapidly changing current on the ground and VCC path causes a
voltage to develop across the parasitic inductance of the wire bond and package pins. This occurrence is called
simultaneous switching noise. Atmel’s AT16646 products have minimized this phenomenon as shown on the graph.
Output data is for 15 outputs switching simultaneously at a frequency of 1 MHz. The ground data is measured on the
one remaining output, which is set to logic low and will reflect any device ground movement.
2. As on the graph for Ground Bounce, a similar condition occurs for low to high transitions. Output data is for 15
outputs switching simultaneously at a frequency of 1 MHz. V CC droop is measured on the one remaining output
pin, which is set to a logic high. This output will reflect any movement on the device VCC.
AT16646
AT16646
Propagation Delay Waveforms
Input
Transition
1.5 V
1.5 V
tPLH
tPHL
VOH
1.5 V
Output
Transition
VOL
Enable and Disable Waveforms(1)
Enable
Disable
3.0 V
Control
Input
1.5 V
0V
tPZL
Output
Switched
Low
tPLZ
3.5 V
Switch Closed
1.5 V
0.3 V
tPHZ
tPZH
Output
Switched
High
VOL
0.3 V
VOH
1.5 V
Switch Open
0V
Note:
1. Enable and disable waveforms are the same for both xOE and xDIR inputs.
5-25
Ordering Information
TPD
Ordering Code
Package
Operation Range
2.5 ns
AT16646F - 25YC
AT16646F - 25XC
56Y
56X
Commercial
2.0 ns
AT16646G - 20YC
AT16646G - 20XC
56Y
56X
Commercial
Package Type
56X
56 Pin, Plastic Thin Shrink Small Outline Package (TSSOP)
56Y
56 Pin, Plastic Shrink Small Outline Package (SSOP)
5-26
AT16646