Features • • • • • • • • Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (Pout Typically 23 dBm) Ramp-controlled Output Power Low-noise Preamplifier (NF Typically 2.1 dB) Biasing for External PIN Diode T/R Switch Current-saving Standby Mode Few External Components Packages: – PSSO20 – QFN20 with Extended Performance Electrostatic sensitive device. Observe precautions for handling. Bluetooth™/ISM 2.4-GHz FrontEnd IC T7024 Description The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like Bluetooth™ and WDCT. Due to the ramp-control feature and a very low quiescent current, an external switch transistor for VS is not required. Figure 1. Block Diagram RX_ON PU VS_LNA TX TX/RX/ standby Control SWITCH_OUT R_SWITCH RX LNA_OUT LNA_IN LNA RAMP V1_PA V2_PA PA_IN V3_PA_OUT PA 4533D–BLURF–01/04 Pin Configuration Figure 2. Pinning PSSO20 20 PU 1 18 LNA_OUT GND 3 V3_PA_OUT V3_PA_OUT V3_PA_OUT GND RAMP 16 PA_IN VS_LNA 5 T7024 GND 6 15 V1_PA V3_PA_OUT 8 13 V2_PA 9 12 V2_PA GND 10 11 RAMP 9 8 7 6 11 5 12 4 13 T7024 3 2 14 1 15 SWITCH_OUT R_SWITCH PU RX_ON LNA_OUT 16 17 18 19 20 14 GND 7 V3_PA_OUT 10 17 GND LNA_IN 4 V3_PA_OUT GND VS_LNA GND LNA_IN GND 19 RX_ON SWITCH_OUT 2 V2_PA V2_PA GND V1_PA PA_IN R_SWITCH Figure 3. Pinning QFN20 Pin Description 2 Pins PSSO20 Pins QFN20 Symbol 1 4 R_SWITCH 2 5 SWITCH_OUT 3 6 GND 4 7 LNA_IN Low-noise amplifier input 5 9 VS_LNA Supply voltage input for low-noise amplifier 6 8 GND 7 11 V3_PA_OUT Inductor to power supply and matching network for power amplifier output 8 12 V3_PA_OUT Inductor to power supply and matching network for power amplifier output 9 13 V3_PA_OUT Inductor to power supply and matching network for power amplifier output 10 10 GND 11 15 RAMP Power ramping control input 12 16 V2_PA Inductor to power supply for power amplifier 13 17 V2_PA Inductor to power supply for power amplifier 14 14 GND 15 19 V1_PA 16 20 PA_IN Power amplifier input 17 18 GND Ground 18 1 LNA_OUT 19 2 RX_ON 20 3 PU Slug Slug GND Function Resistor to GND sets the PIN diode current Switched current output for PIN diode Ground Ground Ground Ground Supply voltage for power amplifier Low-noise amplifier output RX active high Power-up active high Ground T7024 4533D–BLURF–01/04 T7024 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Supply voltage Pins VS_LNA, V1_PA, V2_PA, V3_PA_OUT VS 6 V Junction temperature Tj 150 °C Storage temperature Tstg -40 to +125 °C RF input power LNA PinLNA 5 dBm RF input power PA PinPA 10 dBm Symbol Value Unit Junction ambient PSSOP20, slug soldered on PCB RthJA 19 K/W Junction ambient QFN20, slug soldered on PCB RthJA 27 K/W Thermal Resistance Parameters Handling Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test requirement (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test requirement (MM) in accordance to EIA/JESD22-A115A. Operating Range All voltages are referred to ground (pins GND and slug). Power supply points are VS_LNA, V1_PA, V2_PA, V3_PA_OUT. The table represents the sum of all supply currents depending on the TX/RX mode. Parameters Symbol Min. Typ. Max. Unit Supply voltage Pins V1_PA, V2_PA and V3_PA_OUT VS 2.7 3.0 4.6 V Supply voltage Pin VS_LNA VS 2.7 3.0 5.5 V Supply current TX PSSO20 QFN20 IS IS IS 190 165 8 mA mA mA IS_standby 10 µA Supply current RX Standby current Ambient temperature PU = 0 Tamb -25 +25 +85 °C 3 4533D–BLURF–01/04 Electrical Characteristics Test conditions (unless otherwise specified): VS = 3.0 V, Tamb = 25°C Parameters Test Conditions Symbol Min. VS 2.7 Typ. Max. 3.0 4.6 Unit (1) Power Amplifier Supply voltage Pins V1_PA, V2_PA, V3_PA_OUT Supply current TX TX PSSO20 QFN20 RX (PA off), VRAMP ≤0.1 V IS_TX IS_TX 190 165 IS_RX 10 Standby current Standby Frequency range TX f 2.4 Gain-control range TX ∆Gp 60 42 Power gain maximum TX, Pin PA_IN to V3_PA_OUT Gp 28 30 Power gain minimum TX, Pin PA_IN to V3_PA_OUT Gp -40 Ramping voltage maximum TX, power gain (maximum) Pin RAMP VRAMP max 1.7 Ramping voltage minimum TX, power gain (minimum) Pin RAMP VRAMP min Ramping current maximum TX, VRAMP = 1.75 V, Pin RAMP IRAMP max Power-added efficiency TX TX Saturated output power TX, input power = 0 dBm referred to Pins V3_PA_OUT Input matching(2) TX, Pin PA_IN Load VSWR <1.5:1 Output matching(2) TX, Pins V3_PA_OUT Load VSWR <1.5:1 TX, Pins V3_PA_OUT TX, Pins V3_PA_OUT Harmonics at Psat = 23 dBm IS_standby PSSO20 QFN20 1.75 10 µA GHz dB 33 dB -17 dB 1.83 V V 0.5 30 35 35 40 Psat 22 23 µA 2.5 0.1 PAE PAE V mA mA mA % % 24 dBm 2 fo -30 dBc 3 fo -30 dBc IS_O_standby 1 µA RX IS_O_RX 1 µA TX at 100 Ω IS_O_100 TX at 1.2 kΩ TX at 33 kΩ T/R Switch Driver (Current Programming by External Resistor from R_SWITCH to GND) Standby, Pin SWITCH_OUT Switch-out current output TX at ∞ Low-noise Amplifier 1.7 mA IS_O_1k2 7 mA IS_O_33k 17 mA IS_O_R 19 mA (3) Supply voltage All, Pin VS_LNA VS Supply current RX IS Notes: 4 2.7 3.0 5.5 V 8 9 mA 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10 s, ZG = 50 Ω. 2. With external matching network, load impedance 50 Ω. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 19 on page 11. Please note, that for RX_ON below 1.4 V the T/R switch driver switches to TX mode. T7024 4533D–BLURF–01/04 T7024 Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 3.0 V, Tamb = 25°C Parameters Test Conditions Supply current (LNA and control logic) TX (control logic active) Pin VS_LNA Standby current Standby, Pin VS_LNA Frequency range RX Symbol Min. IS_standby RX, Pin LNA_IN to LNA_OUT Gp 15 Noise figure RX, RX NF NF Gain compression RX, referred to Pin LNA_OUT rd 3 -order input interception point Input matching (4) Output matching PSSO20 QFN20 RX RX, Pin LNA_IN (4) Unit 0.5 mA 10 µA 2.5 GHz 16 19 dB 2.5 2.1 2.8 2.3 dB dB 1 2.4 Power gain Max. IS f (5) Typ. RX Pin LNA_OUT O1dB -9 -7 -6 dBm IIP3 -16 -14 -13 dBm VSWRin 2:1 VSWRout 2:1 Logic Input Levels (RX_ON, PU)(5) High input level = ‘1’ Pins RX_ON and PU ViH 2.4 VS, LNA V Low input level = ‘0’ ViL 0 0.5 V High input current = ‘1’ ViH = 2.4 V IiH 60 µA Low input current = ‘0’ IiL 0.2 µA Notes: 40 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10 s, ZG = 50 Ω. 2. With external matching network, load impedance 50 Ω. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 19 on page 11. Please note, that for RX_ON below 1.4 V the T/R switch driver switches to TX mode. Control Logic for LNA and T/R Switch Driver Operation Mode PU RX_ON Standby 0 0 TX 1 0 RX 1 1 5 4533D–BLURF–01/04 Typical Operating Characteristics Figure 4. LNA (PSSO20): Gain and Noise Figure versus Frequency 20 8 7 Gain 6 5 NF 10 4 3 5 NF (dB) Gain (dB) 15 2 1 0 2000 2200 2400 2600 0 3000 2800 Frequency (MHz) Figure 5. LNA (N20): Gain and Noise Figure versus Frequency 25 5 20 4 15 3 NF 10 2 5 1 0 2000 2200 2400 2600 NF (dB) Gain (dB) Gain 0 3000 2800 Frequency (MHz) Figure 6. LNA: NF and Gain versus Temperature 2.5 2.0 NF VS = 3 V Relative gain, relative NF (dB) 1.5 1.0 0.5 0.0 -0.5 Gain -1.0 -1.5 -2.0 -2.5 -40 -20 0 20 40 60 80 Temperature (°C) 6 T7024 4533D–BLURF–01/04 T7024 Figure 7. LNA: Typical Switch-out Current versus Rswitch 20 IS_O(mA) 16 12 8 4 0 1 10 100 1000 10000 100000 1000000 10000000 Rswitch(Ω) Figure 8. PA (PSSO20): Output Power and PAE versus Supply 50 250 40 220 PAE 30 190 Pout 20 160 f = 2.4 GHz Vramp = 1.75 V PinPA = 0 dBm 10 130 0 2.7 3.1 3.5 3.9 IS_TX (mA) Pout (dBm), PAE (%) I_S_TX 4.3 100 4.7 Supply Voltage (V) Figure 9. PA (PSSO20): Output Power and PAE versus Ramp Voltage 50 250 200 Pout 10 150 -10 100 IS_TX (mA) Pout (dBm), PAE (%) PAE 30 f = 2.4 GHz VS = 3 V PinPA = 0 dBm I_S_TX -30 50 -50 0 1.2 1.4 1.6 1.8 2.0 Vramp (V) 7 4533D–BLURF–01/04 Figure 10. PA (PSSO20): Output Power and PAE versus Input Power 250 PAE Gain 30 200 20 150 IS_TX (mA) Pout (dBm), PAE (%), Gp (dB) 40 I_S_TX 10 100 VS = 3 V f = 2.4 GHz Vramp = 1.75 V PinPA = 0 dBm 0 50 Pout -10 -40 0 -30 -20 -10 0 10 Input Power (dBm) Figure 11. PA (PSSO20): Output Power and PAE versus Frequency 250 I_S_TX 40 200 PAE 30 150 Pout 20 100 VS = 3 V Vramp = 1.7 V PinPA = 0 dBm 10 0 2400 2420 IS_TX (mA) Pout (dBm), PAE (%) 50 2440 2460 50 0 2500 2480 Frequency (MHz) Figure 12. PA (QFN20): Output Power and PAE versus Supply Voltage 250 40 220 PAE I_S_TX 30 190 Pout 20 f = 2.4 GHz Vramp = 1.8 V PinPA = 0 dBm 10 130 0 2.7 3.1 3.5 3.9 160 IS_TX (mA) Pout (dBm), PAE (%) 50 4.3 100 4.7 Supply Voltage (V) 8 T7024 4533D–BLURF–01/04 T7024 Figure 13. PA (QFN20) Output Power and PAE versus Ramp Voltage 50 250 Pout 30 200 10 150 -10 100 IS_TX (mA) Pout (dBm), PAE (%) PAE f = 2.4 GHz VS = 3 V PinPA = 0 dBm I_S_TX -30 50 -50 0 1.2 1.4 1.6 1.8 2.0 Vramp (V) 50 300 PAE 40 250 Gain 30 20 200 150 I_S_TX 10 IS_TX (mA) Pout (dBm), PAE (%), Gp (dB) Figure 14. PA (QFN20): Output Power and PAE versus Input Power 100 VS = 3 V f = 2.4 GHz Vramp = 1.8 V PinPA = 0 dBm 0 50 Pout -10 -40 0 -30 -20 -10 0 10 Input Power (dBm) Figure 15. PA (QFN20): Output Power and PAE versus Frequency 50 250 200 I_S_TX 30 150 Pout 20 VS = 3 V Vramp = 1.8 V PinPA = 0 dBm 10 0 2400 100 IS_TX (mA) Pout (dBm), PAE (%) PAE 40 50 2420 2440 2460 2480 0 2500 Frequency (MHz) 9 4533D–BLURF–01/04 Figure 16. LNA: Supply Current versus Temperature Supply current (mA) 8.0 7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 -40 -20 0 20 40 60 80 Temperature (°C) Figure 17. PA (PSSO20): Supply Current versus Iramp and Temperature Supply current (mA) 200 180 160 -40°C 140 120 40°C 100 0°C 80 60 40 80°C 20 0 0.1 1.0 10.0 100.0 1000.0 Iramp (µA) Figure 18. PA (PSSO20, QFN20): Pout versus Vramp and Temperature 30 f = 2.4 GHz VS = 3 V Pin = 0 dBm 20 Pout (dBm) 5 10 25 0 -15 80 -10 -40°C -20 1.0 1.2 1.4 1.6 1.8 Vramp (V) 10 T7024 4533D–BLURF–01/04 T7024 Figure 19. (PSSO20, QFN20): LNA Gain (dB) versus RX_ON (V) 20.0 15.0 10.0 Gain (dB) 5.0 VS = 3 V 0.0 -5.0 -10.0 -15.0 -20.0 -25.0 1.0 1.5 2.0 2.5 3.0 RX_ON (V) Input/Output Circuits Figure 20. Input Circuit PA_IN/V1_PA V1_PA PA_IN GND Figure 21. Input Circuit RAMP/V1_PA V1_PA RAMP 11 4533D–BLURF–01/04 Figure 22. Input Circuit V2_PA V2_PA GND Figure 23. Input/Output Circuit V3_PA_OUT V3_PA_OUT GND Figure 24. Input Circuit SWITCH_OUT/R_SWITCH V1_PA SWITCH_OUT R_SWITCH GND 12 T7024 4533D–BLURF–01/04 T7024 Figure 25. Input Circuit LNA_IN/VS_LNA VS_LNA LNA_IN GND Figure 26. Input Circuit PU/RX_ON VS_LNA LNA_IN / PU Figure 27. Output Circuit LNA_OUT VS_LNA LNA_OUT GND 13 4533D–BLURF–01/04 Figure 28. Typical Application T7024 (PSSO20 Package) LNA OUT PA IN 5.6nH V1_PA 3.9nH RX ON 3p3 V2_PA PU 3.9p 20 19 18 17 16 15 14 13 12 11 PA ramp 1 2 3 4 5 6 7 8 9 10 T7024 harm. termination 1p5 R1 is selected with DIL-switch Pin-diode replaced by LED on application-board 14 R1 1.8p 15nH LNA IN V3_PA VS_LNA Switch Out PA OUT 0p8 Blocking capacitors depending on application T7024 4533D–BLURF–01/04 T7024 Figure 29. Typical Application T7024 (QFN20 Package) LNA OUT PA IN V1_PA V2_PA 2.2p 1 2 3 4 5 RX ON PU R1 is selected with DIL-switch 3p3 1p R1 Var 20 19 18 17 16 15 14 T7024 13 12 11 6 7 8 9 10 PA ramp harm. termination 2p2 0p8 1.8p 18nH LNA IN Pin-diode replaced by LED on application-board Switch Out VS_LNA V3_PA PA OUT blocking capacitors depending on application 15 4533D–BLURF–01/04 Ordering Information Extended Type Number Package Remarks MOQ T7024-TRS PSSO20 Tube 830 pcs. T7024-TRQ PSSO20 Taped and reeled 4000 pcs. T7024-PGP QN20 Taped and reeled 1500 pcs. T7024-PGQ QFN20 Taped and reeled 6000 pcs. Package Information 16 T7024 4533D–BLURF–01/04 T7024 17 4533D–BLURF–01/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2004. All rights reserved. Atmel ® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. The Bluetooth name and the Bluetooth trademarks are owned By Bluetooth SIG, and are used by Atmel Corporation under license. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4533D–BLURF–01/04