TI CDC536DB

CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
D
D
D
D
D
D
D
D
D
D
D
D
D
DB OR DL PACKAGE
(TOP VIEW)
Low-Output Skew for Clock-Distribution
and Clock-Generation Applications
Operates at 3.3-V VCC
Distributes One Clock Input to Six Outputs
One Select Input Configures Three Outputs
to Operate at One-Half or Double the Input
Frequency
No External RC Network Required
External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
Application for Synchronous DRAM,
High-Speed Microprocessor
Negative-Edge-Triggered Clear for
Half-Frequency Outputs
TTL-Compatible Inputs and Outputs
Outputs Drive 50-Ω Parallel-Terminated
Transmission Lines
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
Distributed VCC and Ground Pins Reduce
Switching Noise
Packaged in Plastic 28-Pin Shrink Small
Outline Package
AVCC
AGND
CLKIN
SEL
OE
GND
1Y1
VCC
GND
1Y2
VCC
GND
1Y3
VCC
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
AVCC
AGND
FBIN
TEST
CLR
VCC
2Y1
GND
VCC
2Y2
GND
VCC
2Y3
GND
description
The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely
align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically
designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to
100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V
VCC and is designed to drive a 50-W transmission line.
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock
(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between
CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL)
input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin
is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the
duty cycle at the input clock.
Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.
When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass
the PLL. TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
description (continued)
Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or
feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon
enable of all outputs via OE.
The CDC536 is characterized for operation from 0°C to 70°C.
detailed description of output configurations
The voltage-controlled oscillator (VCO) in the CDC536 has a frequency range of 100 MHz to 200 MHz, twice
the operating frequency range of the CDC536 outputs. The output of the VCO is divided by two and by four to
provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. The SEL0
and SEL1 inputs determine which of the two signals are buffered to each bank of device outputs.
One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency of this output matches that of the CLKIN signals. In the case that a VCO/2 output is wired to FBIN,
the VCO must operate at twice the CLKIN frequency, resulting in device outputs that operate at the same or
one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at the same or
twice the CLKIN frequency.
output configuration A
Output configuration A is valid when any output configured as a 1× frequency output in Table 1 is fed back to
the FBIN input. The input frequency range for the CLKIN input is 50 MHz to 100 MHz when using output
configuration A. Outputs configured as 1/2× outputs operate at half the CLKIN frequency, while outputs
configured as 1× outputs operate at the same frequency as the CLKIN input.
Table 1. Output Configuration A
INPUTS
OUTPUTS
SEL
1/2×
FREQUENCY
1×
FREQUENCY
L
None
All
H
1Yn
2Yn
NOTE: n = 1, 2, 3
output configuration B
Output configuration B is valid when any output configured as a 1× frequency output in Table 2 is fed back to
FBIN. The input frequency range for the CLKIN input is 25 MHz to 50 MHz when using output configuration B.
Outputs configured as 1× outputs operate at the CLKIN frequency, while outputs configured as 2× outputs
operate at double the frequency of the CLKIN input.
Table 2. Output Configuration B
INPUTS
OUTPUTS
SEL
1×
FREQUENCY
2×
FREQUENCY
L
All
None
H
1Yn
2Yn
NOTE: n = 1, 2, 3
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
functional block diagram
OE
5
24
CLR
FBIN
26
ÎÎÎÎÎÎÎ
ÁÁÁ
ÎÎÎÎÎÎÎ
ÁÁÁ
B
ÁÁÁÁÁÁ
ÎÎÎÎÎÎÎ
ÁÁÁ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Phase-Lock Loop
3
CLKIN
TEST
SEL
25
2
ÁÁÁ
B
ÁÁÁ
ÁÁÁ
2
4
7
10
13
22
19
16
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• DALLAS, TEXAS 75265
1Y1
1Y2
1Y3
2Y1
2Y2
2Y3
3
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
Terminal Functions
TERMINAL
NAME
4
NO.
I/O
DESCRIPTION
CLKIN
3
I
Clock input. CLKIN provides the clock signal to be distributed by the CDC536 clock-driver circuit. CLKIN is used
to provide the reference signal to the integrated phase-lock loop that generates the clock output signals. CLKIN
must have a fixed frequency and fixed phase in order for the phase-lock loop to obtain phase lock. Once the
circuit is powered up and a valid CLKIN signal is applied, a stabilization time is required for the phase-lock loop
to phase lock the feedback signal to its reference signal.
CLR
24
I
CLR is used for testing purposes only.
FBIN
26
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of the
six clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to obtain zero
phase delay between the FBIN and differential CLKIN inputs.
OE
5
I
Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE is
high, all outputs are in the high-impedance state. Since the feedback signal for the phase-lock loop is taken
directly from an output, placing the outputs in the high-impedance state interrupts the feedback loop; therefore,
when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is required before
the phase-lock loop obtains phase lock.
SEL
4
I
Output configuration select. SEL selects the output configuration for each output bank (e.g. 1×, 1/2×, or 2×).
(see Tables 1 and 2).
TEST
25
I
TEST is used to bypass the phase-lock loop circuitry for factory testing of the device. When TEST is low, all
outputs operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses
the PLL circuitry. TEST should be grounded for normal operation.
1Y1 – 1Y3
7, 10, 13
O
These outputs are configured by SEL to transmit one-half or one-fourth the frequency of the VCO. The
relationship between the CLKIN frequency and the output frequency is dependent on SEL. The duty cycle of
the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal.
2Y1 – 2Y3
22, 19, 16
O
These outputs transmit one-half the frequency of the VCO. The relationship between the CLKIN frequency and
the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty cycle of the
Y output signals is nominally 50% independent of the duty cycle of the CLKIN signal.
POST OFFICE BOX 655303
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CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . – 0.5 V to 5.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . 0.68 W
DL package . . . . . . . . . . . . . . . . . . . . 0.7 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
recommended operating conditions (see Note 3)
MIN
MAX
3.6
UNIT
VCC
VIH
Supply voltage
3
High-level input voltage
2
VIL
VI
Low-level input voltage
5.5
V
IOH
IOL
High-level output current
– 32
mA
Low-level output current
32
mA
70
°C
V
0.8
Input voltage
0
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low.
0
V
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IOZH
IOZL
ICC
Ci
TA = 25°C
MIN
MAX
TEST CONDITIONS
VCC = 3 V,
VCC = MIN to MAX‡,
II = –18 mA
IOH = – 100 µA
VCC = 3 V,
VCC = 3 V,
IOH = – 32 mA
IOL = 100 µA
VCC = 3 V,
VCC = 0 or MAX‡,
IOL = 32 mA
VI = 3.6 V
VCC = 3.6 V,
VCC = 3.6 V,
VI = VCC or GND
VO = 3 V
VCC = 3.6 V,
VO = 0
VCC = 3.6
3 6 V,
V
VI = VCC or GND
–1.2
VCC – 0.2
2
0.5
±10
±1
VI = VCC or GND
VO = VCC or GND
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
µA
10
µA
– 10
µA
Outputs high
2
Outputs low
2
Outputs disabled
2
Co
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
V
V
0.2
IO = 0
0,
UNIT
mA
6
pF
9
pF
5
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
fclock
l k
Clock frequency
MIN
MAX
When VCO is operating at four times the CLKIN frequency
25
50
When VCO is operating at double the CLKIN frequency
50
100
40%
60%
Input clock duty cycle
Stabilization time†
After SEL
50
After OE↓
50
After power up
50
UNIT
MHz
µs
After CLKIN
50
† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay
and skew parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Note 4 and Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
Y
45%
55%
CLKIN↑
Y
–500
+500
ps
CLKIN↑
Y
200
ps
0.5
ns
1
ns
1.4
ns
fmax
Duty cycle
tphase error‡
Jitter(pk-pk)
tsk(o)‡
MAX
100
tsk(pr)
tr
UNIT
MHz
tf
1.4
ns
‡ The propagation delay, tphase error, is dependent on the feedback path from any output to FBIN. The tphase error, tsk(o), and tsk(pk) specifications
are only valid for equal loading of all outputs.
NOTE 4: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6
POST OFFICE BOX 655303
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CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
3V
Input
1.5 V
1.5 V
0V
tphase error
From Output
Under Test
CL = 30 pF
(see note A)
500 W
Output
2V
0.8 V
tr
LOAD CIRCUIT FOR OUTPUTS
VOH
2V
1.5 V
0.8 V
VOL
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
CLKIN
tphase error 1
Outputs
Operating
at 1/2 CLKIN
Frequency
tphase error 2
tphase error 3
Outputs
Operating
at CLKIN
Frequency
tphase error 4
tphase error 7
tphase error 5
tphase error 8
tphase error 6
tphase error 9
NOTES: A. Output skew, tsk(o), is calculated as the greater of:
– The difference between the fastest and slowest of tphase error n (n = 1, 2, . . . 6)
– The difference between the fastest and slowest of tphase error n (n = 7, 8, 9)
B. Process skew, tsk(pr), is calculated as the greater of:
– The difference between the maximum and minimum tphase error n (n = 1, 2, . . . 6) across multiple devices under identical
operating conditions.
– The difference between the maximum and minimum tphase error n (n = 7, 8, 9) across multiple devices under identical
operating conditions.
Figure 2. Skew Waveforms and Calculations
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
CLKIN
tphase error 10
Outputs
Operating
at CLKIN
Frequency
tphase error 11
tphase error 12
tphase error 13
Outputs
Operating
at 2× CLKIN
Frequency
tphase error 14
tphase error 15
NOTES: A. Output skew, tsk(o), is calculated as the greater of:
– The difference between the fastest and slowest of tphase error n (n = 10, 11, . . . 15)
B. Process skew, tsk(pr), is calculated as the greater of:
– The difference between the maximum and minimum tphase error n (n = 10, 11, . . . 15) across multiple devices under identical
operating conditions.
Figure 3. Waveforms for Calculation of tsk(o) and tsk(pr)
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9
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
MECHANICAL INFORMATION
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°– 8°
1,03
0,63
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
A MAX
3,30
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
2,70
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 / C 10/95
NOTES: A.
B.
C.
D.
10
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
MECHANICAL INFORMATION
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0.025 (0,635)
0.012 (0,305)
0.008 (0,203)
48
0.005 (0,13) M
25
0.006 (0,15) NOM
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°– 8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / C 03/97
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
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Copyright  1998, Texas Instruments Incorporated