CY7C109D CY7C1009D 1-Mbit (128 K × 8) Static RAM 1-Mbit (128 K × 8) Static RAM Features ■ Pin- and function-compatible with CY7C109B/CY7C1009B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA ■ 2.0 V Data Retention ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE1, CE2 and OE options ■ CY7C109D available in Pb-free 32-pin 400-Mil wide Molded SOJ and 32-pin TSOP I packages. CY7C1009D available in Pb-free 32-pin 300-Mil wide Molded SOJ package (OE), and tri-state drivers.The eight input and output pins (I/O0 through I/O7) are placed in a high-impedance state when: ■ Deselected (CE1 HIGH or CE2 LOW), ■ Outputs are disabled (OE HIGH), ■ When the write operation is active (CE1 LOW, CE2 HIGH, and WE LOW) Write to the device by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Functional Description The CY7C109D/CY7C1009D [1] is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable Read from the device by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the I/O pins. The CY7C109D/CY7C1009D device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. For a complete list of related documentation, click here. Logic Block Diagram IO0 INPUT BUFFER IO1 128K x 8 ARRAY IO3 IO4 IO5 IO6 CE1 CE2 COLUMN DECODER IO7 POWER DOWN A9 A10 A11 A12 A13 A14 A15 A16 WE OE Cypress Semiconductor Corporation Document Number: 38-05468 Rev. *J IO2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 16, 2015 CY7C109D CY7C1009D Contents Pin Configurations ........................................................... 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Document Number: 38-05468 Rev. *J Page 2 of 16 CY7C109D CY7C1009D Pin Configurations Figure 2. 32-pin SOJ pinout (Top View) [2] Figure 1. 32-pin TSOP I pinout A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP I Top View (not to scale) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Selection Guide Description CY7C109D-10 CY7C1009D-10 Unit Maximum Access Time 10 ns Maximum Operating Current 80 mA Maximum CMOS Standby Current 3 mA Note 2. NC pins are not connected on the die. Document Number: 38-05468 Rev. *J Page 3 of 16 CY7C109D CY7C1009D DC Input Voltage [3] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Storage Temperature ............................... –65 C to +150 C Latch-up Current .................................................... > 200 mA Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Operating Range Supply Voltage on VCC to Relative GND [3] ...............................–0.5 V to +6.0 V DC Voltage Applied to Outputs in High-Z State [3] ................................ –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Speed Industrial –40 °C to +85 °C 5 V 0.5 V 10 ns Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage 7C109D-10 7C1009D-10 Test Conditions IOH = –4.0 mA IOH = –0.1mA VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage [3] IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VI < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC Unit Min Max 2.4 – – IOL = 8.0 mA 3.4 V [4] 0.4 V 2.2 VCC + 0.5 V –0.5 0.8 V –1 +1 A –1 +1 A 100 MHz – 80 mA 83 MHz – 72 mA 66 MHz – 58 mA 40 MHz – 37 mA ISB1 Automatic CE Power-Down Current – TTL Inputs Max VCC, CE1 > VIH or CE2 < VIL, VIN > VIH or VIN < VIL, f = fmax – 10 mA ISB2 Automatic CE Power-Down Current – CMOS Inputs Max VCC, CE1 > VCC – 0.3 V, or CE2 < 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 3 mA Note 3. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. 4. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider. Document Number: 38-05468 Rev. *J Page 4 of 16 CY7C109D CY7C1009D Capacitance Parameter [5] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Max Unit 8 pF 8 pF Thermal Resistance Parameter [5] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 300-Mil Wide SOJ 400-Mil Wide SOJ TSOP I Unit 57.61 56.29 50.72 °C/W 40.53 38.14 16.21 °C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [6] ALL INPUT PULSES 3.0 V Z = 50 90% OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* 90% 10% 10% GND 1.5 V Rise Time: 3 ns (a) (b) Fall Time: 3 ns High-Z characteristics: R1 480 5V OUTPUT INCLUDING JIG AND SCOPE R2 255 5 pF (c) Notes 5. Tested initially and after any design or process changes that may affect these parameters. 6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure 3 (a). High-Z characteristics are tested for all speeds using the test load shown in Figure 3 (c). Document Number: 38-05468 Rev. *J Page 5 of 16 CY7C109D CY7C1009D Data Retention Characteristics Over the Operating Range Parameter Description Conditions VCC = VDR = 2.0 V, CE1 > VCC – 0.3 V or CE2 < 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V VDR VCC for Data Retention ICCDR Data Retention Current tCDR [7] Chip Deselect to Data Retention Time tR [8] Operation Recovery Time Min Max Unit 2.0 – V – 3 mA 0 – ns tRC – ns Data Retention Waveform Figure 4. Data Retention Waveform DATA RETENTION MODE VCC 4.5 V VDR > 2 V tCDR 4.5 V tR CE Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. Document Number: 38-05468 Rev. *J Page 6 of 16 CY7C109D CY7C1009D Switching Characteristics Over the Operating Range Parameter [9] Description 7C109D-10 7C1009D-10 Unit Min Max Read Cycle tpower [10] VCC(typical) to the first access 100 – s tRC Read Cycle Time 10 – ns tAA Address to Data Valid – 10 ns tOHA Data Hold from Address Change 3 – ns tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid – 10 ns tDOE OE LOW to Data Valid – 5 ns tLZOE OE LOW to Low Z 0 – ns – 5 ns tHZOE OE HIGH to High Z [11, 12] [12] tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z 3 – ns tHZCE CE1 HIGH to High Z, CE2 LOW to High Z [11, 12] – 5 ns CE1 LOW to Power-Up, CE2 HIGH to Power-Up 0 – ns CE1 HIGH to Power-Down, CE2 LOW to Power-Down – 10 ns tPU [13] tPD [13] Write Cycle [14, 15] tWC Write Cycle Time 10 – ns tSCE CE1 LOW to Write End, CE2 HIGH to Write End 7 – ns tAW Address Set-Up to Write End 7 – ns tHA Address Hold from Write End 0 – ns tSA Address Set-Up to Write Start 0 – ns tPWE WE Pulse Width 7 – ns tSD Data Set-Up to Write End 6 – ns tHD Data Hold from Write End 0 – ns tLZWE WE HIGH to Low Z [12] 3 – ns – 5 ns tHZWE WE LOW to High Z [11, 12] Notes 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 10. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 11. tHZOE, tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 3 on page 5. Transition is measured when the outputs enter a high impedance state. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 13. This parameter is guaranteed by design and is not tested. 14. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 15. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05468 Rev. *J Page 7 of 16 CY7C109D CY7C1009D Switching Waveforms Figure 5. Read Cycle No. 1 (Address Transition Controlled) [16, 17] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 6. Read Cycle No. 2 (OE Controlled) [17, 18] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 16. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 17. WE is HIGH for read cycle. 18. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Document Number: 38-05468 Rev. *J Page 8 of 16 CY7C109D CY7C1009D Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (CE1 or CE2 Controlled) [19, 20] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tHA tPWE WE tSD tHD DATA VALID DATA I/O Figure 8. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [19, 20] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA tHA tPWE WE OE tSD DATA I/O t HD DATAIN VALID NOTE 21 tHZOE Notes 19. Data I/O is high impedance if OE = VIH. 20. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 21. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05468 Rev. *J Page 9 of 16 CY7C109D CY7C1009D Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [22, 23] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 24 tHD DATA VALID tHZWE tLZWE Notes 22. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. 23. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 24. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05468 Rev. *J Page 10 of 16 CY7C109D CY7C1009D Truth Table CE1 CE2 OE WE I/O0–I/O7 Mode Power H X X X High Z Power-down Standby (ISB) X L X X High Z Power-down Standby (ISB) L H L H Data Out Read Active (ICC) L H X L Data In Write Active (ICC) L H H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Package Diagram Ordering Code Package Type CY7C109D-10VXI 51-85033 32-pin SOJ (400 Mils) Pb-free CY7C109D-10ZXI 51-85056 32-pin TSOP (Type I) Pb-free CY7C1009D-10VXI 51-85041 32-pin SOJ (300 Mils) Pb-free Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 xx9 D - 10 X X I Temperature Range: I = Industrial Pb-free Package Type: X = V or Z V = 32-pin SOJ Z = 32-pin TSOP Type I Speed: 10 ns Process Technology: D = C9, 90 nm Technology xx9 = 09 or 009 = (400 Mils / 300 Mils) 1-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05468 Rev. *J Page 11 of 16 CY7C109D CY7C1009D Package Diagrams Figure 10. 32-pin SOJ (300 Mils) V32.3 (Catalog 32.3 Molded SOJ) Package Outline, 51-85041 51-85041 *D Figure 11. 32-pin SOJ (400 Mils) V32.4 (Molded SOJ V33) Package Outline, 51-85033 51-85033 *E Document Number: 38-05468 Rev. *J Page 12 of 16 CY7C109D CY7C1009D Package Diagrams (continued) Figure 12. 32-pin TSOP I (8 × 20 × 1.0 mm) Z32R Package Outline, 51-85056 51-85056 *G Document Number: 38-05468 Rev. *J Page 13 of 16 CY7C109D CY7C1009D Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static random access memory mA milliampere SOJ Small Outline J-Lead mV millivolt TSOP Thin Small Outline Package mW milliwatt Very Fine-Pitch Ball Grid Array ns nanosecond VFBGA Document Number: 38-05468 Rev. *J Symbol Unit of Measure pF picofarad V volt W watt Page 14 of 16 CY7C109D CY7C1009D Document History Page Document Title: CY7C109D/CY7C1009D, 1-Mbit (128 K × 8) Static RAM Document Number: 38-05468 Revision ECN Submission Date Orig. of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233722 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165) Pb-free offering in Ordering Information *B 262950 See ECN RKF Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics Table Shaded Ordering Information *C See ECN See ECN RKF Reduced Speed bins to -10 and -12 ns *D 560995 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Changed Overshoot spec from VCC+2 V to VCC+1 V in footnote #3 Updated Thermal Resistance table Updated Ordering Information Table *E 802877 See ECN VKN Changed ICC spec from 60 mA to 80 mA for 100 MHz, 55 mA to 72 mA for 83 MHz, 45 mA to 58 mA for 66 MHz, 30 mA to 37 mA for 40 MHz *F 3104943 12/08/2010 AJU Added Ordering Code Definitions. Updated Package Diagrams. *G 3220123 04/08/2011 PRAS Updated package diagrams: 51-85033 to *D 51-85056 to *F Added Acronyms and Units of measure. Updated template and styles as per current Cypress standards. *H 4041855 06/27/2013 MEMJ Updated Functional Description. Updated Electrical Characteristics: Added one more Test Condition “IOH = –0.1 mA” for VOH parameter and added maximum value corresponding to that Test Condition. Added Note 4 and referred the same note in maximum value for VOH parameter corresponding to Test Condition “IOH = –0.1 mA”. Updated Package Diagrams: spec 51-85041 – Changed revision from *B to *C. Updated in new template. *I 4386284 05/21/2014 MEMJ Updated Package Diagrams: spec 51-85033 – Changed revision from *D to *E. spec 51-85056 – Changed revision from *F to *G. Completing Sunset Review. *J 4578447 01/16/2015 MEMJ Added related documentation hyperlink in page 1. Updated Figure 10 in Package Diagrams (spec 51-85041 *C to *D). Document Number: 38-05468 Rev. *J Description of Change Page 15 of 16 CY7C109D CY7C1009D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05468 Rev. *J Revised January 16, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16