QTP # 052805 :USB EMBEDDED HOST AUTOMOTIVE (CY7C67300) R52T-3 TECHNOLOGY, FAB4

Document No.001-88006 Rev. *A
ECN # 4416191
Cypress Semiconductor Automotive
Product Qualification Report
QTP# 052805 VERSION *A
June 2014
USB EMBEDDED HOST AUTOMOTIVE
R52T-3 TECHNOLOGY, FAB4
CY7C67300
EZ-Host™ Programmable Embedded
USB Host/Peripheral Controller
FOR ANY QUESTIONS ON THIS REPORT, PLEASE CONTACT
[email protected] or via a CYLINK CRM CASE
Prepared By:
Honesto Sintos
Reliability Engineer
Reviewed By:
Zhaomin Ji
Reliability Manager
Approved By:
Richard Oshiro
Reliability Director
Company Confidential
A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.
Page 1 of 9
Document No.001-88006 Rev. *A
ECN # 4416191
PRODUCT QUALIFICATION HISTORY
QUAL
REPORT
052805
DESCRIPTION OF QUALIFICATION PURPOSE
USB Embedded Host Automotive Technology, R52T-3, Fab 4
Company Confidential
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Page 2 of 9
DATE
COMP.
Mar 06
Document No.001-88006 Rev. *A
ECN # 4416191
PRODUCT DESCRIPTION (for qualification)
Qualification Purpose:
Qualify USB Embedded Host Automotive Technology, R52T-3, Fab 4
Marketing Part #:
CY7C67300
Device Description:
EZ-Host ™ Programmable Embedded USB Host/Peripheral Controller
Cypress Division:
Cypress Semiconductor Corporation – Consumer and Computation Division
Overall Die (or Mask) REV Level (pre-requisite for qualification):
What ID markings on Die:
Rev. A
7C67300A
TECHNOLOGY/FAB PROCESS DESCRIPTION
Number of Metal Layers:
3
Metal Composition:
Metal 1: 500Å TiW / 6000Å Al / 300Å TiW
Metal 2: 500Å TiW / 6000Å Al / 300Å TiW
Metal 3: 500Å Ti / 8000Å Al / 300Å TiW
Passivation Type and Materials:
1000Å SiO2 / 9000Å Si3N4
Free Phosphorus contents in top glass layer (%):
0%
Number of Transistors in Device
2,805,388
Number of Logic Gates in Device
76K
Generic Process Technology/Design Rule (µ-drawn):
CMOS, Triple Metal, 0.25 um
Gate Oxide Material/Thickness (MOS):
SiO2, 55Å
Name/Location of Die Fab (prime) Facility:
Cypress Semiconductor - Bloomington, MN
Die Fab Line ID/Wafer Process ID:
Fab4/R52T-3
PACKAGE AVAILABILITY
ASSEMBLY FACILITY SITE
PACKAGE
100-Lead TQFP
CML-RA,CHINA-JT
Note: Package Qualification details available upon request.
Company Confidential
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Page 3 of 9
Document No.001-88006 Rev. *A
ECN # 4416191
MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION
Package Designation:
AZ100
Package Outline, Type, or Name:
100-Pin Thin Quad Flat Pack (TQFP)
Mold Compound Name/Manufacturer:
Hitachi CEL9200HF9
Mold Compound Flammability Rating:
V-O per UL94
Oxygen Rating Index:
>28%
Lead Frame Material:
Copper
Lead Finish, Composition / Thickness:
Ni-Pd-Au
Die Backside Preparation Method/Metallization:
Backgrind
Die Separation Method:
Wafer Saw
Die Attach Supplier:
Dexter
Die Attach Material:
QMI 509
Die Attach Method:
Epoxy
Wire Bond Method:
Thermosonic
Wire Material/Size:
Au, 1.0mil
Thermal Resistance Theta JA °C/W:
47.47
Package Cross Section Yes/No:
N/A
Name/Location of Assembly (prime) facility:
CML-R
ELECTRICAL TEST / FINISH DESCRIPTION
Test Location:
CML-RA,KYEC, Taiwan
Fault Coverage:
100%
Note: Please contact a Cypress Representative for other packages availability
Company Confidential
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Page 4 of 9
Document No.001-88006 Rev. *A
ECN # 4416191
RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENTS
Stress/Test
Test Condition
(Temp/Bias)
High Temperature Operating Life
Early Failure Rate
High Temperature Operating
Latent Failure Rate
High Accelerated Saturation Test
(HAST)
Result
P/F
Dynamic Operating Condition, Vcc Max = 3.8V, 150°C
P
Dynamic Operating Condition, Vcc Max= 3.8V, 150°C
P
130°C, 3.63V, 85%RH
Precondition: JESD22 Moisture Sensitivity MSL 3
P
192 Hrs, 30°C/60%RH+3IR-Reflow, 260°C+0, -5°C
MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C
Temperature Cycle
Precondition: JESD22 Moisture Sensitivity MSL 3
P
192 Hrs, 30°C/60%RH+3IR-Reflow, 260°C+0, -5°C
121°C, 100%RH
Pressure Cooker
Precondition: JESD22 Moisture Sensitivity MSL 3
P
192 Hrs, 30°C/60%RH+3IR-Reflow, 260°C+0, -5°C
High Temperature Storage
150°C ± 5°C No bias
Electrostatic Discharge
Human Body Model (ESD-HBM)
500V/1000V/1500V/2,000V JESD22, Method A114-B
Electrostatic Discharge
Charge Device Model (ESD-CDM)
250V/500V/750V (Corner Pins)
P
P
P
Ball Shear
AEC-Q100-010
P
Bond Pull
Mil-Std 883, Method 2011
P
Electrical Distribution
AEC-Q100-009
P
Electro Thermal Gate Leakage
AEC-Q100-009
P
External Visual
JESD22-B100
P
Physical Dimensions
JESD22B100 AND B108
P
Solderability
JESD22-B102
P
Static Latchup
125C, 5.4V, ± 100mA
AEC-Q100-004
P
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Page 5 of 9
Document No.001-88006 Rev. *A
ECN # 4416191
RELIABILITY FAILURE RATE SUMMARY
Stress/Test
Device Tested/
Device Hours
#
Fails
Activation
Energy
Thermal
AF3
Failure Rate
High Temperature Operating Life
Early Failure Rate
2,610 Devices
0
N/A
N/A
0 PPM
High Temperature Operating Life1,2
Long Term Failure Rate
49,000 HRs
0
0.7
170
FIT**
** Insufficient samples to calculate FIT Rate.
1
2
3
Assuming an ambient temperature of 55°C and a junction temperature rise of 15 °C.
Chi-squared 60% estimations used to calculate the failure rate.
Thermal Acceleration Factor is calculated from the Arrhenius equation
E  1 1  
AF = exp  A  -  
 k  T 2 T1  
where:
EA =The Activation Energy of the defect mechanism.
K = Boltzmann's constant = 8.62x10-5 eV/Kelvin.
T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use
conditions.
Company Confidential
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Page 6 of 9
Document No.001-88006 Rev. *A
ECN # 4416191
Reliability Test Data
QTP #: 052805
Device
Fab Lot #
Assy Lot # Assy Loc Duration
Samp
Rej
Failure Mechanism
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 3.8V, Vcc Core
CY7C67300 (7C67300A)
4450615
610521772
CML-R
24
893
0
CY7C67300 (7C67300A)
4430113
610455932
CML-R
24
864
0
CY7C67300 (7C67300A)
4511259
610530861
CML-R
24
853
0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 3.8V, Vcc Core
CY7C67300 (7C67300A)
4450615
610521772
CML-R
408
49
0
CY7C67300 (7C67300A)
4450615
610521772
CML-R
1000
49
0
610521772
CML-R
COMP
3
0
610521772
CML-R
COMP
3
0
COMP
6
0
COMP
3
0
COMP
3
0
COMP
3
0
CML-R
COMP
3
0
STRESS: ESD-CHARGE DEVICE MODEL, 250V
CY7C67300 (7C67300A)
4450615
STRESS: ESD-CHARGE DEVICE MODEL, 500V
CY7C67300 (7C67300A)
4450615
STRESS: ESD-CHARGE DEVICE MODEL, 750V, corner pins only
CY7C67300 (7C67300A)
4450615
610521772
CML-R
STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22-A114-B, 500V
CY7C67300 (7C67300A)
4450615
610521772
CML-R
STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22-A114-B, 1,000V
CY7C67300 (7C67300A)
4450615
610521772
CML-R
STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22-A114-B, 1,500V
CY7C67300 (7C67300A)
4450615
610521772
CML-R
STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22-A114-B, 2,000V
CY7C67300 (7C67300A)
4450615
610521772
STRESS: STATIC LATCH-UP TESTING, 125C, 5.4V, +/100mA
CY7C67300 (7C67300A)
4450615
610521772
CML-R
COMP
6
0
4450615
610521772
CML-R
COMP
5
0
4450615
610521772
CML-R
COMP
5
0
CML-R
COMP
5
0
STRESS: BALL SHEAR
CY7C67300 (7C67300A)
STRESS: BOND PULL
CY7C67300 (7C67300A)
STRESS: POST BOND PULL AFTER TEMP CYCLE
CY7C67300 (7C67300A)
4450615
610521772
Company Confidential
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Page 7 of 9
Document No.001-88006 Rev. *A
ECN # 4416191
Reliability Test Data
QTP #: 052805
Device
Fab Lot #
Assy Lot # Assy Loc Duration
Samp
Rej
CY7C67300 (7C67300A)
4450615
610521772
CML-R
COMP
1193
0
CY7C67300 (7C67300A)
4430113
610455932
CML-R
COMP
919
0
CY7C67300 (7C67300A)
4511259
610530861
CML-R
COMP
908
0
Failure Mechanism
STRESS: EXTERNAL VISUAL
STRESS: ELECTRICAL DISTRIBUTION
CY7C67300 (7C67300A)
4450615
610521772
CML-R
COMP
30
0
CY7C67300 (7C67300A)
4430113
610455932
CML-R
COMP
30
0
CY7C67300 (7C67300A)
4511259
610530861
CML-R
COMP
30
0
STRESS: ELECTRO THERMAL GATE LEAKAGE
CY7C67300 (7C67300A)
4450615
610521772
CML-R
COMP
6
0
CY7C67300 (7C67300A)
4450615
610521772
CML-R
COMP
10
0
CY7C67300 (7C67300A)
4430113
610455932
CML-R
COMP
10
0
CY7C67300 (7C67300A)
4511259
610530861
CML-R
COMP
10
0
CML-R
1000
50
0
STRESS: PHYSICAL DIMENSION
STRESS: HIGH TEMPERATURE STORAGE, PLASTIC, 150C
CY7C67300 (7C67300A)
4450615
610521772
STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRE COND 192 HR 30C/60%RH, MSL3
CY7C67300 (7C67300A)
4450615
610521772
CML-R
96
50
0
CY7C67300 (7C67300A)
4450615
610521772
CML-R
168
50
0
STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 3.63V, PRE COND 192 HR 30C/60%RH, MSL3
CY7C67300 (7C67300A)
4450615
610521772
CML-R
96
45
0
CY7C67300 (7C67300A)
4450615
610521772
CML-R
128
44
0
STRESS: TC COND. C -65C TO 150C, PRE COND 192 HRS 30C/60%RH, MSL3
CY7C67300 (7C67300A)
4450615
610521772
CML-R
500
55
0
CY7C67300 (7C67300A)
4450615
610521772
CML-R
1000
50
0
CY7C67300 (7C67300A)
4450615
610521772
CML-R
COMP
15
0
CY7C67300 (7C67300A)
4430113
610455932
CML-R
COMP
15
0
CY7C67300 (7C67300A)
4511259
610530861
CML-R
COMP
15
0
STRESS: SOLDERABILITY
Company Confidential
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Page 8 of 9
Document No.001-88006 Rev. *A
ECN # 4416191
Document History Page
Document Title:
QTP # 052805 : USB EMBEDDED HOST AUTOMOTIVE (CY7C67300) R52T-3
TECHNOLOGY, FAB4
Document Number:
001-88006
Rev. ECN
Orig. of
No.
Change
**
4033621 ILZ
*A
4416191 HSTO
Description of Change
Initial Spec Release
Qualification report published on Cypress.com is documented on
memo HGA-113 and not in spec format.
Initiated spec for QTP 052805 and all data from memo# HGA-113
was transferred to qualification report spec template.
Deleted package qualification details on package qualification history
table.
Deleted Cypress reference Spec and replaced with Industry Standards
Updated package availability based on current qualified test &
assembly site.
Align qualification report based on the new template in the front page
Distribution: WEB
Posting:
None
Company Confidential
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Page 9 of 9