Features • • • • • • • • • • 1024 x 1024 Pixels with Memory Zone Up to 30 Images/Second Built-in Antiblooming Device Providing an Electric Shutter Function Pixel: 14 µm x 14 µm Image Zone: 14.34 x 14.34 mm2 Two Outputs at 20 MHz Each Readout Through 1 or 2 Outputs Possible Binning 2 x 2 Optical Shield Against Parasitic Reflexions and Stray Light A/R Window in 400 - 700 nm Bandwidth Description The TH7888A is particularly designed for high data rate applications (up to 30 pictures/second in 1024 x 1024 progressive scan format) in the medical and industrial fields. This area array image sensor consists of a 1024 x 1024 pixels (14 µm x 14 µm) image zone associated with a memory zone (masked with an optical shield). To increase the data rate, two separate outputs are provided, which can be used for parallel readout (the readout frequency is up to 20 MHz/output, leading to a total readout frequency of 40 MHz). These two outputs allow three readout modes (single or dual port). The TH7888A is designed with an antiblooming structure which provides an electronic shutter capability. Moreover, the 2 x 2 binning mode is available on this sensor, providing an image size of 512 x 512 pixels with 28 µm x 28 µm pixels. The TH7888A package is sealed with a specific anti-reflective window optimized in the 400 - 700 nm spectrum bandwidth on the sealed version. Area Array CCD Image Sensor (1024 x 1024 Pixels with Antiblooming) TH7888A Rev. 1999A–IMAGE–09/03 1 Figure 1. TH7888A General Sensor Organization ΦP1,2,3,4 ΦM1,2,3,4 ΦA VA 1024 x 1024 Image Area 1024 x 1024 Memory Area ΦM VDR VDR ΦR ΦR VDD1 VDD2 VOS1 VOS2 VS1 VS2 Bi-directional Serial Register VGS Functional Overview ΦL1-6 VGS Extra dark lines are provided for use as dark references or for smearing digital correction. Extra dark pixels are provided for dark line reference clamping. Each frame consists of 1056 video lines: • 1 dummy line • 12 useful dark reference lines (with optical shield) • 3 isolation lines • 1024 useful lines • 3 isolation lines • 12 dark reference lines (with optical shield) • 1 dummy line Each video line is made up of 546 or 1058 elements, depending on the readout mode (single or dual port mode): 2 • 12 inactive prescan elements • 1 isolation prescan element • 16 useful dark references (with optical shield) • 5 isolation elements • 512 or 1024 useful video pixels TH7888A 1999A–IMAGE–09/03 TH7888A Pin Description Figure 2. Pin Overview AA ΦP4 ΦP2 VSS VA ΦM4 ΦM2 VSS NC NC NC ΦP3 ΦP1 VSS ΦA ΦM3 ΦM1 ΦM NC NC NC Y B VS1 VOS2 VS2 VDP VSS VSS ΦR ΦL4 ΦL1 ΦL5 A VOS1VDD1VDD2 VDR VGS VSS VSS ΦL3 ΦL2 ΦL6 10 9 8 7 6 5 Top View 4 3 2 1 A1 Index Table 1. Pin Description Pin Number Symbol Designation Y9 ΦP1 AA9 ΦP2 Y10 ΦP3 AA10 ΦP4 Y5 ΦM1 AA5 ΦM2 Y6 ΦM3 AA6 ΦM4 Y4 ΦM B2 ΦL1 A2 ΦL2 A3 ΦL3 B3 ΦL4 B1 ΦL5 A1 ΦL6 A9 VDD1 A8 VDD2 B10 VS1 B8 VS2 B7 VDP Protection drain bias A6 VGS Register output gate bias A10 VOS1 B9 VOS2 B4 ΦR Image zone clocks Memory zone clocks Memory to register clock Readout register clocks Output amplifier drain supply Output amplifier source supply Video outputs Reset clock 3 1999A–IMAGE–09/03 Table 1. Pin Description (Continued) Pin Number Symbol Designation Y7 ΦA Antiblooming gate clock A7 VDR Reset bias AA7 VA Antiblooming diode bias A4, A5, B5, B6 VSS Y8, AA4, AA8 VSS Substrate bias Geometrical Characteristics Figure 3. Pixel Layout ΦA VA ΦA ΦA ΦA VA A Φ P1 ΦP2 14 µm ΦP3 ΦP4 ΦP1 A' Aperture 10 µm 14 µm Figure 4. AA Cross Section ΦP1 ΦP2 ΦP3 ΦP4 ΦP1 14 µm Transfer Direction Potential Profile During Integration Time 4 Signal Charge for One Pixel TH7888A 1999A–IMAGE–09/03 TH7888A Absolute Maximum Ratings* Storage Temperature ..................................... -55°C to +150°C Operating Temperature.................................... -40°C to +85°C Thermal Cycling..........................................................15°C/mn Maximum Applied Voltages: • Pins: Y9, AA9, Y10, AA10, Y5, AA5, Y6, AA6, Y4, B2, A2, A3, B3, B1, A1, B4, A6 ...........-0.3 V to 15 V *NOTICE: *Stresses above those listed under absolute maximum ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Operating range defines the limits within which functionality is guaranteed. Electrical limits of applied signals are given in the operating conditions section. • Pins: A9, A8, B10, B8, B7, A7, AA7 ..............-0.3 V to 15.5 V • Pin: Y7..............................................................-0.3 V to 12 V • Pins: A4, A5, B5, B6, Y8, AA4, AA8................... 0 V (ground) Operating Precautions Shorting the video outputs to any pin, even temporarily, can permanently damage the on-chip output amplifier. 5 1999A–IMAGE–09/03 Operating Conditions Table 2. DC Characteristics Value Parameter Symbol Min Typ Max Unit VDD1, VDD2 14.5 15 15.5 V Protection drain bias VDP 14.5 15 15.5 V Reset bias VDR 14.5 15 15.5 V Antiblooming diode bias VA 14.5 15 15.5 V Register output gate bias VGS 2.2 2.5 2.8 V Output amplifier drain supply VS1(2), VS2 Output amplifier source supply Ground Notes: (1) (2) VSS 0 V 0 V 1. Ground: note that the package metal back is grounded. 2. In dynamic mode, to avoid possible damage to the device, the addition of a Schottky diode is recommended (for example; diode reference BAR 43S) between VS1 and VSS ground in order to increase the potential on VS1, thus avoiding any direct mode diode current during clock transitions. Readout Mode The serial readout register is operated in a two-phase transfer mode. However, there are 6 separate command electrodes that should be connected differently, depending on the required readout mode. The following table gives the connections to be made for each mode. Table 3. Readout Modes Readout Modes 1 Output, VOS 1 1 Output, VOS2 (Mirror Effect) 2 Outputs (Parallel) ΦL1 Pins B2, B3, B1 Pins B2, A3, A1 Pins B2, B3, A1 ΦL2 Pins A2, A3, A1 Pins A2, B3, B1 Pins A2, A3, B1 Symbol Comments Vertical transfer period TV Nominal value = 800 nm Vertical transfer subdivision TO Tv = 8 x To Rise time tr Fall time tf For vertical transfer clocks (between 10% and 90% of the transition time) Readout register clock transition time t1 Reset clock transition time t2 Delay between output reset signal and reset clock td Drive Clocks (Signals) Table 4. Timing Parameters Definition 6 TH7888A 1999A–IMAGE–09/03 TH7888A Timing Diagrams The following diagrams describe the 20 MHz readout frequency and 1.25 MHz vertical transfer frequency. Figure 5. Frame Timing Diagram Integration Image # i + 1 Image Readout Memory Cleaning Period Fast Image to Memory Transfer ΦA Φ P1 Φ P2 Φ P3 Φ P4 1 2 1056 Pulses 1056 Φ M = Φ M1 Φ M2 Φ M3 Φ M4 1 1056 2 Φ L1 Φ L2 ΦR See Figure 6 See Figure 7 Figure 6. Line Timing Diagram 7To Φ M = Φ M1 5To Φ M2 5To 3To Φ M3 3To 3To Φ M4 See Figure 9 100 ns Min 3To 100 ns Min Φ L1 Φ L2 ΦR Vos1 (Vos2) 1 Note 1 Notes: 1058 (or 546) Min 12 13 Note 2 Note 3 1 12 Note 1 1. 12 pre-scan elements 2. 1 isolation element, 16 dark reference pixels, 5 isolation elements 3. 1024 useful video pixels (single output readout mode), 512 useful video pixels (dual output readout mode) 7 1999A–IMAGE–09/03 Figure 7. Vertical Transfer During Image to Memory Zone Transfer 20 ns < Tf < To 100 ns Min 100 ns Min 20 ns < Tr < To ΦA 1 2 1056 ΦP1 ΦP2 ΦP3 ΦP4 ΦM1 = ΦM2 ΦM2 ΦM3 ΦM4 See Figure 8 Figure 8. Transfer Period from Image Zone to Memory Zone (ΦP and ΦM for 1.25 Vertical Transfer Frequency FV = 1: Tv) Tv = 800 ns ΦP1 = ΦM1 3 To tr 5 To tf 25 ns < Tr < To/3 25 ns < Tf < To/3 ΦP2 = ΦM2 5 To To = 100 ns ΦP3 = ΦM3 3 To 5 To ΦP4 = ΦM4 To = Tv /8 Note: 8 3 To Tr = Rise time Tf = Fall time To = Vertical transfer time subdivision Tv = Vertical transfer period. TH7888A 1999A–IMAGE–09/03 TH7888A Figure 9. Output Diagram for Readout Register and Reset Clock 20 MHz Applications Crossover of Complementary Clocks (ΦL1, ΦL2). Between 30% and 70% of Maximum Amplitude. 50 ns 16 ns Min 16 ns Min ΦL1 t1 t1 ΦL2 12 ns Min ΦR t2 t2 td VOS (1,2) Signal Level Note: td Reset Feedthrough t1 = 7 ns typical t2 = 5 ns typical td = 8 ns typical delay time 9 1999A–IMAGE–09/03 Binning Mode Operation In binning mode operation, the image is composed of 512 x 512 pixels (28 µm x 28 µm each). Figure 10. Summation in the Readout Register of Two Adjacent Lines 15 T0 3 T0 5 T0 Φ M1 5 T0 5 T0 Φ M2 Φ M3 3 T0 Φ M4 5 T0 5 T0 3 T0 3 T0 3 T0 3 T0 5 T0 3 T0 Φ M = Φ M1 100 ns Min 100 ns Min Φ L1 Φ L2 Note: To view fall and rise times see Figure 8 on page 8 Figure 11. Summation of Two Adjacent Pixels Φ L1 Φ L2 Output Reset Frequency Divided by 2 ΦR VOS (1,2) Pixel i Useful Signal Pixel i + pixel i+1 10 TH7888A 1999A–IMAGE–09/03 TH7888A Exposure Time Reduction The TH7888A provides an exposure time control (electronic shutter) function. The exposure time reduction is achieved by pulsing all the ΦPi gates to 0 V to continuously remove all the photogenerated electrons through antiblooming drain VA. Figure 12. Timing Diagram for Electronic Shutter Frame Period 2 µs ΦA Φ P1 1 µs Φ P2 Φ P3 Φ P4 Transfer Note: Obturation Integration To view fall and rise times see Figure 6 on page 7 11 1999A–IMAGE–09/03 Table 5. Drive Clock Characteristics Value Parameter Symbol Image zone clocks High level Low level ΦP1, 1, 3, 4 Memory zone clocks High level Low level ΦM1, 2, 3, 4 Memory register clocks High level Low level ΦM Antiblooming gate High level (integration) Low level (transfer) ΦA Reset gate High level Low level ΦR Readout register clocks High level Low level Min Typ Max Unit Remarks 7.5 0 8 0.5 8.5 0.8 V V Typical input capacitance 15 nF See Figure 12 7.5 0 8 0.5 8.5 0.8 V V Typical input capacitance 15.5 nF See Figure 12 8.5 0 9 0.5 9.5 0.8 V V 3 0 4 0.5 7 0.8 V V 10 0 12 2 13 3 V V 8.5 0 9 0.5 9.5 0.8 V V Typical input capacitance 10 pF Typical input capacitance 14 nF See Figure 12 and Figure 14 Typical input capacitance 10 pF ΦL1, 2 Φ1L 8 pF 40 pF Maximum readout register frequency FH 20 – – MHz Maximum image zone to memory zone Transfer frequency FV 1.7 – – MHz 12 Φ2L 40 pF See Figure 9 See Figure 14 TH7888A 1999A–IMAGE–09/03 TH7888A Figure 13. Drive Clocks Capacitance Network ΦP2 ΦP2 3.3 nF 2.3 nF ΦA ΦP1 0.7 nF 2.3 nF 0.5 nF VA ΦP1 ΦP3 0.5 nF ΦP3 2.8 nF 3.3 nF 0.7 nF Substrate ΦP4 ΦP4 ΦP1 3.4 nF ΦP2 4.4 nF 4.4 nF 2.2 nF 4.4 nF 2.2 nF 4.4 nF 3.4 nF ΦP4 ΦM1 3.9 nF ΦP3 4.4 nF ΦM2 4.4 nF 3.2 nF 4.4 nF 3.2 nF 4.4 nF 3.9 nF ΦM4 ΦM3 Table 6. Static and Dynamic Electrical Characteristics Value Parameter Symbol Output amplifier supply current IDD Output impedance ZS DC output level VREF Output conversion factor CVF Min 200 Typ Max Unit Remarks 10 15 mA per amplifier 225 250 Ω 11 5.5 6 V 6.5 µV/e- 13 1999A–IMAGE–09/03 Electro-optical Performance • General conditions: Temp = 25°C (package temperature) Light source: 2854 K with 2 mm BG38 filter (unless specified) + F/3.5 optical aperture. 30 images per second mode (Ti = 33 ms) under typical operating conditions • Readout mode: 2 outputs • Values exclude dummy elements and blemishes Table 7. Performance Description and Values Value Parameter Symbol Min Typ Max Unit Output register saturation level VSAT reg – 2.6 – V Pixel saturation level VSAT 1.6 1.9 3 V Pixel saturation charge (electron per pixel) QSAT – 320 – ke- Responsivity at 640 nm Responsivity with BG38 filter R – 3 6.5 4 – – V/(µJ/cm2) V/(µJ/cm2) Quantum efficiency at 640 nm QE – 15 – % Photo response non uniformity (1σ) PRNU – 0.4 1.7 %Vos Dark signal non uniformity (1σ) DSNU – 0.28 0.4 mV (2) VDS – 2 3 mV (3) – 4 5.6 mV (4) Average dark signal Remarks (1) See Figure 17 Temporal RMS noise in darkness (last line) VN – 200 – µV (5) Dynamic range D – 80 – dB (6) Horizontal modulation transfer function at 500 nm MTF – 70 – % (7) Vertical charge transfer inefficiency (per stage) VCTI – – 2.5.10-5 – (8) Horizontal charge transfer inefficiency (per stage) HCTI – – 5.10-5 – (9) Notes: 14 1. Pixel saturation (full well) as a function of vertical transfer frequency (see Figure 14 on page 15) and antiblooming adjustment (see Figure 15 on page 15). 2. After substraction of dark signal slope due to memory readout time. 3. First line level referenced from inactive prescan elements (12 samples). 4. Last line level referenced from inactive prescan elements (12 samples). 5. Measured with Correlated Double Sampling (CDS) including 160 µV readout noise and dark current noise in general test conditions. 6. Saturation to RMS noise in darkness ratio. 7. At Nyquist frequency. 8. VSAT/2 measurement and 417 kHz vertical transfer frequency. 9. VSAT/2 measurement and 10 MHz horizontal transfer frequency. TH7888A 1999A–IMAGE–09/03 TH7888A Figure 14. Saturation Level by Full Well with Antiblooming Off (ΦA High = 0 V) Versus the Vertical Transfer Frequency Saturation Voltage (V) 2 1.8 1.6 1.4 1.2 200 700 1200 1700 Vertical Transfer Frequency (kHz) Figure 15. Saturation Level Limitation by the Antiblooming Effect on the Pixel (Typical Operating Conditions) Efficient Antiblooming Output Saturation Voltage (V) Inefficient Antiblooming Inefficient Antiblooming ΦA High Level Clock (V) 15 1999A–IMAGE–09/03 Figure 16. Smearing Effect Smearing/Vsat(%) 50 40 30 100 x ESAT 20 10 10 x ESAT 0 2 0 6 4 8 10 % of Overilluminated Zone (Height) NESAT = number of times ESAT TV V SMEARING ----------------------------- = N ESAT × ------ × H TI V SAT with ESAT = VSAT/responsivity (typical illumination conditions) • Ti = integration time • Tv = image to memory transfer time Vertical Smearing Overillumination Smearing Level H a b Vsat a,b Signal Line 16 TH7888A 1999A–IMAGE–09/03 TH7888A Figure 17. Spectral Response with A/R Window (Typical Case) 10 8 Responsivity V/(µJ/cm²) 6 4 2 0 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 Wavelength (nm) Image Quality Grade Blemish Maximum area of 2 x 2 defective pixels. Clusters Less than 7 contiguous defects in a column. Columns More than 7 contiguous defects in a column. General Conditions Room Temperature ...........................................................25°C Frequency 30 images/s(under typical operating conditions) Considered image zone ........................................ 1024 x 1024 Light Source 2854K with BG38 filter + F/3.5 optical aperture At Vos = 0.7 Vsat Type White Black Blemishes/clusters α > 20% Vos |α| > 30% Vos Columns α > 10% Vos |α| > 10% Vos Blemishes/clusters α > 10 mV (*) Columns α > 5 mV (*) In Darkness (*) reference is Vo: average darkness signal 17 1999A–IMAGE–09/03 Number of Defects Total pixel numbers affected by blemishes and clusters .....100 Maximum number of clusters................................................10 Maximum number of columns.................................................5 α: amplitude of video signal of defect with respect to mean output voltage Vos Ordering Codes TH7888AVRHRB: sealed version TH7888AVRHN: unsealed version Figure 18. Ordering Information Key 1 2 3 4 5 6 7 8 9 10 11 TH788A Technological Variants Temperature Range V: -40°C to +85°C Package Families R: Pin Grid Array (PGA) Image Grade H: High 18 Customer Specification Quality Assurance Level Standard Screening Nothing B = Mechanical Mask Package Variants N: Non-sealed Window R: Anti-reflective Window TH7888A 1999A–IMAGE–09/03 TH7888A Package Outline Figure 19. Package Drawing for 40-lead PGA 26.50 ±0.3 52.0 ±0.6 0.3 ± 0.1 Pin No. = A1 Index 0,734 ± 0,1 6.90 ± 0.20 17.25 ± 0.20 2.31 ± 0.30 2.19 ± 0.25 8 Y Φ3.04+- 0.04 0.5 X Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. All values are in mm. Black alumina 40-lead PGA package Black optical mask (only on sealed version) 400 nm – 700 nm AR coated window (R < 1% per side). Only on sealed version Metal back, (CuW – copper tungsten) gold plated. Electrically grounded (VSS) Optical center First useful pixel (readout through Vos1) Mechanical reference Photosensitive area dimensions 14,392(X) x 14,358(Y) 19 1999A–IMAGE–09/03 Parameter Mechanical Distance Optical Distance Unit Ztop 2.82 ± 0.31 2.31 ± 0.30 mm Zbottom 1.68 ± 0.15 2.19 ± 0.25 mm 20 TH7888A 1999A–IMAGE–09/03 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131, USA TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131, USA TEL 1(408) 441-0311 FAX 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2003. All rights reserved. Atmel® is the registered trademark of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1999A–IMAGE–09/03 0M