DATA SHEET MOS INTEGRATED CIRCUIT µPD3725A 5000-BIT × 3 CCD COLOR LINEAR IMAGE SENSOR The µPD3725A is a high sensitivity 5000-bit × 3 CCD (Charge Coupled Device) color linear image sensor which changes optical images to electrical signal and has the function of color separation. The µPD3725A has 3 rows of 5000-bit photocell array and 6 rows of 2500-bit charge transferred register, so it is suitable for high resolution color image scanners and digital color copiers. FEATURES • Valid photocell : 5000-bit × 3 • Photocell's pitch : 14 µm • Line distance : 112 µm (8 lines) R(red) bit-G(green) bit, Gbit-B(blue)bit • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107lx•Hour) • Resolution : 16 dot/mm across the shorter side of a B4-size (257 × 364 mm) sheet • Drive clock level : CMOS output under 5 V operation • Data rate : 16 MHz MAX. • High speed scan : 320 µs/line • Power supply : +12 V CHANGED POINTS from the µPD3725D-01 • Pins 18 and 15, 17 and 14, 11 and 8, 12 and 9 are each connected inside of the device (refer to BLOCK DIAGRAM). • The specification of the total transfer efficiency (TTE) is improved from 92 % to 93.5 % (MIN.) (refer to ELECTRICAL CHARACTERISTICS). ORDERING INFORMATION Part Number Package µPD3725AD CCD linear image sensor 24-pin ceramic DIP (600 mil) The information in this document is subject to change without notice. Document No. S11324EJ1V0DS00 (1st edition) Date Published March 1996 P Printed in Japan © 1996 µPD3725A BLOCK DIAGRAM φ R2B φ 1A1 φ 2A1 VOD 20 5 18 17 4 22 24 2 2 Transfer gate CCD analog shift register 5 3 6 19 8 9 φ 2L φ 1L φ 1A4 φ 2A4 ........... GND 21 GND 16 φ TG1 15 φ 1A2 14 φ 2A2 13 φ TG2 12 φ 2A3 11 φ 1A3 10 φ TG3 D133 D133 Photocell S4999 S5000 D128 ........... 7 D133 S4999 S5000 D128 ........... CCD analog shift register 6 Transfer gate (R) VOUT5 Photocell Transfer gate CCD analog shift register 3 1 D26 VOUT6 ........... D127 S1 S2 (G) VOUT3 ........... CCD analog shift register 4 Transfer gate D127 S1 S2 VOUT4 Photocell Transfer gate CCD analog shift register 1 23 D26 VOUT1 ........... S4999 S5000 D128 (B) D127 S1 S2 CCD analog shift register 2 Transfer gate D26 VOUT2 φ R1B µPD3725A PIN CONFIGURATIONS (Top View) CCD linear image sensor 24-pin ceramic DIP (600 mil) 24 VOUT4 Signal output 4 (GREEN) Signal output 6 (RED) VOUT6 2 23 VOUT1 Signal output 1 (BLUE) Signal output 5 (RED) VOUT5 3 22 VOUT2 Signal output 2 (BLUE) Output drain voltage VOD 4 21 GND Reset clock 2 φ R2B 5 20 φ R1B Reset clock 1 φ 2L 6 19 φ 1L Last-stage shift register clock 1 Ground GND 7 18 φ 1A1 Shift register clock 1 Shift register clock 1 φ 1A4 8 17 φ 2A1 Shift register clock 2 Shift register clock 2 φ 2A4 9 16 φ TG1 Transfer gate clock 1 Transfer gate clock 3 φ TG3 10 15 φ 1A2 Shift register clock 1 Shift register clock 1 φ 1A3 11 14 φ 2A2 Shift register clock 2 Shift register clock 2 φ 2A3 12 13 φ TG2 Transter gate clock 2 Ground 5000 B G 5000 5000 R Last-stage shift register clock 2 1 1 1 VOUT3 1 Signal output 3 (GREEN) PHOTOCELL STRUCTURE DIAGRAM 2 µm 14 µ m 12 µ m Channel stopper Aluminium electrode 3 µPD3725A ABSOLUTE MAXIMUM RATINGS (TA = +25 °C) Parameter Symbol Ratings Unit Output drain voltage VOD –0.3 to +15 V Shift register clock voltage Vφ1, Vφ2 –0.3 to +15 V Reset signal voltage VφR1B, VφR2B –0.3 to +15 V Transfer gate signal voltage VφTG –0.3 to +15 V Operating ambient temperature TA –25 to +60 °C Storage temperature Tstg –40 to +100 °C Caution Exposure to Absolute Maximum Rating for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. RECOMMENDED OPERATING CONDITIONS (TA = +25 °C) Parameter MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock signal high level Vφ1H, Vφ2H 4.5 5 5.5 V Shift register clock signal low level Vφ1L, Vφ2L –0.3 0 +0.5 V Reset signal high level VφR1BH, VφR2BH 4.5 5 5.5 V Reset signal low level VφR1BL, VφR2BL –0.3 0 +0.5 V Transfer gate signal high level VφTGH 4.5 5 5.5 V Transfer gate signal low level VφTGL –0.3 0 +0.5 V Data rate 2 × fφR1B, 2 × fφR2B – 2 16 MHz Remark φ1: φ1A1 to φ1A4, φ1L φ2: φ2A1 to φ2A4, φ2L 4 Symbol µPD3725A ELECTRICAL CHARACTERISTICS TA = +25 °C, VOD = 12 V, føR1B, fφR2B = 1 MHz, data rate = 2 MHz, storage time = 10 ms, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1 mm), input signal clock = 5 Vp-p Parameter Saturation voltage Saturation exposure Symbol Conditions Vsat MIN. TYP. MAX. Unit 1.0 1.3 – V SER 0.3 lx•s SEG 0.3 lx•s SEB 0.6 lx•s Photo response non-uniformity PRNU VOUT = 500 mV ±6 ±15 % Average dark signal ADS Light shielding 0.1 5 mV Dark signal non-uniformity DSNU Light shielding 0.5 +5 mV Power consumption PW 300 500 mW Output impedance ZO 0.5 1 kΩ Response –5 RR 2.71 3.87 5.03 V/lx•s RG 2.66 3.80 4.91 V/lx•s RB 1.45 2.07 2.70 V/lx•s 2 5 % Image lag IL VOUT = 500 mV Offset levelNote 1 VOS 4 6 8 V Output fall delay timeNote 2 td 33 40 47 ns Total transfer efficiency TTE fφR1B, fφR2B = 8 MHz, data rate = 16 MHz 93.5 98 Register imbalance RI VOUT = 500 mV 0.0 % 4.0 % Red response peak 630 nm Green response peak 540 nm Blue response peak 460 nm times Dynamic range DR Vsat/DSNU 2600 Reset feed through noise RFSN Light shielding 300 500 mV Notes 1. Refer to TIMING CHART 3, 5. 2. Each fall delay time of φ1L and φ2L (t11, t27 and t1, t37) is the TYP. value (refer to TIMING CHART 3, 5). 5 µPD3725A INPUT PIN CAPACITANCE Parameter Transfer gate pin capacitance Reset clock pin capacitance Last stage shift register clock pin capacitance Shift register clock pin capacitance A Shift register clock pin capacitance B 6 Symbol CφTG Cφ R Cφ L Cφ A Cφ B Pin name Pin No. φTG1 16 φTG2 13 φTG3 10 φR1B 20 φR2B 5 φ1L 19 φ2L 6 φ1A1 18 φ1A4 8 φ2A1 17 φ2A4 9 φ1A2 15 φ1A3 11 φ2A2 14 φ2A3 12 MIN. TYP. MAX. Unit 300 450 pF 50 80 pF 100 150 pF 250 380 pF 500 750 pF TIMING CHART 1 R, B φTG1, φ TG3 φTG2 G 0 1 2 3 D0 D2 D4 D8 13 60 61 62 63 64 65 66 φ1A1 to φ1A4, φ1L φ 2A1 to φ2A4, φ 2L φR1B φR2B D26 D122 D126 S1 S3 S5 VOUT1, 3, 5 D1 D3 D5 D25 D27 D123 D127 S2 S4 S6 VOUT2, 4, 6 Vacant transfer (26 bits) Optical black (96 bits) Invalid photocell (6 bits) Valid photocell (5000 bits) Caution Pins 18 (φ1A1) and 15 (φ1A2), 11 (φ1A3) and 8 (φ1A4) are each connected inside of the device, so do not input different timings to them. 7 µPD3725A And also pins 17 (φ2A1) and 14 (φ2A2), 12 (φ2A3) and 9 (φ2A4) are each connected inside of the device, so do not input different timings to them (refer to BLOCK DIAGRAM). 8 TIMING CHART 2 φ TG1, φ TG3 φTG2 φ1A1 to φ 1A4, φ 1L φ2A1 to φ2A4, φ 2L φR1B φR2B S4997 S4999 D128 D130 D132 VOUT1, 3, 5 S4996 S4998 S5000 D129 D131 D133 VOUT2, 4, 6 Invalid photocell (6 bits) µPD3725A µPD3725A fφR1B, fφR2B = 1 to 5 MHz) TIMING CHART 3 (Usual speed drive t10 t1 φ1L, φ 1A1 to φ1A4 t11 90% 10% t2 t6 φ 2L, φ 2A1 to φ 2A4 t12 t3 t4 t16 t5 φ R2B t13 t14 t15 φ R1B td 90% VOUT2, 4, 6 VOS 10% td VOUT1, 3, 5 VOS TIMING CHART 4 φ2L, φ2A1 to φ 2A4 90% 10% φ 1L, φ1A1 to φ1A4 φTG2 t7 t8 t9 t8 t7 t17 t18 t19 t18 t17 φTG1, φ TG3 9 µPD3725A Recommended Timing (Unit: ns) Symbol MIN. TYP. MAX. t1, t11 0 10 – t2, t12 0 50 – t3, t5, t13, t15 0 5 – t4, t14 20 50 – t6, t16 20 50 – t7, t17 20 50 – t8, t18 0 50 – t9, t19 1000 2000 – t10 100 500 – φ1A, φ 1A,φ2A φ 2Across cross points points φ1L, φ2A cross φ 1L, φ 2A crosspoints points φ 1A φ 2A 2 V or more 2 V or more 2 V or more φ 2A φ 1L φ1A, φ 2Lcross cross points points φ 1A,φ2L φ 1A 2 V or more φ 2L 0.5 V or more Remark 1. Adjust input resistance of each pin for cross points (φ1A, φ2A), (φ1L, φ2A) and (φ1A, φ2L) 2. φ1A: φ1A1 to φ1A4 φ2A: φ2A1 to φ2A4 10 0.5 V or more µPD3725A fφR1B, fφR2B = 5 to 8 MHz) TIMING CHART5 (High speed drive t30 t21 t31 90% φ1A1 to φ1A4 10% φ 2A1 to φ 2A4 t26 t27 φ 1L t36 t37 φ 2L t32 t33 φ R2B t34 t35 t22 t23 t24 t25 φ R1B td 90% VOUT2, 4, 6 VOS 10% td 90% VOUT1, 3, 5 VOS 10% 11 µPD3725A Recommended Timing (High speed drive fφR1B, fφR2B = 5 to 8 MHz) (Unit: ns) Symbol Caution MIN. TYP. MAX. t21, t31 0 10 — t22, t32 0 30 — t23, t25, t33, t35 0 5 — t24, t34 20 t30/2 — t26, t36 10 20 — t27, t37 0 10 — t30 60 100 — When driving µPD3725A according to timing shown in TIMING CHART 3 at high speed, period of signal output is shorten, therefore data may not be sampled normally. To sample data normally, drive µPD3725A according to timing shown in TIMING CHART 5. To extend the period of signal output, falling edge of last gate shift register clock φ1L, φ2L should be earlier than that of shift register clock φ1A, φ2A. When making the falling edge of φ1L, φ2L early, output signal is effected by noise from reset clock φR1B, φR2B. To avoid the effection of this noise, the falling edge of φR1B, φR2B should be set earlier. Driving at high speed, drive capability is necessary to be powered up. So design the peripheral circuit referring to peripheral circuit example 2. 12 µPD3725A DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time(s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The peak/bottom ratio to the average output voltage of all the valid bits calculated by the following formula. PRNU(%)= VMAX. or VMIN. –1 n 1 ∑ Vj n j=1 x 100 n: Number of valid bits Vj: Output voltage of each bit VMIN. Register Dark DC level 4. VMAX. 1 n n Vj j=1 S Average dark signal: ADS Output average voltage in light shielding ADS(mV) = 5. n 1 ∑ Vj n j=1 Dark signal non-uniformity: DSNU The difference between peak or bottom output voltage in light shielding and ADS. ADS Register Dark DC level DSNU MIN. DSNU MAX. 6. Output impedance: ZO Output pin impedance viewed from outside. 7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source. 13 µPD3725A 8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light OFF ON VOUT V1 VOUT IL = 9. V1 VOUT ×100 (%) Register Imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even bits, against the average output voltage of all the valid bits. 2 n RI = n 2 Σ (V 1 n 14 – V2j) 2j – 1 j=1 n ΣV j j=1 × 100 (%) µPD3725A STANDARD CHARACTERISTIC CURVES (TA = +25 °C) DARK OUTPUT TEMPERATURE CHARACTERISTICS 8 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTICS 2 4 Relative Output Voltage Relative Output Voltage 1 2 1 0.5 0.2 0.25 0.1 0.1 0 10 20 30 40 1 50 5 100 TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) B R 80 Response Ratio (%) 10 Storage Time (ms) Operating Ambient Temperature TA (°C) G 60 40 G 20 B 0 400 500 600 700 800 Wavelength (nm) 15 16 PERIPHERAL CIRCUIT EXAMPLE 1 +12 V B1 B2 B3 10 Ω φ R2B 47 Ω VOUT3 VOUT4 2 VOUT6 VOUT1 3 4 VOD GND 6 φ 2L 10 Ω GND 24 23 22 0.1 µ F B4 + _ 47 µ F/25 V B5 B6 21 φ R1B 20 47 Ω φ R1B 47 Ω φ 1L 19 φ1 φ 1A1 18 8 φ 1A4 φ 2A1 17 9 φ 2A4 φ TG1 16 B1 to B6 EQUIVALENT CIRCUIT +12 V 47 µ F/25 V 10 Ω 100 Ω 15 10 φ TG3 φ 1A2 11 φ 1A3 φ 2A2 14 12 φ 2A3 φ TG2 13 + _ CCD VOUT 10 Ω φ TG2 100 Ω 2 kΩ µPD3725A Remark Inverters: µ PD74HC04 VOUT2 5 φ R2B 7 φ TG1 VOUT5 µ PD3725AD φ2 + 47 µ F/25 V _ 47 Ω 1 PERIPHERAL CIRCUIT EXAMPLE 2 (For high speed drive) +12 V B1 B2 B3 10 Ω + 47 µ F/25 V _ 47 Ω φ R2B VOUT3 VOUT4 2 VOUT6 VOUT1 3 4 * VOD GND 6 φ 2L 10 Ω * VOUT2 GND 24 23 22 0.1 µ F B4 47 µ F/25 V B5 B6 47 Ω φ R1B 47 Ω φ 1L 19 φ1 φ 1A1 18 8 φ 1A4 φ 2A1 17 9 φ 2A4 φ TG1 16 10 Ω 15 10 φ TG3 φ 1A2 11 φ 1A3 φ 2A2 14 12 φ 2A3 φ TG2 13 * * 10 Ω 17 * inverter, use high speed inverter which has double driving capability of 74AC04 φ TG2 µPD3725A Remarks 1. Inverters: 74AC04 2. For + _ 21 φ R1B 20 5 φ R2B 7 φ TG1 VOUT5 µ PD3725AD 47 Ω φ2 1 µPD3725A PACKAGE DIMENSIONS (Unit: mm) CCD LINEAR IMAGE SENSOR 24PIN CERAMIC DIP (600 mil) (Unit : mm) 14.4 2.62 1bit 11.0±0.6 2 Connecting part 85.4±0.3 1.27±0.05 0.46±0.05 2.54 27.9 85.0±1.2 90.0±1.3 20.03±0.6 1 Pin 1 index 3.5±1.0 3 Connecting part 0.97±0.3 6.4±0.3 3.3±0.35 15.1±0.3 4.33 NOTE 1 pin 1 index and 2 , 3 connecting parts are made of silver wax and plated with gold. As they are electrically connected with GND, be sure not to touch with other wirings on the board. 2.0±0.3 (2.33) 15.24 0.25±0.05 Name Dimensions Refractive index Glass cap 89.0 × 13.6 × 1.0 1.5 24D-1CCD-PKG-2 18 µPD3725A RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Type of Through Hole Device µPD3725AD : CCD linear image sensor 24-pin ceramic DIP (600 mil) Process Conditions Wave soldering (only to leads) Solder temperature: 260 °C or below, Flow time: 10 seconds or less. Partial heating method Pin temperature: 260 °C or below, Heat time: 10 seconds or less (Per each lead). Caution For through hole devices, the wave soldering process must be applied only to leads, and make sure that the package body does not get jet soldered. 19 µPD3725A [MEMO] 20 µPD3725A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 21 µPD3725A [MEMO] The application circuits and their parameters are for references only and are not intended for use in actual design-in's. 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Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11