SDNS017C − FEBRUARY 1994 − REVISED DECEMBER 1995
D Recovers a 622.08-MHz Clock Signal From
D
D
a 622.08-Mbit /s STS-12/STM-4 NRZ Data
Stream
Accepts Pseudo-ECL (PECL) Input Voltage
Levels on the Input Data Stream
Requires a Single 5-V Supply
Provides PECL-Clock and PECL-Data
Outputs
VCC
VCC
NC
GND
DATAIN
DATAIN
GND
VCC
CAPOUTN
CAPOUTP
description
The TNETA1622 recovers an embedded clock
signal from a 622.08-Mbit /s STS-12/STM-4
nonreturn-to-zero (NRZ) data stream using a
frequency/phase-locked loop. The device
accepts PECL (ECL signals referenced to 5 V
instead of GND) input-voltage levels. The
recovered clock and data outputs are PECL
compatible. The serial data input and recovered
clock and data outputs are differential to provide
maximum noise immunity.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
GND
GND
DATAOUT
DATAOUT
VCC
VCC
CLKOUT
CLKOUT
GND
GND
NC − No internal connection
The TNETA1622 requires only a positive 5-V supply (5 V ± 5%) for operation. The TNETA1622 is characterized
for operation over a temperature range of − 40°C to 85°C.
functional block diagram
CAPOUTP CAPOUTN
DATAIN
DATAIN
Frequencyand-Phase
Detector
Transition
Detector
Charge
Pump/Loop
Filter
Voltage Controlled
Oscillator
Retiming
DATAOUT
DATAOUT
CLKOUT
CLKOUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
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•
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•
1
PRODUCT PREVIEW
D
DW PACKAGE
(TOP VIEW)
SDNS017C − FEBRUARY 1994 − REVISED DECEMBER 1995
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CAPOUTN
CAPOUTP
9
10
I
Capacitor connection for phase-locked-loop filter
CLKOUT
CLKOUT
13
14
O
Recovered clock output, PECL compatible
DATAIN
DATAIN
5
6
I
Serial data input, PECL compatible
DATAOUT
DATAOUT
17
18
O
Serial data output, PECL compatible
GND
4, 7, 11, 12,
19, 20
VCC
NC
1, 2, 8, 15, 16
3
Ground (0-V reference)
Supply voltage
No connection. Leave floating (open).
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
PRODUCT PREVIEW
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI, PECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 mW
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
recommended operating conditions
VCC
VIH
Supply voltage
High-level input voltage
PECL (see Note 2)
VIL
TA
Low-level input voltage
PECL (see Note 2)
Operating free-air temperature
MIN
NOM
4.75
5
VCC −1.15
VCC −1.90
− 40
MAX
UNIT
5.25
V
VCC −0.80
VCC −1.50
V
85
V
°C
NOTE 2: The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for
logic-level voltages only.
2
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•
SDNS017C − FEBRUARY 1994 − REVISED DECEMBER 1995
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted) (see Figure 1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
DATAOUT,
DATAOUT
VCC = 4.75 V to 5.25 V,
See Notes 2 and 3
VCC −1.03
VCC −0.85
V
VOL
Low-level output voltage
DATAOUT,
DATAOUT
VCC = 4.75 V to 5.25 V,
See Notes 2 and 3
VCC −1.85
VCC −1.62
V
VOH
High-level output voltage
CLKOUT,
CLKOUT
VCC = 5 V
VCC −1.0
V
VOL
Low-level output voltage
CLKOUT,
CLKOUT
VCC = 5 V
VCC −1.6
V
VO(PP)
Output voltage swing, PECL
CLKOUT,
CLKOUT
VCC = 4.75 V to 5.25 V,
See Note 3
IIH
High-level input current
DATAIN,
DATAIN
VCC = 5.25 V,
VI = 4.45 V
µA
IIL
Low-level input current
DATAIN,
DATAIN
VCC = 5.25 V,
VI = 3.35 V
µA
VCC = 5.25 V,
Outputs open
f = 622.08 Mbit/s,
VCC = 5.25 V,
See Note 4
f = 622.08 Mbit/s,
ICC
Supply current
400
mV
107
mA
107
NOTES: 2. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for
logic-level voltages only.
3. PECL outputs are terminated through a 50-Ω resistor to VCC − 2 V.
4. CLKOUT, CLKOUT, DATAOUT, and DATAOUT each are terminated with a 50-Ω resistor to VCC − 2 V.
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Acquisition time
See Note 5
ms
Deviation of clock-sampling point, tcsp
See Figure 1
ps
RMS jitter, recovered clock
See Note 6
ps
Peak-to-peak jitter, recovered clock
ps
Input data rate
622.08
Duty cycle, recovered clock
See Note 3
Maximum number of consecutive bits (1 or 0) in input data stream
See Note 7
NOTES: 3.
5.
6.
7.
45%
Mbit/s
55%
PECL outputs are terminated through a 50-Ω resistor to VCC − 2 V.
Acquisition time is the time required to achieve a valid clock output while applying a 27 − 1 pseudo-random bit sequence.
RMS jitter is measured with a 231 − 1 pseudo-random bit sequence.
This measurement is made with a 213 − 1 pseudo-random bit sequence with string substitution.
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3
PRODUCT PREVIEW
PARAMETER
SDNS017C − FEBRUARY 1994 − REVISED DECEMBER 1995
PARAMETER MEASUREMENT INFORMATION
VCC − 2 V
50 Ω
DATAIN
DATAIN
CAPOUTP
6
18
5
17
14
13
10
TNETA1622
50 Ω
50 Ω
50 Ω
DATAOUT
DATAOUT
CLKOUT
CLKOUT
9
CAPOUTN
LOAD CIRCUIT
DATAIN
PRODUCT PREVIEW
CLKOUT
50%
50%
50%
50%
tcsp
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
4
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