SCAS212 − D3447, MARCH 1990 − REVISED APRIL 1993 • • • • • • • • Inputs Are TTL-Voltage Compatible 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Asynchronous Clear Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C DW PACKAGE (TOP VIEW) 1CLK 1Q1 1Q2 1Q3 1Q4 GND GND GND GND 2Q1 2Q2 2Q3 2Q4 2CLK description 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 1OE 1CLR 1D1 1D2 1D3 1D4 VCC VCC 2D1 2D2 2D3 2D4 2CLR 2OE The 74ACT11874 contains dual 4-bit registers featuring 3-state outputs designed specifically for bus driving. This makes this device particularly suitable for implementing buffer registers, I/O ports, and working registers. The D-type edge-triggered flip-flops enter data on the low-to-high transition of the clock. The 74ACT11874 has CLR inputs and noninverting outputs. Taking CLR low causes the four Q outputs to go low independently of the clock. The 74ACT11874 is characterized for operation from − 40°C to 85°C. FUNCTION TABLE (each flip-flop) INPUTS OE D OUTPUT Q CLR CLK L L X X L L H ↑ H H L H ↑ L L L H L X Q0 H X X X Z EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 2−1 SCAS212 − D3447, MARCH 1990 − REVISED APRIL 1993 logic symbol† 1OE 1CLK 1CLR 1D1 1D2 1D3 1D4 2OE 2CLK 2CLR 2D1 2D2 2D3 2D4 28 1 27 23 22 logic diagram (each 4-bits) (positive logic) EN OE C1 CLK R 1D 1 2 3 21 4 20 5 15 14 16 20 19 CLR 1Q1 1Q2 R 1Q3 C1 1Q4 D1 1D R EN Q2 C1 C1 D2 R 1D Q1 1 10 11 18 12 17 13 1D 2Q1 R 2Q2 Q3 C1 2Q3 D3 2Q4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1D R Q4 C1 D4 1D absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2−2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • SCAS212 − D3447, MARCH 1990 − REVISED APRIL 1993 recommended operating conditions MIN MAX 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL Dt /Dv TA Operating free-air temperature High-level input voltage 2 UNIT V V 0.8 V VCC VCC V High-level output current −24 mA Low-level output current 24 mA 0 10 ns/ V − 40 85 °C Input transition rise or fall rate V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = − 50 mA VOH IOH = − 4 mA VCC MIN TA = 25°C TYP MAX MIN 3V 2.9 2.9 4.5 V 4.4 4.4 5.5 V 5.4 5.4 3V 2.58 2.48 4.5 V 3.94 3.8 IOH = − 24 mA 5.5 V 4.94 4.8 IOH = − 75 mA† 5.5 V MAX UNIT V 3.85 3V 0.1 0.1 4.5 V 0.1 0.1 5.5 V 0.1 0.1 3V 0.36 0.44 4.5 V 0.36 0.44 IOL = 24 mA 5.5 V 0.36 0.44 IOL = 75 mA† 5.5 V IOZ II VO = VCC or GND VI = VCC or GND 5.5 V ± 0.5 ±5 mA 5.5 V ± 0.1 ±1 mA ICC Ci VI = VCC or GND, VI = VCC or GND 5.5 V 8 80 mA IOL = 50 mA VOL IOL = 12 mA IO = 0 5V 1.65 4 Co VO = VCC or GND 5V 10 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • V pF pF 2−3 SCAS212 − D3447, MARCH 1990 − REVISED APRIL 1993 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) MIN fclock Clock frequency tw Pulse duration tsu Setup time before CLK↑ th Hold time after CLK↑ TA = 25°C TYP MAX MIN MAX UNIT 125 0 125 MHz 0 CLR low 2 4 CLK high or low 2 4 Data 1 5 CLR low 2 2 Data 2 1 ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX 125 CLK Any Q CLR Any Q OE Any Q OE Any Q MIN MAX 125 UNIT MHz 7.5 3.7 9.4 8.1 4.1 10.6 8.8 3.5 11.8 6.4 1.6 7.4 8.6 2.4 9.5 6.9 5.4 9.4 6.8 4.9 9.1 ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled Cpd 2−4 Power dissipation capacitance Outputs disabled • UNIT 76 CL = 50 pF, POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • TYP f = 1 MHz 64 pF SCAS212 − D3447, MARCH 1990 − REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH /tPHL tPLZ /tPZL tPHZ /tPZH Open 2 × VCC GND 500 Ω LOAD CIRCUIT 3V Timing Input (see Note B) 1.5 V 0V tw tsu 3V Input 1.5 V th 1.5 V 3V 1.5 V 1.5 V Data Input 0V 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) 3V Input (see Note B) 1.5 V 1.5 V 0V tPHL tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC 3V Output Waveform 2 S1 at GND (see Note C) VOH 50% VCC VOL 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 2 × VCC (see Note C) tPLH tPHL Out-of-Phase Output VOLTAGE WAVEFORMS 50% VCC 20% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS [ VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 2−5 SCAS212 − D3447, MARCH 1990 − REVISED APRIL 1993 2−6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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