ICs for Communication Equipment AN6591FJM Transmission / reception, single chip PLL IC for PHS, cordless telephone ■ Overview 3C 23 33 (6.00) 6.20±0.10 22 34 0.10 Seating plane 5.00±0.10 (1.10) 1 5.00±0.10 0.20±0.10 11 1 11 12 44 22 34 33 0.40 0.80 max. 12 44 R0.30 ■ Features • Transmission and reception PLL block on a single chip • Transmission block: A quadrature modulator, a phase shifter APC (auto power control) and an up-converter • Reception block: A down-mixer (to 300 MHz), an IF amplifier and an RSSI circuit • PLL block: PLLs for 1st and 2nd local oscillators. • 6 mm × 6 mm small package Unit: mm 0. 50 6.20±0.10 (6.00) (1.10) (0.48) AN6591FJM is a single chip IC optimum for PHS, and a quadrature modulator, reception IF and PLL are integrated in it. As this IC is housed in a QFN package (quad flat nonleaded PKG), realization of compact equipment through this super-small package is possible. 23 (0.48) 0.16±0.06 0.10 M QFN044-P-0606A (Lead-free package) ■ Applications • PHS, digital cordless telephone, etc. Publication date: October 2002 SDM00007BEB 1 AN6591FJM STROBE 34 IO 23-bit shift register 14-bit 1st R counter 36 1st charge pump VCC 37 1 000 pF VCO1 IO LPF2 300 kHz 1st phase comparator Lock detection 0Ω fRFIN 23 50 kHz 2nd R counter (384) 20 38 19 39 IO fIFIN 47 Ω φ Σ 15 1 kΩ I 100 pF 1 kΩ I 100 pF 42 14 IO 1 kΩ Q 100 pF 5 µF P0 VCO2 17 16 41 2 200 pF 4 700 pF 1 649.7 MHz to 1 686.3 MHz 560 Ω 560 Ω VCC1 VCC VCC1 40 Lo1 1 000 pF 18 2nd prescaler (1 / 16, 1 / 17) 1st N counter latch 100 pF 24 25 21 2nd N counter (291) A counter (7) 18-bit 1st A / N counter 1st prescaler 2nd phase comparator 0Ω 13 43 1 000 pF 100 pF 47 Ω 223.15 MHz 2 200 pF 100 pF 5 µF 47 Ω 330 Ω Lo3 2 200 pF Ceramic MIXO filter (Maker: Murata) 330 Ω 47 Ω VLI SDM00007BEB VCC2 22 nF VLM 12 11 10 9 8 7 6 5 2 200 pF 100 pF 22 nF 1 000 pF RSSI IO 4 3 2 1 IO VMI 1 kΩ Q 100 pF 44 2 22 2nd charge pump 1st R counter latch 35 LPF1 VCC 1 000 pF 26 PSIF 27 PSRF 28 30 31 LD 32 33 Data Clock 5 µF 29 LD Controller fREFIN ■ Application Circuit Example 0Ω 47 Ω 560 pF VS Lo2 223.15 MHz AN6591FJM ■ Pin Descriptions Pin No. Symbol 1 RXMXIN 2 RXLOIN 3 Description Pin No. Symbol Description RX mix. in 23 N.C. RX local in 24 N.C. VCC2 VCC mix. 25 N.C. 4 MXO Mix. out 26 VCC VCC 2nd CMOS 5 LMDEC1 Lim. decouple1 27 CP2 2nd charge pump out 6 LMIN Lim. in 28 PSIF 2nd power save in 7 LMDEC2 Lim. decouple2 29 PSRF 1st power save in 8 VCC2 VCC lim. 30 Ref. Reference in 9 LMO Lim. out 31 LD Lock detect out 10 TXLO2 TX local2 in 32 Clock Clock in 11 RSO RSSI out 33 Data Serial data in 12 GND GND 34 STROBE 13 Q-in Q-input 35 GND GND 1st / 2nd CMOS 14 Q-in Q-input 36 CP1 1st charge pump out 15 I-in I-input 37 VCC VCC 1st CMOS 16 I-in I-input 38 RFIN 1st prescaler in 17 VCC1 VCC TX mod. 39 TXLO1 18 GNDM GND TX mod. 40 TXLO1R TX local 1ref. 19 IFIN 2nd prescaler in 41 APC / BS APC / BS 20 N.C. 42 VCC1 VCC TX out 21 GND2 GND 2nd CMOS 43 TXO TX output 22 VCC VCC 1st 2nd BIP 44 GNDO Strobe in TX local 1 GND TX out ■ Absolute Maximum Ratings Parameter Supply voltage Symbol Rating Unit VCC VCC1 VCC2 3.5 V ICC 54 mA PD 194 mW Topr −20 to +70 °C Tstg −55 to +125 °C Supply current *2 Power dissipation *2 Operating ambient temperature Storage temperature *1 *1 Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. *2: The above power dissipation PD shows the power dissipation of the package without heat sink. Refer to "■ Technical Data" when mounting this IC to a PCB and check that the IC will operate within the package power dissipation range. ■ Recommended Operating Range Parameter Supply voltage Symbol Range Unit VCC , VCC1 , 2.7 to 3.3 V VCC2 SDM00007BEB 3 AN6591FJM ■ Electrical Characteristics at Ta = 25°C Parameter Symbol Test circuit Conditions Min Typ Max Unit Current consumption (reception) ICCRX 2 No signal input 5.3 6.8 mA Mix. conversion gain GMX 1 VMI = 70 dBµ Filter loss excluded. 13 16 19 dB Mix. max. output level VMX 1 VMI = 105 dBµ Filter loss excluded. 105 110 dBµ Lim. voltage gain GLM 1 VMI = 20 dBµ 63 68 73 dB Lim. max. output amplitude VLM 1 VLI = 80 dBµ 350 400 mV[p-p] RSSI output voltage (1) VS (1) 1 VLI: No signal input 0 0.2 0.5 V RSSI output voltage (2) VS (2) 1 VLI = 115 dBµ 1.60 1.80 V Change in RSSI output DS 1 VS (VIS) = VS(1) + 0.15 V DS (1) = VS (VIS + 65 dBµ) − VS (VIS) 1.0 1.25 1.5 V Gradient of RSSI output ∆DS(n) 1 ∆DS (n) = 5 (VS (VIS + n13 dBµ) − VS (VIS + (n − 1) 13 dBµ)) / DS (1) n = 1 to 5 0.75 1.0 1.25 Current consumption (transmission) ICCTX 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 672.5 MHz, −10 dBm VAPC = 2.75 V 28 37 mA Sleep current in transmission ISL 2 No signal input, VAPC = 0 V 0 10 µA Transmission output level 1 * P01 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 660 MHz, −10 dBm, VAPC = 2.2 V −13 −9 dBm Transmission output level 2 * P02 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 687 MHz, −10 dBm, VAPC = 2.2 V −13 −9 dBm Image leakage suppression IL1 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 672.5 MHz, −10 dBm VAPC = 2.75 V, I / Q: No level adjusted −35 −30 dBc fLO1 + fLO2 leakage suppression CL 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 672.5 MHz, −10 dBm VAPC = 2.75 V, I / Q: DC offset adjusted −35 −30 dBc Proximity spurious suppression DU 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 672.5 MHz, −10 dBm −55 −51 dBc Make VAPC adjustments so that the Po value will be −13 dBm. Note) 1. Unless otherwise specified, at reception: VCC2 = 3.0 V, VLO3 = −10 dBm, f = 233.15 MHz, VMI: f = 243.95 MHz, SW1 = a, VLI: f = 10.8 MHz (The input level of pin 6, except the signal attenuation at the matching circuit and filter circuit.) The VMO and VLO values are at high impedance. (VLM shall be measured at probe load conditions of 27 pF and 1 MΩ.) 2. The VIS is the input level VLI where the RSSI output voltage is VS (1) + 0.15 V. At transmission: VCC1 = 3.0 V, I / Q signal amplitude: 0.5 V[p-p] in both phases, DC bias: 1.5 V, SW1: a ICCTX , IL1, CL: π / 4 QPSK-modulated wave, P01, P02, DU: PN9-level-modulated wave I / Q signal input condition: Make an amplitude adjustment of π / 4 QPSK modulation signal 0000 to 0.5 V[p-p] with an oscilloscope and change the signal wave to a PN9-level continuous wave. Spectrum analyzer setting conditions for transmission output level measurement: SPAN = 2 MHz, RBW = 3 MHz, VBW = 3 MHz, SWPT = 5 s Det.: Pose. peak *: P01 output frequency: 1 893.15 MHz, P02 output frequency: 1 920.15 MHz 4 SDM00007BEB AN6591FJM ■ Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Test circuit Conditions Min Typ Max Unit 7.0 mA Current consumption 1 (PLL) ICC1 1 1st PLL and 2nd PLL blocks are simultaneously turned on. 3.7 5.4 Current consumption 2 (PLL) ICC2 1 1st PLL block is turned on while the 2nd PLL block is turned off. 3.0 4.4 5.7 mA Current consumption 3 (PLL) ICC3 1 1st PLL block is turned off while the 2nd PLL block is turned on. 1.2 1.7 2.2 mA Current consumption 4 (PLL) ICC4 1 Power save mode 0 10 µA 1st RF input level VRFIN 1 fRFIN = 1 500 MHz to 1 800 MHz −15 −2 dBm 2nd IF input level VIFIN 1 fIFIN = 120 MHz to 300 MHz −10 +6 dBm 1 fREFIN = 10 MHz to 25 MHz 0.2 1.2 V[p-p] Reference signal input level VREFIN Note) Unless otherwise specified, VCC is 3.0 V and reference signal input level VREFIN is 0.6 V[p-p] at fREFIN = 19.2 MHz. • Design reference data Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Test circuit Conditions Min Typ Max Unit CL1 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 672.5 MHz, −10 dBm VAPC = 2.75 V −25 −20 dBc 2nd local leakage suppression CL2 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 672.5 MHz, −10 dBm VAPC = 2.75 V −15 −10 dBc 1st local leakage suppression In-band output level deviation ∆P 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 660 MHz to 1 687 MHz, −10 dBm, VAPC = 2.2 V 1.0 dB Adjacent channel leakage power suppression (600 kHz detuning) BL1 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 672.5 MHz, −10 dBm VAPC = 2.75 V −60 dBc Modulation accuracy EVM 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 672.5 MHz, −10 dBm VAPC = 2.2 V 3 5 %[rms] Min. output level Pmin 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 672.5 MHz, −10 dBm VAPC = 1.0 V −30 −25 dBm IIL 1 Lo1 = 233.15 MHz, −10 dBm Lo2 = 1 672.5 MHz, −10 dBm VAPC = 2.75 V −36 dBc Rmix 2 No signal input 330 Ω RF + 233.15 MHz leakage suppression Mixer output resistance Note) Unless otherwise specified, VCC = VCC1 = VCC2 = 3.0 V I / Q signal: 0.5 V[p-p] in both phases, DC bias: 1.5 V CL1, CL2, ∆P, BL1, EVM, Pmin, IIL : PN9-level modulated wave. SDM00007BEB 5 AN6591FJM ■ Electrical Characteristics at Ta = 25°C (continued) • Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Test circuit Conditions Min Typ Max Unit High-level input voltage VIH 2 2.4 V Low-level input voltage VIL 2 0.6 V High-level output voltage VOH 2 2.4 V Low-level output voltage VOL 2 0.6 V High-level input current 1 IIH1 2 VIH of 3.0 V applied 0 10 µA Low-level input current 1 IIL1 2 VIL of 0 V applied 0 10 µA High-level input current 2 IIH2 2 VIH of 3.0 V applied 0 10 µA Low-level input current 2 IIL2 2 VIL of 0 V applied 0 10 µA High-level output current 1 / 2 (High power) IOH1H,2H 2 High power with VOH of 2.4 V applied. −3.2 −2.6 −1.9 mA Low-level output current 1 / 2 (High power) IOL1H,2H 2 High power with VOL of 0.6 V applied. 3.5 4.4 mA High-level output current 1 / 2 (Low power) IOH1L,2L 2 Low power with VOH of 2.4 V applied. − 0.74 − 0.6 − 0.46 mA Low-level output current 1 / 2 (Low power) IOL1L,2L 2 Low power with VOL of 0.6 V applied. 0.53 IOZ 2 VOZ of 0 V / 3.0 V applied High-level output current 3 IOH3L 2 Low-level output current 3 IOL3L Lockup time (1st) rockt1 Output leakage current 2.8 0.7 0.87 mA −1 0 1 µA VOH of 2.4 V applied −3.6 −2.6 −1.5 mA 2 VOL of 0.6 V applied 1.9 3.3 4.6 mA 1 1st PLL block and 2nd PLL block are simultaneously turned on for all chan- 600 µs nels with RX-to-TX and TX-to-RX burst. Lockup time (2nd) rockt2 1 1st PLL block and 2nd PLL block are simultaneously turned on intermittently (during PS triggering) 600 µs 1st spurious ±50 kHz Lspu1 1 1st PLL block and 2nd PLL block are simultaneously turned on. L-channel to H-channel −40 dBc 1st proximity C / N Lspu2 1 1st PLL block and 2nd PLL block are simultaneously turned on. df = 1 kHz, L-channel to H-channel −70 dBc / Hz 1st reference leakage Lspu3 1 1st PLL block and 2nd PLL block are simultaneously turned on. df = 600 kHz, BW192 kHz −67 dBc Note) Unless otherwise specified, VCC is 3.0 V and reference signal input level VREFIN is 0.6 V[p-p] at fREFIN of 19.2 MHz. 6 SDM00007BEB AN6591FJM ■ Electrical Characteristics at Ta = 25°C (continued) • Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Test circuit Conditions Min Typ Max Unit −40 dBc 2nd reference leakage ±50 kHz Lspu4 1 1st PLL block and 2nd PLL block are simultaneously turned on. RW 1 kHz, VW 1 kHz 2nd proximity C / N Lspu5 1 1st PLL block and 2nd PLL block are simultaneously turned on. df = 1 kHz −76 dBc / Hz Note) Unless otherwise specified, VCC is 3.0 V and reference signal input level VREFIN is 0.6 V[p-p] at fREFIN of 19.2 MHz. fREFIN 1. Test circuit 1 STROBE 34 IO 23-bit shift register 14-bit 1st R counter 36 1st charge pump VCC 37 IO 300 kHz 1st phase comparator 1 000 pF 0Ω fRFIN 23 24 25 2nd phase comparator 21 50 kHz 2nd R counter (384) 20 2nd N counter (291) A counter (7) 19 18 2nd prescaler (1 / 16, 1 / 17) 39 IO fIFIN MHz fout2 (Lo2, Lo3) 17 47 Ω 16 1 kΩ I 100 pF φ Σ 41 2 200 pF 4 700 pF 1 651.2 MHz to 1 684.8 MHz 560 Ω 560 Ω 15 1 kΩ I 100 pF 42 14 IO 1 kΩ Q 100 pF 5 µF 13 43 1 000 pF 44 100 pF 47 Ω 223.15 MHz 2 200 pF 100 pF 5 µF 47 Ω 330 Ω Lo3 2 200 pF Ceramic MIXO filter (Maker: Murata) 330 Ω 47 Ω VCC2 Q 22 nF VLM 12 11 10 9 8 7 6 5 2 200 pF 100 pF 22 nF 1 000 pF RSSI IO 4 3 2 IO VMI 1 kΩ 100 pF 1 P0 VCO2 VCC1 40 VAPC/BS VCC1 VCC 223.15 38 0Ω Lo1 1 000 pF 22 2nd charge pump 1st N counter latch 100 pF fout1 (Lo1) Lock detection 18-bit 1st A / N counter 1st prescaler 1 651.2 MHz to 1 684.8 MHz VCO1 LPF2 1st R counter latch 35 LPF1 VCC 1 000 pF 26 PSIF 27 PSRF 28 30 31 LD 32 33 Data Clock 5 µF 29 LD Controller 0Ω 47 Ω 560 pF VS Lo2 223.15 MHz VLI SDM00007BEB 7 AN6591FJM ■ Electrical Characteristics at Ta = 25°C (continued) STROBE 34 VOH, VOL, IOH2, IOL2, 10 z 5 µF 14-bit 1st R counter 36 1st charge pump VCC 37 IO 24 23 22 2nd charge pump 1st prescaler 300 kHz 1st phase comparator Lock detection 2nd phase comparator 21 50 kHz 2nd R counter (384) 20 2nd N counter (291) A counter (7) 18-bit 1st A / N counter 38 19 18 2nd prescaler (1 / 16, 1 / 17) 1st N counter latch 39 0Ω IO 40 17 16 100 pF 100 pF 1 kΩ 14 100 pF 1 kΩ 43 13 100 pF 1 kΩ 44 12 5 µF 1 000 pF 42 IO P0 100 pF VMI MIXO 1 000 pF SDM00007BEB VCC2 VLM Lo2 11 10 LIMIN 8 22 nF 7 2 200 100 pF pF 22 nF 5 µF 6 5 4 2 200 pF 100 pF Lo3 RSSI IO 9 100 pF 3 2 1 IO 8 VCC1 1 kΩ 15 φ Σ 41 VAPC/BS VCC1 VCC 1st R counter latch 35 VOH, VOL, IOH1, IOL1, 10 z 25 26 IO 23-bit shift register VCC 1 000 pF 27 28 VIH, VIL, IIH2, IIL2 PSIF 29 VIH, VIL, IIH2, IIL2 PSRF 30 31 LD 32 33 Data Clock VIH, VIL, IIH1, IIL1 VOH, VOL, IOH3, IOL3 VIH, VIL, IIH1, IIL1 VIH, VIL, IIH1, IIL1 2. Test circuit 2 560 pF VS 1.5 V AN6591FJM ■ Terminal Equivalent Circuits Pin No. Equivalent circuit Description 1 I/O RXMIXIN: Reception mixer input pin with an input impedance of approx. 16 kΩ. I RXLOIN: Local input pin. I 1 2 2 3 4 VCC2: Mixer power supply pin. MXO: Mixer output pin. O LMDEC1, 2: Coupling pin for limiter amplifier feedback. Ground this pin through an external capacitor. 4 5 6 5 7 7 6 8 9 LMIN: Limiter amplifier input pin with an input impedance of approx. 330 Ω. I VCC2: Pin to provide power supply to the limiter amplifier and RSSI. LMO: Limiter amplifier output pin. O 9 SDM00007BEB 9 AN6591FJM ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 10 Description 42 I/O TXLO2: Quadrature modulator local input pin I RSO: RSSI output pin with DC output according to the input signal level of the limiter amplifier. O GNDR: Ground pin. 10 11 11 12 13 Q-in: Q signal input pin with the following relationship between the input DC bias and amplitude. 17 I DC bias (V) Amplitude V[p-p] 1.5 14 14 13 0.5 (Both phases) Q-in: Q signal input pin with the following relationship between the input DC bias and amplitude. I DC bias (V) Amplitude V[p-p] 1.5 15 0.5 (Both phases) I-in: I signal input pin with the following relationship between the input DC bias and amplitude. 42 I DC bias (V) Amplitude V[p-p] 1.5 16 16 15 0.5 (Both phases) I-in: I signal input pin with the following relationship between the input DC bias and amplitude. DC bias (V) Amplitude V[p-p] 1.5 10 SDM00007BEB 0.5 (Both phases) I AN6591FJM ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description I/O 17 VCC1: Pin to provide supply voltage to the quadrature modulator. The pin is connected to the built-in band gap regulator, thus providing stable bias voltage without being affected by VCC or temperature changes as much as possible. I 18 GNDM: Ground pin for the quadrature modulator. Keep the grounding surface wide to lower the impedance. 19 2nd prescaler in: 2nd PLL prescaler input pin. I 19 21 GND 2nd CMOS: Ground pin for the 2nd PLL. 22 VCC: Bip power supply pin for the PLL. 26 VCC: 2nd CMOS power supply pin for the PLL. 2nd chargepump out: 2nd PLL charge pump output pin. O 28: 2nd power save in: 29: 1st power save in: 2nd PLL and 1st PLL power save control input pins. I Reference in: Reference signal input pin. I 27 27 28 29 28 29 30 30 SDM00007BEB 11 AN6591FJM ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description 31 I/O Lock detect out: Lock detection output pin. O 32: Clock in: Clock input pin. 33: Serial data in: Data input pin. 34: Strobe in: Strobe input pin. I 31 32 32 33 33 34 34 35 36 GND 1st / 2nd CMOS: 1st and 2nd PLL ground pin. 1st charge pump out: 1st PLL charge pump output pin. O VCC: 1st PLL CMOS power supply pin. 36 37 38 1st prescaler in: 1st PLL prescaler input pin. I TX LO1: Local input pin for the up-mixer. The use of an external balancer is recommended to apply balanced input. I TX LO1R: Local input pin for the up-mixer. The use of an external balancer is recommended to apply balanced input. I 38 39 42 40 39 12 40 SDM00007BEB AN6591FJM ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description 41 I/O APC / BS: Pin used for the battery save of the transmission circuit block and the power control of RF output. Regulator 41 (APC control) VAPC (V) Status 0 to 0.3 Off 1.0 to VCC On (APC control) I The impedance is a minimum of 5 kΩ. 42 43 42 VCC1: Pin to provide power supply to the upmixer and output amplifier circuit. This pin is connected to the built-in stabilized power supply circuit and provides stable bias voltage without being affected by VCC or temperature changes as much as possible. TXO: RF output pin connected to the output amplifier circuit and has emitter follower output. O GNDO: Ground pin for the up-mixer and output amplifier circuit. This pin is a highfrequency ground pin. Therefore, keep the grounding surface wide to lower the impedance. 43 44 SDM00007BEB 13 AN6591FJM ■ Technical Data 1. Serial data interface specifications Carrier data is transferred in 23-bit serial data transfer. The serial data is set at the clock falling edge and latched onto the synthesizer at the clock rising edge. It is necessary to input a single STROBE pulse when the 23-bit serial data transfer is completed. 1) Serial interface of 1st synthesizer 1st synthesizer serial data input format MSB LSB N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 A6 A5 A4 A3 A2 A1 A0 PD X X X TO TC C1 C0 X R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 T1 T0 C1 C0 ←N data input direction fout = (P × N + A) × fin / R Possible set range: 1st A = 0 to 127 or 63, N = 5 to 2 047 (N > A) R = 5 to 16 383 (1) Control bit C0 P X: don't care (2) Test contents C1 1 0 1 1 T0 T1 0 0 1st synthesizer R counter frequency dividing ratio setting 2nd synthesizer R counter output 2nd synthesizer N counter output 0 1 1st synthesizer A / N counter frequency dividing ratio setting 1st synthesizer R counter output 1 0 1st synthesizer N counter output 1 1 (3) Data contents PD Phase comparator polarity selection P Prescaler frequency dividing ratio TC Counter test mode setting TO Output pin test 0 negative 1 positive 128 / 129 LD output normal 64 / 65 Counter output test 2) Serial transfer timing Timing chart Data 22 21 20 19 18 2 t1 t2 0 (t1 , t2 ≥ 50 ns) Clock STROBE 14 1 SDM00007BEB AN6591FJM ■ Technical Data (continued) 2. 2nd synthesizer frequency dividing ratio Set frequency (frequency dividing ratio) fout2 = 233.15 MHz, fr = 50 kHz, (P = 16, N = 291, A = 7, R = 384 fixed) Reference frequency fREFIN = 19.2 MHz MSB LSB N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 1 0 0 0 X X X R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 X X 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 X 1 1 0 X 1 0 X 0 0 1 P 0 0 1 A3 A2 A1 A0 PD 1 0 0 X 0 0 0 X 0 0 0 X 0 X: don't care 3. Unlock detection and LD output specifications 1) The AND of the LD signal (2) of the 1st synthesizer block and the LD signal (3) of the 2nd synthesizer block is output. 2) 1st synthesizer block When the synthesizer block is locked, the LD output level will be high. When the synthesizer block is unlocked, the LD output level will be low. The detection time is 3.3 µs. As for the precision of detection, unlock output turns on if the devided frequency output of the circuit is (52 × 4) ns slower or faster than it should be at the frequency fref of 300 kHz. The lock signal is output in power save mode. 3) 2nd synthesizer block When the synthesizer block is locked, the LD output level will be high. When the synthesizer block is unlocked, the LD output level will be low. The detection time is 20 µs. As for the precision of detection, unlock output turns on if the devided frequency output of the circuit is (52 × 4) ns slower or faster than it should be at the frequency fref of 50 kHz. The lock signal is output in power save mode. 1st synthesizer 2nd synthesizer LD output Lock or power save mode Lock or power save mode High Unlock Lock or power save mode Low Lock or power save mode Unlock Low Unlock Unlock Low 4. Other specifications 1) Clock, Data, and STROBE all are high-active logics. 2) When the IC is turned on, set the IC to power save mode by setting both PS1 and PS2 to low-level. After serial data is input, set the IC to operating mode by setting both PS1 and PS2 to high-level. SDM00007BEB 15 AN6591FJM ■ Technical Data (continued) 3. TX-RX burst / intermittent reception lockup time Lockup time (µs) 450 RX → TX 350 250 TX → RX 255 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Channel (ch) Unless otherwise specified, VCC = 3.0 V, and fREF = 19.2 MHz. The lockup time means converging time into ±1 kHz. 1) Test circuit PLL3V 100 pF 68 pF 15 nH 27 Ω 15 kΩ 0.68 µF 470 Ω Ref. VCC1/2/B CP2 MA2Z331 TCX03V 2.2 kΩ CP1 68 pF 33 pF 1 000 pF 8.2 kΩ AN6591FJM 4 700 pF 47 pF 12 nH 0.68 1 000 µF pF 5.6 kΩ 10 kΩ XN06543 1.5 kΩ 1.5 pF 33 pF 39 pF 22 pF IFIN 1 000 pF 56 pF 1 000 pF 47 Ω 180 Ω RFIN PS1 Clock PS2 Data STROBE Time-98 Data generator VCO ENFVJ1G 1 000 2S03 1 000 pF TCX03V 0.68 µF PLL3V TCX03V (2) At intermittent reception 1.2 s 13.5 ms 1.25 ms 1.25 ms 1.25 ms 1.25 ms PS1 PS2 TCX03V PLL3V RX TX Clock STROBE 27 µs 16 5 600 pF pF 47 Ω 2) Serial control timing (1) At TX-RX burst Data 2.5 pF 680 pF 15.2 µs PS2 PS1 Channel setting 4 ms2 ms 1 ms SDM00007BEB 3.5 ms max. Intermittent AN6591FJM ■ Technical Data (continued) 4. Oscillator frequency by channel (fRFIN) ch fRFIN <TX> (MHz) fRFIN <RX> (MHz) ch fRFIN <TX> (MHz) fRFIN <RX> (MHz) 251 1 660.5 1 649.7 31 1 671.0 1 660.2 252 1 660.8 1 650.0 32 1 671.3 1 660.5 253 1 666.1 1 650.3 33 1 671.6 1 660.8 254 1 666.4 1 650.6 34 1 671.9 1 661.1 255 1 666.7 1 650.9 35 1 672.2 1 661.4 1 1 662.0 1 651.2 36 1 672.5 1 661.7 2 1 662.3 1 651.5 37 1 672.8 1 662.0 3 1 662.6 1 651.8 38 1 673.1 1 662.3 4 1 662.9 1 652.1 39 1 673.4 1 662.6 5 1 663.2 1 652.4 40 1 673.7 1 662.9 6 1 663.5 1 652.7 41 1 674.0 1 663.2 7 1 663.8 1 653.0 42 1 674.3 1 663.5 8 1 664.1 1 653.3 43 1 674.6 1 663.8 9 1 664.4 1 653.6 44 1 674.9 1 664.1 10 1 664.7 1 653.9 45 1 675.2 1 664.4 11 1 665.0 1 654.2 46 1 675.5 1 664.7 12 1 665.3 1 654.5 47 1 675.8 1 665.0 13 1 665.6 1 654.8 48 1 676.1 1 665.3 14 1 665.9 1 655.1 49 1 676.4 1 665.6 15 1 666.2 1 655.4 50 1 676.7 1 665.9 16 1 666.5 1 655.7 51 1 677.0 1 666.2 17 1 666.8 1 656.0 52 1 677.3 1 666.5 18 1 667.1 1 656.3 53 1 677.6 1 666.8 19 1 667.4 1 656.6 54 1 677.9 1 667.1 20 1 667.7 1 656.9 55 1 678.2 1 667.4 21 1 668.0 1 657.2 56 1 678.5 1 667.7 22 1 668.3 1 657.5 57 1 678.8 1 668.0 23 1 668.6 1 657.8 58 1 679.1 1 668.3 24 1 668.9 1 658.1 59 1 679.4 1 668.6 25 1 669.2 1 658.4 60 1 679.7 1 668.9 26 1 669.5 1 658.7 61 1 680.0 1 669.2 27 1 669.8 1 659.0 62 1 680.3 1 669.5 28 1 670.1 1 659.3 63 1 680.6 1 669.8 29 1 670.4 1 659.6 64 1 680.9 1 670.1 30 1 670.7 1 659.9 65 1 681.2 1 670.4 SDM00007BEB 17 AN6591FJM ■ Technical Data (continued) 4. Oscillator frequency by channel (fRFIN) (continued) ch fRFIN <TX> (MHz) fRFIN <RX> (MHz) ch fRFIN <TX> (MHz) fRFIN <RX> (MHz) 66 1 681.5 1 670.7 77 1 684.8 1 674.0 67 1 681.8 1 671.0 78 1 685.1 1 674.3 68 1 682.1 1 671.3 79 1 685.4 1 674.6 69 1 682.4 1 671.6 80 1 685.7 1 674.9 70 1 682.7 1 671.9 81 1 686.0 1 675.2 71 1 683.0 1 672.2 82 1 686.3 1 675.5 72 1 683.3 1 672.5 max. 1 686.3 1 649.7 73 1 683.6 1 672.8 (1st) (2nd) 74 1 683.9 1 673.1 Inter- 1 662.6 233.15 mittent 75 1 684.2 1 673.4 76 1 684.5 1 673.7 5. PD Ta curves of QFN044-P-0606A PD Ta 1.500 Mounted on standard board (glass epoxy: 50 mm × 50 mm × t0.8 mm) Rth(j-a) = 71.8°C/W 1.400 1.392 1.300 Power dissipation PD (W) 1.200 1.100 1.000 0.900 0.800 0.700 0.600 0.500 0.400 0.353 0.300 Independent IC without a heat sink Rth(j-a) = 282.9°C/W 0.200 0.100 0.000 0 25 50 75 100 Ambient temperature Ta (°C) 18 SDM00007BEB 125 AN6591FJM ■ Technical Data (continued) Wideband spurious characteristics 0 20 0 −10 18 −10 16 −20 Transmission output −30 −40 14 12 Adjacent channel at 300 kHz −50 8 × Lo −60 Adjacent channel at 600 kHz −70 Modulation accuracy −80 10 8 6 −30 Spurious (dBm) −20 Modulation accuracy (%) Transmission output level (dBm) / adjacent channel leakage suppression (dBc) / 8 × Lo (dBc) 6. Main characteristics APC control voltage characteristics −40 −50 −60 −70 −80 4 Lo1:1 672.5 MHz, −10 dBm Lo2: 233.15 MHz, −10 dBm 2 I / Q signal DC bias: 1.5 V, amplitude: 500 mV[p-p], PN9-level continuous wave 0 −100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 RLV: 0.0 dBm AT 15 dB RB 1 MHz ST 200 ms VB 1MHz −90 −90 −100 0.6 6 60 600 AN6591FJM Lim. characteristics 120 120 110 110 100 100 90 90 70 25°C 60°C 60 50 40 Lim. output level (dBµ) Mix. output level (dBµ) AN6591FJM Mix.I / O characteristics −20°C 60k 600k 6M 60M 600M 6G (Hz) APC control voltage (V) 80 6k 60°C 25°C −20°C 80 70 60 50 40 30 30 20 20 10 10 0 0 0 0 10 20 30 40 50 60 70 80 90 100 110 120 10 20 30 40 50 60 70 80 90 100 110 120 Limiter input level (dBµ) Mix. input level (dBµ) Note) 1. Unless otherwise specified, the test conditions conform to electrical characteristics. 2. The values in the above are reference values for designing and not guaranteed. SDM00007BEB 19 AN6591FJM ■ Technical Data (continued) 6. Main characteristics (continued) AN6591FJM RSSI characteristics 130 2.0 120 1.8 110 60°C IM / Mix. output level (dBµ) RSSI output level (V) AN6591FJM Mix. characteristics 2.2 1.6 1.4 25°C 1.2 1.0 −20°C 0.8 0.6 0.4 100 Output level 90 80 70 IM 60 50 40 30 20 0.2 10 0.0 0 0 10 20 30 40 50 60 70 80 90 100 110 120 0 Limiter input level (dBµ) 10 20 30 40 50 60 70 80 90 100 110 120 130 Mix. input level (dBµ) AN6591FJM Mix. characteristics 20 18 16 CG Mix. CG (dB) NF (dB) 14 12 10 8 6 4 NF 2 0 −20 −18 −16 −14 −12 −10 −8 −6 −4 −2 0 Local input level (dBm) Note) 1. Unless otherwise specified, the test conditions conform to electrical characteristics. 2. The values in the above are reference values for designing and not guaranteed. 20 SDM00007BEB Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. 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At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd. 2002 JUL