Revised August 2000 100355 Low Power Quad Multiplexer/Latch General Description Features The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable (En) inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routing data from either D0 or D1, the Select inputs can force the outputs LOW for the case where the latch is transparent (both Enables are LOW) and can steer a HIGH signal from either D0 or D1 to an output. The Select inputs can be tied together for applications requiring only that data be steered from either D0 or D1. A positive-going signal on either Enable input latches the outputs. A HIGH signal on the Master Reset (MR) input overrides all the other inputs and forces the Q outputs LOW. All inputs have 50 kΩ pull-down resistors. ■ Greater than 40% power reduction of the 100155 ■ 2000V ESD protection ■ Pin/function compatible with 100155 ■ Voltage compensated operating range = −4.2V to −5.7V ■ Available to industrial grade temperature range Ordering Code: Order Number Package Number 100355PC N24E Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100355QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100355QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP Pin Descriptions Pin Names Description E1, E2 Enable Inputs (Active LOW) S0, S1 Select Inputs MR Master Reset Dna–Dnd Data Inputs Qa–Qd Data Outputs Qa–Qd Complementary Data Outputs © 2000 Fairchild Semiconductor Corporation 28-Pin PLCC DS010147 www.fairchildsemi.com 100355 Low Power Quad Multiplexer/Latch July 1989 100355 Operating Mode Table Controls Truth Table Outputs Inputs Outputs E1 E2 S1 S0 Qn MR E1 E2 S1 S0 H X X X Latched (Note 1) H X X X X X X H L X H X X Latched (Note 1) L L L H H H X L H L L L L D0x L L L H H L X H L L L H L D0x + D1x L L L L L X H L H L L L H L L L L L L X L H L L L H H D1x L L L L H X X H L L L L H L H X L H L L L H L X H L H L L L H L L L H L L H X X X X X Latched (Note 1) L X H X X X X Latched (Note 1) H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Note 1: Stores data present before E went HIGH Logic Diagram www.fairchildsemi.com 2 D1x D0x Qx Qx Storage Temperature (TSTG) VEE Pin Potential to Ground Pin Recommended Operating Conditions −65°C to +150°C +150°C Maximum Junction Temperature (TJ) Case Temperature (TC) −7.0V to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 3) ≥2000V 0°C to +85°C Commercial VEE to +0.5V Input Voltage (DC) 100355 Absolute Maximum Ratings(Note 2) −40°C to +85°C Industrial −5.7V to −4.2V Supply Voltage (VEE) Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 4) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 mV VIN = VIH (Max) Conditions Loading with VOL Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1035 mV VIN = VIH (Min) Loading with VOLC Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal IIL Input LOW Current 0.50 IIH Input HIGH Current for ALL Inputs for ALL Inputs S0, S1 220 E1, E2 350 Dna–Dnd 340 MR IEE Power Supply Current µA VIN = VIL (Min) µA VIN = VIH (Max) mA Inputs Open 430 −87 −40 Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3 www.fairchildsemi.com 100355 Commercial Version (Continued) DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Dna–Dnd to Output TC = 0°C TC = +25°C TC = +85°C Units Conditions Min Max Min Max Min Max 0.60 1.90 0.60 1.90 0.70 2.00 ns 1.00 2.60 1.00 2.60 1.20 2.70 ns 0.80 2.00 0.80 2.00 0.80 2.10 ns 0.80 2.30 0.80 2.30 0.80 2.30 ns Figures 1, 3 0.60 1.40 0.60 1.40 0.60 1.40 ns Figures 1, 2 ns Figure 4 (Transparent Mode) tPLH Propagation Delay tPHL S0, S1 to Output Figures 1, 2 (Transparent Mode) tPLH Propagation Delay tPHL E1, E2 to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time tH Dna–Dnd 0.90 0.90 0.90 S0, S1 1.70 1.70 1.70 MR (Release Time) 1.50 1.50 1.50 Figure 3 Hold Time Dna–Dnd 0.40 0.40 0.40 S0, S1 0.00 0.00 0.00 ns Figure 4 tPW (L) Pulse Width LOW E1, E2 2.00 2.00 2.00 ns Figure 2 tPW (H) Pulse Width HIGH MR 2.00 2.00 2.00 ns Figure 3 www.fairchildsemi.com 4 100355 Commercial Version (Continued) PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Dna–Dnd to Output TC = 0°C TC = +25°C TC = +85°C Units Conditions Min Max Min Max Min Max 0.60 1.70 0.60 1.70 0.70 1.80 ns 1.00 2.40 1.00 2.40 1.20 2.50 ns 0.80 1.80 0.80 1.80 0.80 1.90 ns 0.80 2.10 0.80 2.10 0.80 2.10 ns Figures 1, 3 0.60 1.30 0.60 1.30 0.60 1.30 ns Figures 1, 2 ns Figure 4 (Transparent Mode) tPLH Propagation Delay tPHL S0, S1 to Output Figures 1, 2 (Transparent Mode) tPLH Propagation Delay tPHL E1, E2 to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time tH Dna–Dnd 0.80 0.80 0.80 S0, S1 1.60 1.60 1.60 MR (Release Time) 1.40 1.40 1.40 Figure 3 Hold Time Dna–Dnd 0.30 0.30 0.30 S0, S1 −0.10 −0.10 −0.10 ns Figure 4 tPW (L) Pulse Width LOW E1, E2 2.00 2.00 2.00 ns Figure 2 tPW (H) Pulse Width HIGH MR 2.00 2.00 2.00 ns Figure 3 tOSHL Maximum Skew Common Edge Output-to-Output Variation PLCC only 330 330 330 ps (Note 5) 370 370 370 ps (Note 5) 370 370 370 ps (Note 5) 270 270 270 ps (Note 5) Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC only Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC only Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation PLCC only Data to Output Path Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST ). Parameters tOST and tPS guaranteed by design. 5 www.fairchildsemi.com 100355 Industrial Version PLCC DC Electrical Characteristics (Note 6) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C TC = −40°C Symbol Parameter Min Max TC = 0°C to +85°C Min Max Units Conditions VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH (Max) Loading with VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or VIL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1095 mV VIN = VIH (Min) Loading with VOLC Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal VIL Input LOW Voltage −1830 −1480 1830 1475 mV Guaranteed LOW Signal IIL Input LOW Current 0.50 IIH Input HIGH Current −1035 −1565 for ALL Inputs for ALL Inputs S0, S1 300 220 E1, E2 350 350 Dna–Dnd 340 340 MR IEE 0.50 430 Power Supply Current −87 µA VIN = VIL (Min) µA VIN = VIH (Max) mA Inputs Open 430 −40 −87 −40 Note 6: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Dna–Dnd to Output TC = −40°C TC = +25°C TC = +85°C Units Conditions Min Max Min Max Min Max 0.60 1.70 0.60 1.70 0.70 1.80 ns 1.00 2.40 1.00 2.40 1.20 2.50 ns 0.80 1.80 0.80 1.80 0.80 1.90 ns 0.80 2.10 0.80 2.10 0.80 2.10 ns Figures 1, 3 0.40 1.90 0.60 1.30 0.60 1.30 ns Figures 1, 2 ns Figure 4 (Transparent Mode) tPLH Propagation Delay tPHL S0, S1 to Output Figures 1, 2 (Transparent Mode) tPLH Propagation Delay tPHL E1, E2 to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time tH Dna–Dnd 0.90 0.80 0.80 S0, S1 2.40 1.60 1.60 MR (Release Time) 1.50 1.40 1.40 Figure 3 Hold Time Dna–Dnd 0.40 0.30 0.30 S0, S1 0.00 −0.10 −0.10 ns Figure 4 tPW (L) Pulse Width LOW E1, E2 2.00 2.00 2.00 ns Figure 2 tPW (H) Pulse Width HIGH MR 2.00 2.00 2.00 ns Figure 3 www.fairchildsemi.com 6 100355 Test Circuit Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF Pin numbers shown are for flatpak; for DIP see logic symbol FIGURE 1. AC Test Circuit 7 www.fairchildsemi.com 100355 Switching Waveforms FIGURE 2. Enable Timing FIGURE 3. Reset Timing Notes: tS is the minimum time before the transition of the enable that information must be present at the data input. tH is the minimum time after the transition of the enable that information must remain unchanged at the data input. FIGURE 4. Data Setup and Hold Times www.fairchildsemi.com 8 100355 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 9 www.fairchildsemi.com 100355 Low Power Quad Multiplexer/Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10