Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET DESCRIPTION Monolithic temperature and overload protected logic level power MOSFET in a 5 pin plastic envelope, intended as a low side switch for automotive applications. FEATURES Vertical power DMOS output stage Low on-state resistance Low operating supply current Overtemperature protection Overload protection against short circuit load with drain current limiting Latched overload protection reset by protection supply Protection circuit condition indicated by flag pin Off-state detection of open circuit load indicated by flag pin 5 V logic compatible input level Integral input resistors. ESD protection on all pins Over voltage clamping BUK112-50GL QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Tj RDS(ON) Continuous drain source voltage Continuous drain current Continuous junction temperature Drain-source on-state resistance SYMBOL PARAMETER VPS Protection supply voltage MAX. UNIT 50 12 150 93 V A ˚C mΩ NOM. UNIT 5 V FUNCTIONAL BLOCK DIAGRAM PROTECTION SUPPLY FLAG DRAIN OC LOAD O/V DETECT CLAMP POWER INPUT RIG MOSFET LOGIC AND PROTECTION RIS SOURCE Fig.1. Elements of the TOPFET. PINNING - SOT263 PIN PIN CONFIGURATION DESCRIPTION 1 input 2 flag 3 drain 4 protection supply 5 source D tab TOPFET P F I P 1 2345 leadform 263-01 Fig. 2. tab SYMBOL S Fig. 3. drain September 1996 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VIS = 0 V - 50 V A A mA mA mA Continuous voltage VDS Drain source voltage1 Continuous currents ID Drain current VPS = 5 V; Tmb = 25 ˚C - II IF IP Input current Flag current Protection supply current VPS = 0 V; Tmb = 94 ˚C - -5 -5 -5 self limited 12 5 5 5 - 52 W -55 - 175 150 260 ˚C ˚C ˚C MIN. MAX. UNIT Thermal Ptot Total power dissipation Tmb = 25 ˚C Tstg Tj Tsold Storage temperature Junction temperature2 Lead temperature continuous during soldering ESD LIMITING VALUES SYMBOL PARAMETER CONDITIONS Electrostatic discharge capacitor voltages Human body model; C = 100 pF; R = 1.5 kΩ VC1 Drain to source - 4.5 kV VC2 Input, flag or protection to source - 2 kV OVERLOAD PROTECTION LIMITING VALUE With the protection supply connected, TOPFET can protect itself from two types of overload short circuit load and overtemperature. SYMBOL VPSP For overload conditions an n-MOS transistor turns on between the gate and source to quickly discharge the power MOSFET gate capacitance. PARAMETER CONDITIONS 3 Protection supply voltage for valid protection The drain current is limited to reduce dissipation in case of short circuit load. Refer to OVERLOAD CHARACTERISTICS. MIN. MAX. UNIT 4.5 - V OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT EDSM Non-repetitive clamping energy IDM = 6 A; Tmb = 25˚C - 200 mJ EDRM Repetitive clamping energy IDM = 3.1 A; VDD ≤ 20 V; Tmb ≤ 120˚C; f = 250 Hz - 20 mJ 1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch. 3 The minimum supply voltage required for correct operation of the overload protection circuits. September 1996 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT - - 2.38 K/W - 60 - K/W MIN. TYP. MAX. UNIT 50 - 70 V 50 60 70 V - 0.5 1 10 10 20 100 µA µA µA - 70 135 93 165 mΩ mΩ MIN. TYP. MAX. UNIT Thermal resistance Rth j-mb Junction to mounting base Rth j-a Junction to ambient in free air OUTPUT CHARACTERISTICS Tmb = 25 ˚C; VPS = 0 V unless otherwise specified SYMBOL PARAMETER CONDITIONS Off-state V(CL)DSS Drain-source clamping voltage ID = 10 mA; -40˚C ≤ Tmb ≤ 150˚C IDM = 0.75 A; tp ≤ 300 µs; δ ≤ 0.01 IDSS RDS(ON) 1 Drain-source leakage current VIS = 0 V; VDS = 13 V VDS = 50 V Tmb = 125 ˚C; VDS = 40 V On-state tp ≤ 300 µs; δ ≤ 0.01 Drain-source on-resistance IDM = 6 A; VIS = 4.4 V; VPS = 4.5 V Tmb = 150 ˚C INPUT CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS Normal operation VIS(TO) Input threshold voltage VDS = 13 V; VPS = 0 V; ID = 1 mA -40˚C ≤ Tmb ≤ 150˚C 1 0.5 1.5 - 2 2.5 V V IIS Input current VIS = 5 V -40˚C ≤ Tmb ≤ 150˚C 200 350 500 µA V(CL)IS Input clamping voltage II = 1.5 mA 6 7.1 - V RIG Internal series resistance to gate of power MOSFET - 1.5 - kΩ 1.5 3.2 4 mA MIN. TYP. MAX. UNIT Overload protection latched IISL Input current VPS = 5 V; VIS = 5 V REVERSE CHARACTERISTICS Tmb = 25 ˚C SYMBOL PARAMETER CONDITIONS 2 -VDS Reverse drain voltage -ID = 6 A - 0.8 - V -VIS Reverse input voltage -II = 5 mA - 0.7 - V -VPS Reverse protection pin voltage -IP = 5 mA - 0.7 - V -VFS Reverse flag voltage -IF = 5 mA - 0.7 - V 1 The drain current required for open circuit load detection is switched off when there is no protection supply, in order to ensure a low off-state quiescent current. Refer to OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS. 2 Protection functions are disabled during reverse conduction. September 1996 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL PROTECTION SUPPLY CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT - 330 - 400 450 µA µA 6 7.1 - V -40˚C ≤ Tmb ≤ 150˚C 1.5 2.1 - 3 V V -40˚C ≤ Tmb ≤ 150˚C - 25 - 150 µs µs MIN. TYP. MAX. UNIT 0.5 1.4 2 mA 0.4 1.1 - mA - 1.2 - V Normal operation or protection latched IPS, IPSL Supply current VPS = 4.5 V V(CL)PS Clamping voltage IP = 1.5 mA -40˚C ≤ Tmb ≤ 150˚C Overload protection latched VPSR Reset voltage t pr Reset time VPS = 0 V OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS An open circuit load condition can be detected while the TOPFET is in the off-state. -40˚C ≤ Tmb ≤ 150˚C; VPS = 5 V; VDS = 13 V unless otherwise specified SYMBOL PARAMETER CONDITIONS 1 IDSP Off-state drain current VIS = 0 V IDSF Off-state drain threshold current VIS = 0 V; IF = 100 µA VISF Input threshold voltage2 IF = 100 µA; ID = 100 µA; Tmb = 25 ˚C TRUTH TABLE For normal, open-circuit load and overload conditions or inadequate protection supply voltage. CONDITION PROTECTION INPUT FLAG OUTPUT Normal on-state 1 1 0 1 Normal off-state 1 0 0 0 Open circuit load 1 1 0 1 Open circuit load 1 0 1 0 Short circuit load 1 1 1 0 Over temperature 1 X 1 0 Low protection supply voltage 0 1 1 1 Low protection supply voltage 0 0 1 0 For protection ‘0’ equals low, ‘1’ equals high. For input ‘0’ equals low, ‘1’ equals high, ‘X’ equals don’t care. For flag ‘0’ equals low, ‘1’ equals open or high. For output switch ‘0’ equals off, ‘1’ equals on. 1 The drain source current which flows when the protection supply is high and the input is low. 2 For open circuit load indication, VIS must be less than VISF. September 1996 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL OVERLOAD CHARACTERISTICS Tmb = 25 ˚C; VPS = 5 V unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. ID Short circuit load protection Drain current limiting VIS = 5 V VDS = 13 V PD(TO) EDSC Overload power threshold1 Characteristic energy for protection to operate which determines trip time2 IDM Peak drain current3 VDD = 13 V; RL ≤ 10 mΩ -40˚C ≤ Tmb ≤ 150˚C TYP. MAX. UNIT 12 24 36 A - 100 200 - W mJ - 45 - A 150 185 215 ˚C MIN. TYP. MAX. UNIT - 0.7 - V - - 0.9 V - 10 - mA - 0.1 1 1 10 µA µA 6 6.9 - V 2.5 3 4 V 2 - 4 V - 50 - kΩ Overtemperature protection Tj(TO) Threshold temperature ID ≥ 1 A FLAG CHARACTERISTICS The flag is an open drain transistor which requires an external pull-up circuit. Tmb = 25 ˚C unless otherwise specified SYMBOL VFSF PARAMETER CONDITIONS Flag ‘low’ normal operation; VPS = 5 V Flag voltage IF = 100 µA -40˚C ≤ Tmb ≤ 150˚C Flag saturation current VFS = 5 V Flag ‘high’ overload or fault IFSO Flag leakage current VFS = 5 V V(CL)FS Flag clamping voltage IF = 100 µA VPSF Protection supply threshold voltage4 IF = 100 µA; VDS = 5 V IFSF Tmb = 150˚C -40˚C ≤ Tmb ≤ 150˚C Application information RF Suitable external pull-up resistance VFF = 5 V 1 Refer to figure 15. 2 Trip time td sc ≈ EDSC / [ PD - PD(TO) ]. Refer also to figure 15. 3 For short circuit load connected after turn-on. 4 When VPS is less than VPSF the flag pin indicates low protection supply voltage. Refer to TRUTH TABLE. September 1996 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL SWITCHING CHARACTERISTICS Tmb = 25 ˚C SYMBOL PARAMETER CONDITIONS Resistive load RL = 4 Ω; ID = 3 A td on Turn-on delay time VIS: 0 V ⇒ 5 V tr Rise time td off Turn-off delay time tf Fall time VIS: 5 V ⇒ 0 V Inductive load ID = 3 A; VDD = 13 V; with freewheel diode td on Turn-on delay time VIS: 0 V ⇒ 5 V tr Rise time td off Turn-off delay time tf Fall time September 1996 VIS: 5 V ⇒ 0 V 6 MIN. TYP. MAX. UNIT - 0.6 - µs - 2.8 - µs - 3.5 - µs - 3.2 - µs - 0.9 - µs - 1.2 - µs - 6.7 - µs - 0.6 - µs Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL VIN VIS (input) 0V VCC VGS (internal) 0V VDS(OFF) SHORT CIRCUIT FAULT VDS (output) VDS(ON) PROTECTION RESET VCC PROTECTION RESET LOSS OF PROT’N SUPPLY VPS (protection supply) 0V VCC VFS (flag) 0V NORMAL FAULT NORMAL FAULT NORMAL OPERATION CONDITION OPERATION CONDITION OPERATION Fig. 4. Waveforms for normal and fault conditions. VIN VIS (input) 0V VCC VGS (internal) 0V VDS(OFF) VDS (output) VDS(ON) VCC VPS (protection supply) 0V VCC VFS (flag) 0V NORMAL OPEN NORMAL OPEN NORMAL OPERATION LOAD OPERATION LOAD OPERATION Fig. 5. Waveforms for normal and open circuit load. September 1996 7 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET 120 BUK112-50GL Normalised Power Derating PD% 50 ID / A BUK112-50GL WITHOUT PROTECTION 110 VIS / V = 100 90 40 7 6 80 70 30 60 50 20 5 40 4 30 10 20 10 0 0 20 40 60 80 100 Tmb / C 120 0 140 Fig.6. Normalised limiting power dissipation. PD% = 100⋅PD/PD(25˚C) = f(Tmb) 14 ID / A 3 0 5 10 VDS / V 15 20 Fig.9. Typical output characteristics, Tj = 25˚C. ID = f(VDS); tp = 250 µs; VPS = 0 V; parameter VIS BUK112-50GL 30 ID / A BUK112-50GL WITHOUT PROTECTION 12 VPS = 0 V 25 10 20 VPS = 5 V 8 15 CURRENT LIMITING 6 10 4 5 2 0 WITH PROTECTION 0 50 100 0 150 0 1 2 Tmb / C Fig.7. Continuous limiting drain current. ID = f(Tmb); conditions: VIS = 5 V; VPS = 5 V 25 ID / A WITH PROTECTION 3 4 5 VDS / V Fig.10. Typical on-state characteristics, Tj = 25˚C. ID = f(VDS); VIS = 5 V; tp = 250 µs; parameter VPS BUK112-50GL VIS / V = 20 200 RDS(ON) / mOhm BUK112-50GL 7 6 150 5 15 CURRENT LIMITING 4 TYP. 100 10 0 50 3 5 0 5 10 15 VDS / V 20 25 0 30 Fig.8. Typical output characteristics, Tj = 25˚C. ID = f(VDS); tp = 250 µs; VPS = 5 V; parameter VIS September 1996 0 1 2 3 4 VIS / V 5 6 7 8 Fig.11. Typical on-state resistance, Tj = 25˚C. RDS(ON) = f(VIS); tp = 250 µs; parameter VIS 8 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET a BUK112-50GL Normalised RDS(ON) = f(Tj) 5 1 / [td sc / ms] BUK112-50GL RECIPROCAL TRIP TIME 1.5 4 3 1.0 intercept = PD(TO) 1/slope = EDSC 2 0.5 1 0 OVERLOAD DISSIPATION -60 -40 -20 0 20 40 60 Tj / C 80 0 100 120 140 Fig.12. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25˚C = f(Tj); ID = 6 A; VIS ≥ 4.4 V 50 ID / A 200 400 600 PD / W 800 1000 1200 Fig.15. Typical reciprocal overload trip time. 1/td sc = f(PD); conditions: VPS = 5 V, Tmb = 25˚C BUK112-50GL 500 VPS = 0 V 40 0 ESC(TO) / mJ BUK112-50GL 400 30 300 20 200 TYP. VPS = 5 V 10 0 100 0 1 2 3 4 VIS / V 5 6 7 0 8 Fig.13. Typical transfer characteristics, Tj = 25˚C. ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 µs 30 ID / A VIS / V = 50 100 Tmb / C 150 200 Fig.16. Typical overload protection energy. ESC(TO) = f(Tmb); VDD = 13 V; VPS = 5 V, VIS = 5 V BUK112-50GL 25 0 210 7 Tj(TO) / C BUK112-50GL 200 6 5 20 190 4.4 15 10 170 5 0 TYP. 180 4 4 5 6 VPS / V 7 150 8 3 4 5 6 7 8 VPS / V Fig.14. Typical output current limiting, Tj = 25˚C. ID = f(VPS); tp = 250 µs; VDS = 10 V; parameter VIS September 1996 VPSP MIN. 160 VPSP MIN. Fig.17. Typical overtemperature protection threshold. Tj(TO) = f(VPS); VIS = 5 V; ID ≥ 1 A 9 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET 2 BUK112-50GL II / mA BUK112-50GL 2 1.5 1.5 1 1 0.5 0.5 0 0 0 1 2 3 4 VIS / V 5 6 7 8 IISL / mA 0 BUK112-50GL 1 2 3 4 VPS / V 5 6 7 8 Fig.21. Typical protection supply characteristics. IP = f(VPS); normal or overload operation; Tj = 25˚C Fig.18. Typical DC input characteristic. II = f(VIS) normal operation; Tj = 25˚C 8 IP / mA BUK112-50GL 2 IF / mA BUK112-50GL 7 1.5 6 5 1 4 3 0.5 2 1 0 0 0 1 2 3 4 VIS / V 5 6 7 8 Fig.19. Typical DC input characteristic, Tj = 25˚C. IISL = f(VIS) overload protection latched; VPS = 5 V 0 1 2 3 4 VFS / V 5 6 7 8 Fig.22. Typical flag high characteristic, Tj = 25˚C. IF = f(VFS); refer to TRUTH TABLE VIS(TO) / V 200 IF / uA BUK112-50GL max. 2 150 typ. 100 min. 1 50 0 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.20. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V September 1996 0 0.1 0.2 0.3 0.4 VFS / F 0.5 0.6 0.7 0.8 Fig.23. Typical flag low characteristic, Tj = 25˚C. IF = f(VFS); VPS = 5 V; refer to TRUTH TABLE 10 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET 20 BUK112-50GL IF / mA BUK112-50GL VPSR / V 3 15 2.5 10 2 5 1.5 BUK112-50GL typ. 0 0 1 2 3 4 5 VFS / V 6 7 8 1 -50 9 VFSF / V 50 100 150 200 Tj / C Fig.27. Protection supply reset voltage. VPSR = f(Tj) Fig.24. Typical flag saturation current, Tj = 25˚C. IF = f(VFS); flag ’low’; external RF = 0 kΩ; VPS = 5 V 1 0 BUK112-50GL 600 IP / uA BUK112-50GL 500 0.8 400 0.6 300 0.4 200 0.2 100 0 -50 0 50 100 150 0 -50 200 0 50 Fig.25. Typical flag low voltage. VFSF = f(Tj); VPS = 5 V; VIS = 5 V; VDS = 0 V 4 100 150 200 Tmb / C Tj / C VPSF / V Fig.28. Typical protection supply current. IP = f(Tj); VPS = 4.5 V BUK112-50GL 40 IS / A BUK112-50GL 30 3.5 typ. 3 20 2.5 10 2 -50 0 50 100 150 0 200 Tj / C Fig.26. Protection supply threshold voltage. VPSF = f(Tj); condition: VDS = 5 V September 1996 0 0.2 0.4 0.6 0.8 VSD / V 1 1.2 1.4 Fig.29. Typical reverse diode current, Tj = 25˚C. IS = f(VSD); conditions: VIS = 0 V; tp = 250 µs 11 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL ID / A 12 BUK112-50GL 5 ID / mA BUK112-50GL OVERVOLTAGE CLAMPING 10 4 8 3 OPEN CIRCUIT LOAD DETECTION 6 2 4 VPS = 5 V IDSP VPS = 0 V IDSS 30 40 VDS / V 50 1 2 IDSF 0 50 55 60 VIS / V 65 0 70 10 20 60 70 Fig.33. Typical off-state characteristics, Tj = 25˚C. ID = f(VDS); VIS = 0 V; parameter VPS Fig.30. Typical clamping characteristics, 25˚C. ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs EDSM% 120 0 2 IDSP & IDSF / mA BUK112-50GL 110 100 IDSP 1.5 90 IDSF 80 70 1 60 50 40 0.5 30 20 10 0 0 0 20 40 60 80 Tmb / C 100 120 0 140 V(CL)DSP 2 VDS VDD + 6 8 IDSP & IDSF / mA BUK112-50GL VDD 1.5 L ID 4 VPS / V Fig.34. Typical open circuit load detect currents. IDSP & IDSF = f(VPS); VIS = 0 V; VDS ≥ 5 V; Tj = 25˚C Fig.31. Normalised limiting clamping energy. EDSM% = f(Tmb); conditions: ID = 6 A 0 2 IDSP VDS + VPS 0 VIS - D RF TOPFET P F I 0 1 IDSF -ID/100 D.U.T. P 0.5 S R 01 shunt 0 -50 50 100 150 200 Tmb / C Fig.32. Clamping energy test circuit. EDSM = 0.5 ⋅ LID2 ⋅ V(CL)DSS /(V(CL)DSS − VDD ) September 1996 0 Fig.35. Typical open circuit load detect currents. IDSP & IDSF = f(Tj); VPS = 5 V; VIS = 0 V 12 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET 1 mA BUK112-50GL Idss 10 BUK112-50GL Zth / (K/W) D= 100 uA 0.5 1 0.2 10 uA 0.1 typ. 0.05 0.1 1 uA 0.02 PD tp D= tp T 0 0.01 1E-07 100 nA 0 20 40 60 80 Tj / C 100 120 140 Fig.36. Typical off-state leakage current. IDSS = f(Tj); Conditions: VDS = 40 V; VIS = 0 V. 100 ID & IDM / A 1E-05 1E-03 t/s 1E-01 1E+01 Fig.38. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T BUK112-50GL ID t T 10 nF Coss BUK112-50GL tp = S/ ) ON D =V 10 us S( RD 100 us 10 DC 1 nF 1 ms 10 ms Overload protection characteristics not shown. 100 ms 1 1 10 VDS / V 100 pF 100 10 20 30 40 50 VDS / V Fig.37. Safe operating area, VPS = 0 V, Tmb = 25˚C. ID & IDM = f(VDS); IDM single pulse; parameter tp September 1996 0 Fig.39. Typical output capacitance. Coss = f(VDS); conditions: VIS = 0 V; f = 1 MHz 13 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL APPLICATION INFORMATION From main control loop Take input low Wait typ 15 us no Return to main control loop Is Flag High? yes Wait for cooling Wait >= 1 min RESET Take prot’n supply low Wait >= 150 us Take prot’n supply high Wait typ 15 us yes Is Flag High? no Take input high Wait typ 15 us yes Is Flag High? no Take input low Take input low Record fault Record Fault Record Fault S/C or over temp. Open load Low prot’n supply Fig. 40. Possible fault diagnosis procedure. September 1996 14 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL MECHANICAL DATA Dimensions in mm 4.5 max Net Mass: 2 g 10.3 max 1.3 3.6 2.8 5.9 min mounting base 15.8 max 5 m in 2.4 max R 0. (2) 3.5 max not tinned 5.6 9.75 0. 5 0.6 min (4 x) 0.6 R 1 2 3 4 5 in 5 m 0.5 (1) 1.7 2.4 4.5 (4 x) 0.4 (1) M 0.9 max 8.2 (5 x) NOTES (1) (2) positional accuracy of the terminals is controlled in this zone only. terminal dimensions in this zone are uncontrolled. Fig.41. SOT263 leadform 263-01; pin 3 connected to mounting base. Note 1. Refer to mounting instructions for TO220 envelopes. 2. Epoxy meets UL94 V0 at 1/8". September 1996 15 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK112-50GL DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September 1996 16 Rev 1.000